llvm-native-core 0.1.6

//! X86 SelectionDAG — complete DAG building, combining, legalization,
//! and DAG-to-DAG instruction selection for the X86 target.
//!
//! Clean-room behavioral reconstruction from:
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual
//! - AMD64 Architecture Programmer's Manual
//! - X86-64 ABI (System V and Microsoft conventions)
//! - LLVM X86ISelLowering and X86DAGToDAGISel behavioral patterns
//!
//! ## Architecture
//! ```text
//! LLVM IR → X86DAGBuilder → X86SelectionDAG
//!                           ├── X86DAGCombine
//!                           ├── X86DAGLegalize
//!                           └── X86DAGToDAGISel → MachineInstr (via X86InstrEmitter)
//! ```
//!
//! ## Modules / Sections
//! 1. `X86ISD` — X86-specific SDNode opcodes
//! 2. `X86DAGNode` — X86-specific node types (CMP, TEST, SETCC, etc.)
//! 3. `X86SelectionDAG` — SelectionDAG wrapper for X86
//! 4. `X86DAGBuilder` — DAG construction from LLVM IR
//! 5. `X86DAGCombine` — Target-specific DAG combining patterns
//! 6. `X86DAGLegalize` — Type/operation legalization
//! 7. `X86DAGToDAGISel` — Pattern-based DAG-to-DAG instruction selection
//! 8. `X86SchedModel` — Node scheduling model
//! 9. `X86InstrEmitter` — Machine instruction emission from DAG

use crate::codegen::{MachineBasicBlock, MachineFunction, MachineInstr, MachineOperand};
use crate::selection_dag::dag_builder::SelectionDAGBuilder;
use crate::selection_dag::dag_combine::DAGCombiner;
use crate::selection_dag::legalize_ops::{
    OpLegalizeAction, OperationLegalizer, PromoteAction, TargetLegalizer,
};
use crate::selection_dag::legalize_types::{LegalizeAction, TypeActionMap, TypeLegalizer};
use crate::selection_dag::sd_node::{
    EVTKind, SDNode, SDNodeFlags, SDOpcode, SDValue, SelectionDAG, EVT, MVT,
};
use crate::types::Type;
use crate::value::ValueRef;
use crate::x86::{
    x86_calling_convention::X86CallingConvention,
    x86_instr_info::{
        OperandType, X86InstrDesc, X86InstrInfo, X86MemOperand, X86Opcode, X86Operand, X86SchedInfo,
    },
    x86_register_info::X86RegisterInfo,
    x86_schedule_model::{
        instruction_latency, instruction_resources, instruction_uops, lookup_itinerary,
        InstrItinerary, ProcResource, SchedMachineModel, SchedModel, X86SchedModelKind,
    },
    x86_subtarget::X86Subtarget,
};

use std::collections::HashMap;

// ============================================================================
// 1. X86ISD — X86-specific SelectionDAG opcodes
// ============================================================================

/// X86-specific SelectionDAG opcodes.
///
/// These opcodes represent operations that are specific to the X86 ISA
/// and don't have a direct counterpart in the generic SDOpcode enum.
/// Nodes with these opcodes have `is_target_node = true`.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86ISD {
    // ---- Comparison ----
    /// Integer comparison (SUB-based, sets EFLAGS)
    Cmp,
    /// TEST-based comparison (AND-based, sets EFLAGS)
    Test,
    /// Floating-point comparison (UCOMISS/UCOMISD-based)
    FCmp,
    /// Conditional set (SETcc)
    SetCC,
    /// Conditional move (CMOVcc)
    CMov,

    // ---- Bit Operations ----
    /// Bit-test instruction (BT)
    BitTest,
    /// Bit-test and set (BTS)
    BitTestAndSet,
    /// Bit-test and reset (BTR)
    BitTestAndReset,
    /// Bit-test and complement (BTC)
    BitTestAndComplement,

    // ---- Shift / Rotate ----
    /// Double-precision shift left (SHLD)
    Shld,
    /// Double-precision shift right (SHRD)
    Shrd,

    // ---- Division ----
    /// X86 unsigned division (DIV — produces quotient+remainder in EDX:EAX)
    UDivRem,
    /// X86 signed division (IDIV)
    SDivRem,

    // ---- Multiply ----
    /// Multiply that produces high bits (MUL/IMUL hi part)
    MulHW,
    /// Unsigned multiply high
    UMulH,

    // ---- String Operations ----
    /// REP MOVS (memcpy)
    RepMovs,
    /// REP STOS (memset)
    RepStos,

    // ---- Call / Return ----
    /// X86 call sequence (chain, callee, args... → chain, glue)
    Call,
    /// X86 return (flag, chain, retval → chain)
    Ret,
    /// X86 tail call
    TailCall,

    // ---- Frame ----
    /// X86 frame address (load from frame index)
    FrameAddr,
    /// X86 return address
    RetAddr,

    // ---- Addressing ----
    /// LEA-based wrapper around add for address calculation
    LeaAddr,
    /// Global base reg (for PIC)
    GlobalBaseReg,

    // ---- Overflow ----
    /// X86 add with carry (ADC)
    AddCarry,
    /// X86 subtract with borrow (SBB)
    SubBorrow,

    // ---- Vector ----
    /// Load from memory and broadcast to vector (VBROADCAST)
    VBroadcast,
    /// Load from memory and broadcast to vector (load + splat)
    VBroadcastLoad,
    /// Packed scalar to vector (MOVD/MOVQ + insert)
    MovdToVec,
    /// Extract from vector to GPR (PEXTR)
    VecExtract,
    /// Insert into vector from GPR (PINSR)
    VecInsert,
    /// Packed shuffle (SHUFPS, SHUFPD)
    VShuffle,
    /// Unpack low (UNPCKLPS/UNPCKLPD)
    Unpckl,
    /// Unpack high (UNPCKHPS/UNPCKHPD)
    Unpckh,
    /// Horizontal add (HADDPS/HADDPD)
    HAdd,
    /// Horizontal sub (HSUBPS/HSUBPD)
    HSub,
    /// Add/sub packed (ADDSUBPS/ADDSUBPD)
    AddSub,

    // ---- FMA ----
    /// Fused multiply-add (VFMADD*)
    Fmadd,
    /// Fused multiply-sub (VFMSUB*)
    Fmsub,
    /// Fused negate multiply-add (VFNMADD*)
    Fnmadd,
    /// Fused negate multiply-sub (VFNMSUB*)
    Fnmsub,
    /// Fused multiply add/sub interleaved (VFMADDSUB*)
    Fmaddsub,

    // ---- Mask (AVX-512) ----
    /// Mask register operation (KADD*, KAND*, etc.)
    MaskOp,
    /// Masked vector operation
    MaskedOp,

    // ---- Gather/Scatter (AVX-512) ----
    /// Gather (VPGATHER* / VGATHER*)
    Gather,
    /// Scatter (VPSCATTER* / VSCATTER*)
    Scatter,

    // ---- Compression/Expansion (AVX-512 VBMI2) ----
    /// Compress (VPCOMPRESS* / VCOMPRESS*)
    Compress,
    /// Expand (VPEXPAND* / VEXPAND*)
    Expand,

    // ---- Misc ----
    /// EH_RETURN (exception handling return)
    EhReturn,
    /// TLS address calculation
    TlsAddr,
    /// Wrapper node for X86-specific patterns
    Wrapper,
    /// Wrapper for RIP-relative addressing
    WrapperRIP,
}

impl X86ISD {
    /// Get a human-readable string name.
    pub fn as_str(&self) -> &'static str {
        match self {
            X86ISD::Cmp => "X86ISD::Cmp",
            X86ISD::Test => "X86ISD::Test",
            X86ISD::FCmp => "X86ISD::FCmp",
            X86ISD::SetCC => "X86ISD::SetCC",
            X86ISD::CMov => "X86ISD::CMov",
            X86ISD::BitTest => "X86ISD::BitTest",
            X86ISD::BitTestAndSet => "X86ISD::BitTestAndSet",
            X86ISD::BitTestAndReset => "X86ISD::BitTestAndReset",
            X86ISD::BitTestAndComplement => "X86ISD::BitTestAndComplement",
            X86ISD::Shld => "X86ISD::Shld",
            X86ISD::Shrd => "X86ISD::Shrd",
            X86ISD::UDivRem => "X86ISD::UDivRem",
            X86ISD::SDivRem => "X86ISD::SDivRem",
            X86ISD::MulHW => "X86ISD::MulHW",
            X86ISD::UMulH => "X86ISD::UMulH",
            X86ISD::RepMovs => "X86ISD::RepMovs",
            X86ISD::RepStos => "X86ISD::RepStos",
            X86ISD::Call => "X86ISD::Call",
            X86ISD::Ret => "X86ISD::Ret",
            X86ISD::TailCall => "X86ISD::TailCall",
            X86ISD::FrameAddr => "X86ISD::FrameAddr",
            X86ISD::RetAddr => "X86ISD::RetAddr",
            X86ISD::LeaAddr => "X86ISD::LeaAddr",
            X86ISD::GlobalBaseReg => "X86ISD::GlobalBaseReg",
            X86ISD::AddCarry => "X86ISD::AddCarry",
            X86ISD::SubBorrow => "X86ISD::SubBorrow",
            X86ISD::VBroadcast => "X86ISD::VBroadcast",
            X86ISD::VBroadcastLoad => "X86ISD::VBroadcastLoad",
            X86ISD::MovdToVec => "X86ISD::MovdToVec",
            X86ISD::VecExtract => "X86ISD::VecExtract",
            X86ISD::VecInsert => "X86ISD::VecInsert",
            X86ISD::VShuffle => "X86ISD::VShuffle",
            X86ISD::Unpckl => "X86ISD::Unpckl",
            X86ISD::Unpckh => "X86ISD::Unpckh",
            X86ISD::HAdd => "X86ISD::HAdd",
            X86ISD::HSub => "X86ISD::HSub",
            X86ISD::AddSub => "X86ISD::AddSub",
            X86ISD::Fmadd => "X86ISD::Fmadd",
            X86ISD::Fmsub => "X86ISD::Fmsub",
            X86ISD::Fnmadd => "X86ISD::Fnmadd",
            X86ISD::Fnmsub => "X86ISD::Fnmsub",
            X86ISD::Fmaddsub => "X86ISD::Fmaddsub",
            X86ISD::MaskOp => "X86ISD::MaskOp",
            X86ISD::MaskedOp => "X86ISD::MaskedOp",
            X86ISD::Gather => "X86ISD::Gather",
            X86ISD::Scatter => "X86ISD::Scatter",
            X86ISD::Compress => "X86ISD::Compress",
            X86ISD::Expand => "X86ISD::Expand",
            X86ISD::EhReturn => "X86ISD::EhReturn",
            X86ISD::TlsAddr => "X86ISD::TlsAddr",
            X86ISD::Wrapper => "X86ISD::Wrapper",
            X86ISD::WrapperRIP => "X86ISD::WrapperRIP",
        }
    }

    /// Whether this opcode represents a comparison.
    pub fn is_comparison(&self) -> bool {
        matches!(self, X86ISD::Cmp | X86ISD::Test | X86ISD::FCmp)
    }

    /// Whether this opcode sets EFLAGS.
    pub fn sets_flags(&self) -> bool {
        matches!(
            self,
            X86ISD::Cmp | X86ISD::Test | X86ISD::FCmp | X86ISD::AddCarry | X86ISD::SubBorrow
        )
    }

    /// Convert to an X86Opcode where there's a direct mapping.
    pub fn to_x86_opcode(&self) -> Option<X86Opcode> {
        match self {
            X86ISD::Cmp => Some(X86Opcode::CMP),
            X86ISD::Test => Some(X86Opcode::TEST),
            X86ISD::RepMovs => Some(X86Opcode::MOVSB),
            X86ISD::RepStos => Some(X86Opcode::STOSB),
            X86ISD::Shld => Some(X86Opcode::SHLD),
            X86ISD::Shrd => Some(X86Opcode::SHRD),
            X86ISD::AddCarry => Some(X86Opcode::ADC),
            X86ISD::SubBorrow => Some(X86Opcode::SBB),
            _ => None,
        }
    }
}

// ============================================================================
// 2. X86DAGNode — X86-specific SDNode extensions
// ============================================================================

/// A wrapper for an SDNode with X86-specific metadata.
///
/// In LLVM, X86 target nodes carry additional information such as
/// the X86ISD opcode, condition codes, addressing modes, etc.
#[derive(Debug, Clone)]
pub struct X86DAGNode {
    /// The underlying generic SDNode
    pub node: SDNode,
    /// X86-specific opcode (if this is a target node)
    pub x86_opcode: Option<X86ISD>,
    /// Condition code for comparison nodes
    pub condition_code: Option<X86CondCode>,
    /// Addressing mode for memory nodes
    pub addressing_mode: Option<X86AddressMode>,
    /// Memory operand descriptor
    pub mem_operand: Option<X86MemOperand>,
    /// Target constant for immediate folding
    pub target_constant: Option<i64>,
}

/// X86 condition codes (EFLAGS conditions).
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86CondCode {
    /// Overflow (OF=1)
    O,
    /// No overflow (OF=0)
    NO,
    /// Below / Carry (CF=1)
    B,
    /// Above or equal / No carry (CF=0)
    AE,
    /// Equal / Zero (ZF=1)
    E,
    /// Not equal / Not zero (ZF=0)
    NE,
    /// Below or equal (CF=1 or ZF=1)
    BE,
    /// Above (CF=0 and ZF=0)
    A,
    /// Sign (SF=1)
    S,
    /// Not sign (SF=0)
    NS,
    /// Parity (PF=1)
    P,
    /// Not parity (PF=0)
    NP,
    /// Less (SF≠OF)
    L,
    /// Greater or equal (SF=OF)
    GE,
    /// Less or equal (ZF=1 or SF≠OF)
    LE,
    /// Greater (ZF=0 and SF=OF)
    G,
}

impl X86CondCode {
    /// Get the mnemonic suffix for this condition code.
    pub fn as_str(&self) -> &'static str {
        match self {
            X86CondCode::O => "o",
            X86CondCode::NO => "no",
            X86CondCode::B => "b",
            X86CondCode::AE => "ae",
            X86CondCode::E => "e",
            X86CondCode::NE => "ne",
            X86CondCode::BE => "be",
            X86CondCode::A => "a",
            X86CondCode::S => "s",
            X86CondCode::NS => "ns",
            X86CondCode::P => "p",
            X86CondCode::NP => "np",
            X86CondCode::L => "l",
            X86CondCode::GE => "ge",
            X86CondCode::LE => "le",
            X86CondCode::G => "g",
        }
    }

    /// Get the complementary condition code.
    pub fn complement(&self) -> X86CondCode {
        match self {
            X86CondCode::O => X86CondCode::NO,
            X86CondCode::NO => X86CondCode::O,
            X86CondCode::B => X86CondCode::AE,
            X86CondCode::AE => X86CondCode::B,
            X86CondCode::E => X86CondCode::NE,
            X86CondCode::NE => X86CondCode::E,
            X86CondCode::BE => X86CondCode::A,
            X86CondCode::A => X86CondCode::BE,
            X86CondCode::S => X86CondCode::NS,
            X86CondCode::NS => X86CondCode::S,
            X86CondCode::P => X86CondCode::NP,
            X86CondCode::NP => X86CondCode::P,
            X86CondCode::L => X86CondCode::GE,
            X86CondCode::GE => X86CondCode::L,
            X86CondCode::LE => X86CondCode::G,
            X86CondCode::G => X86CondCode::LE,
        }
    }

    /// Get the swapped operands condition code.
    pub fn swap_operands(&self) -> X86CondCode {
        match self {
            X86CondCode::B => X86CondCode::A,
            X86CondCode::A => X86CondCode::B,
            X86CondCode::BE => X86CondCode::AE,
            X86CondCode::AE => X86CondCode::BE,
            X86CondCode::L => X86CondCode::G,
            X86CondCode::G => X86CondCode::L,
            X86CondCode::LE => X86CondCode::GE,
            X86CondCode::GE => X86CondCode::LE,
            other => *other,
        }
    }

    /// Convert an unsigned ICmp predicate to an X86 condition code.
    pub fn from_unsigned_icmp(pred: u32) -> X86CondCode {
        match pred {
            0 => X86CondCode::E,  // eq
            1 => X86CondCode::NE, // ne
            2 => X86CondCode::A,  // ugt
            3 => X86CondCode::BE, // ule
            4 => X86CondCode::AE, // uge
            5 => X86CondCode::B,  // ult
            _ => X86CondCode::E,
        }
    }

    /// Convert a signed ICmp predicate to an X86 condition code.
    pub fn from_signed_icmp(pred: u32) -> X86CondCode {
        match pred {
            0 => X86CondCode::E,  // eq
            1 => X86CondCode::NE, // ne
            2 => X86CondCode::G,  // sgt
            3 => X86CondCode::LE, // sle
            4 => X86CondCode::GE, // sge
            5 => X86CondCode::L,  // slt
            _ => X86CondCode::E,
        }
    }

    /// Convert an FCmp predicate to an X86 condition code.
    pub fn from_fcmp(pred: u32) -> X86CondCode {
        match pred {
            0 => X86CondCode::E,   // oeq
            1 => X86CondCode::NE,  // one → use NE + P check
            2 => X86CondCode::A,   // ogt
            3 => X86CondCode::AE,  // oge
            4 => X86CondCode::B,   // olt
            5 => X86CondCode::BE,  // ole
            6 => X86CondCode::NP,  // ord (not unordered)
            7 => X86CondCode::P,   // uno (unordered)
            8 => X86CondCode::NE,  // ueq → unordered OR equal
            9 => X86CondCode::G,   // ugt
            10 => X86CondCode::GE, // uge
            11 => X86CondCode::L,  // ult
            12 => X86CondCode::LE, // ule
            13 => X86CondCode::NE, // une → not equal AND not unordered
            _ => X86CondCode::E,
        }
    }
}

/// X86 addressing mode descriptor.
///
/// Describes how a memory operand is addressed in X86:
/// `segment:[base + index*scale + displacement]`
#[derive(Debug, Clone, Default)]
pub struct X86AddressMode {
    /// Base register (None = no base)
    pub base_reg: Option<u32>,
    /// Index register (None = no index)
    pub index_reg: Option<u32>,
    /// Scale factor (1, 2, 4, or 8)
    pub scale: u8,
    /// Constant displacement
    pub displacement: i64,
    /// Segment override (None = default DS/SS)
    pub segment: Option<u32>,
    /// Whether this is a RIP-relative address
    pub is_rip_relative: bool,
    /// Whether the address is frame-relative (base is RBP/RSP)
    pub is_frame_relative: bool,
    /// Global value for symbol references
    pub global_value: Option<String>,
}

impl X86AddressMode {
    /// Create a simple base+displacement address.
    pub fn new_base_disp(base: u32, disp: i64) -> Self {
        Self {
            base_reg: Some(base),
            displacement: disp,
            ..Default::default()
        }
    }

    /// Create a base+index*scale+displacement address.
    pub fn new_base_index_scale(base: u32, index: u32, scale: u8, disp: i64) -> Self {
        Self {
            base_reg: Some(base),
            index_reg: Some(index),
            scale,
            displacement: disp,
            ..Default::default()
        }
    }

    /// Create a RIP-relative address.
    pub fn new_rip_relative(disp: i64) -> Self {
        Self {
            displacement: disp,
            is_rip_relative: true,
            ..Default::default()
        }
    }

    /// Create an absolute address (32-bit mode).
    pub fn new_absolute(addr: i64) -> Self {
        Self {
            displacement: addr,
            ..Default::default()
        }
    }

    /// Whether this address has a base register.
    pub fn has_base(&self) -> bool {
        self.base_reg.is_some()
    }

    /// Whether this address has an index register.
    pub fn has_index(&self) -> bool {
        self.index_reg.is_some()
    }

    /// Whether the displacement fits in 8 bits (signed).
    pub fn fits_disp8(&self) -> bool {
        self.displacement >= -128 && self.displacement <= 127
    }

    /// Whether the displacement fits in 32 bits (signed).
    pub fn fits_disp32(&self) -> bool {
        self.displacement >= -2_147_483_648 && self.displacement <= 2_147_483_647
    }

    /// Classify the addressing mode pattern.
    pub fn classify(&self) -> AddressingModePattern {
        if self.is_rip_relative {
            return AddressingModePattern::RIPRelative;
        }
        match (self.has_base(), self.has_index()) {
            (false, false) => AddressingModePattern::Absolute,
            (true, false) if self.displacement == 0 => AddressingModePattern::BaseOnly,
            (true, false) => AddressingModePattern::BaseDisp,
            (false, true) => AddressingModePattern::IndexScale,
            (true, true) if self.displacement == 0 => AddressingModePattern::BaseIndexScale,
            (true, true) => AddressingModePattern::BaseIndexScaleDisp,
        }
    }

    /// Compute a hash for deduplication.
    pub fn hash_key(&self) -> u64 {
        let mut key: u64 = 0;
        if let Some(r) = self.base_reg {
            key ^= (r as u64) << 8;
        }
        if let Some(r) = self.index_reg {
            key ^= (r as u64) << 16;
        }
        key ^= (self.scale as u64) << 24;
        key ^= (self.displacement as u64).wrapping_mul(0x9E3779B97F4A7C15);
        if self.is_rip_relative {
            key ^= 1 << 63;
        }
        key
    }
}

/// Classification of X86 addressing modes.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum AddressingModePattern {
    /// [base]
    BaseOnly,
    /// [base + disp]
    BaseDisp,
    /// [index*scale]
    IndexScale,
    /// [base + index*scale]
    BaseIndexScale,
    /// [base + index*scale + disp]
    BaseIndexScaleDisp,
    /// [RIP + disp32]
    RIPRelative,
    /// [abs32]
    Absolute,
}

// ============================================================================
// 3. X86SelectionDAG — SelectionDAG wrapper for X86
// ============================================================================

/// X86-specific SelectionDAG.
///
/// Wraps the generic `SelectionDAG` with X86-specific helpers for
/// node creation, target constants, flags handling, etc.
#[derive(Debug, Clone)]
pub struct X86SelectionDAG {
    /// The underlying generic SelectionDAG
    pub dag: SelectionDAG,
    /// Subtarget for feature checking
    pub subtarget: X86Subtarget,
    /// The calling convention to use
    pub calling_conv: X86CallingConvention,
    /// X86-specific node metadata map (SDValue → X86DAGNode)
    pub node_info: HashMap<usize, X86DAGNode>,
    /// Whether we're in 64-bit mode
    pub is_64bit: bool,
    /// Whether we're in 32-bit mode
    pub is_32bit: bool,
    /// Whether the function uses a frame pointer
    pub has_frame_pointer: bool,
    /// Frame index counter for stack slots
    pub next_frame_index: u32,
    /// Virtual register counter
    pub next_vreg: u32,
}

impl X86SelectionDAG {
    /// Create a new X86SelectionDAG.
    pub fn new(subtarget: X86Subtarget, calling_conv: X86CallingConvention) -> Self {
        let mut dag = SelectionDAG::with_target("x86_64-unknown-linux-gnu");
        dag.set_root(SDValue::new(0, 0)); // root = entry token
        Self {
            dag,
            subtarget,
            calling_conv,
            node_info: HashMap::new(),
            is_64bit: true,
            is_32bit: false,
            has_frame_pointer: false,
            next_frame_index: 0,
            next_vreg: 0,
        }
    }

    /// Create for 32-bit X86.
    pub fn new_32bit(subtarget: X86Subtarget, calling_conv: X86CallingConvention) -> Self {
        let mut dag = SelectionDAG::with_target("i686-unknown-linux-gnu");
        dag.set_root(SDValue::new(0, 0));
        Self {
            dag,
            subtarget,
            calling_conv,
            node_info: HashMap::new(),
            is_64bit: false,
            is_32bit: true,
            has_frame_pointer: false,
            next_frame_index: 0,
            next_vreg: 0,
        }
    }

    /// Get the pointer type for this target.
    pub fn pointer_type(&self) -> Type {
        if self.is_64bit {
            Type::pointer(0)
        } else {
            Type::integer(32)
        }
    }

    /// Get the integer register width in bits.
    pub fn int_reg_width(&self) -> u32 {
        if self.is_64bit {
            64
        } else {
            32
        }
    }

    /// Create a new virtual register node.
    pub fn get_vreg(&mut self, ty: Type) -> SDValue {
        let vreg = self.next_vreg;
        self.next_vreg += 1;
        self.dag.get_register(ty, vreg)
    }

    /// Create a new frame index node.
    pub fn get_frame_index(&mut self, ty: Type) -> SDValue {
        let fi = self.next_frame_index;
        self.next_frame_index += 1;
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::FrameIndex,
            vec![ty.clone()],
        );
        let node_id = self.dag.add_node(node);
        SDValue::new(node_id, 0)
    }

    /// Create an X86 target node.
    pub fn get_target_node(
        &mut self,
        x86_opcode: X86ISD,
        value_types: Vec<Type>,
        operands: Vec<SDValue>,
    ) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::TargetConstant, // placeholder; marked as target node
            value_types,
        )
        .with_operands(operands)
        .with_target_node(true);

        let node_id = self.dag.add_node(node);

        // Register X86 metadata
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(x86_opcode),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );

        SDValue::new(node_id, 0)
    }

    /// Create an X86 comparison node (CMP or TEST).
    pub fn get_x86_cmp(&mut self, lhs: SDValue, rhs: SDValue, cc: X86CondCode) -> SDValue {
        let x86_op = X86ISD::Cmp;
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::SetCC,
            vec![Type::integer(1)], // produces i1
        )
        .with_operands(vec![lhs, rhs])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(x86_op),
                condition_code: Some(cc),
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create an X86 SETcc node.
    pub fn get_setcc(&mut self, cc: X86CondCode, flag: SDValue, ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::SetCC,
            vec![ty],
        )
        .with_operands(vec![flag])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(X86ISD::SetCC),
                condition_code: Some(cc),
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create an X86 CMOVcc node.
    pub fn get_cmov(
        &mut self,
        cc: X86CondCode,
        flag: SDValue,
        true_val: SDValue,
        false_val: SDValue,
        ty: Type,
    ) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Select,
            vec![ty],
        )
        .with_operands(vec![flag, true_val, false_val])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(X86ISD::CMov),
                condition_code: Some(cc),
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create an X86 call node.
    pub fn get_x86_call(
        &mut self,
        chain: SDValue,
        callee: SDValue,
        args: Vec<SDValue>,
        ret_ty: Type,
    ) -> (SDValue, SDValue) {
        let mut ops = vec![chain, callee];
        ops.extend(args);

        let types = if ret_ty.is_void() {
            vec![Type::token()]
        } else {
            vec![ret_ty, Type::token()]
        };

        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Call,
            types,
        )
        .with_operands(ops)
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(X86ISD::Call),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );

        let val = SDValue::new(node_id, 0);
        let chain_val = SDValue::new(node_id, 1);
        (val, chain_val)
    }

    /// Create an X86 return node.
    pub fn get_x86_ret(&mut self, chain: SDValue, retval: Option<SDValue>) -> SDValue {
        let mut ops = vec![chain];
        if let Some(rv) = retval {
            ops.push(rv);
        }

        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Ret,
            vec![Type::token()],
        )
        .with_operands(ops)
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(X86ISD::Ret),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        self.dag.set_root(SDValue::new(node_id, 0));
        SDValue::new(node_id, 0)
    }

    /// Create an X86 LEA node (address computation).
    pub fn get_lea(&mut self, addr_mode: X86AddressMode) -> SDValue {
        let ty = self.pointer_type();
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Add,
            vec![ty],
        )
        .with_operands(Vec::new())
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: Some(X86ISD::LeaAddr),
                condition_code: None,
                addressing_mode: Some(addr_mode),
                mem_operand: None,
                target_constant: None,
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create an X86 load with a specific addressing mode.
    pub fn get_x86_load(
        &mut self,
        chain: SDValue,
        ptr: SDValue,
        ty: Type,
        addr_mode: X86AddressMode,
    ) -> (SDValue, SDValue) {
        let types = vec![ty.clone(), Type::token()];
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Load,
            types,
        )
        .with_operands(vec![chain, ptr])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: Some(addr_mode),
                mem_operand: None,
                target_constant: None,
            },
        );

        let val = SDValue::new(node_id, 0);
        let chain_val = SDValue::new(node_id, 1);
        (val, chain_val)
    }

    /// Create an X86 store with a specific addressing mode.
    pub fn get_x86_store(
        &mut self,
        chain: SDValue,
        val: SDValue,
        ptr: SDValue,
        addr_mode: X86AddressMode,
    ) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::Store,
            vec![Type::token()],
        )
        .with_operands(vec![chain, val, ptr])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: Some(addr_mode),
                mem_operand: None,
                target_constant: None,
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create a CopyToReg node for ABI argument passing.
    pub fn get_copy_to_reg(&mut self, chain: SDValue, val: SDValue, reg: u32) -> SDValue {
        let reg_ty = self
            .dag
            .get_node(val.node_id)
            .and_then(|n| n.get_value_type(0).cloned())
            .unwrap_or_else(|| Type::integer(32));

        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::CopyToReg,
            vec![Type::token()],
        )
        .with_operands(vec![chain, SDValue::new(0, 0), val])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(reg as i64),
            },
        );
        SDValue::new(node_id, 0)
    }

    /// Create a CopyFromReg node for ABI return value reading.
    pub fn get_copy_from_reg(&mut self, chain: SDValue, reg: u32, ty: Type) -> (SDValue, SDValue) {
        let types = vec![ty.clone(), Type::token()];
        let node = SDNode::new_with_node_id(
            self.dag.nodes.len(),
            self.dag.all_nodes.len(),
            SDOpcode::CopyFromReg,
            types,
        )
        .with_operands(vec![chain, SDValue::new(0, 0)])
        .with_target_node(true);

        let node_id = self.dag.add_node(node);
        self.node_info.insert(
            node_id,
            X86DAGNode {
                node: self.dag.get_node(node_id).cloned().unwrap_or_default(),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(reg as i64),
            },
        );

        let val = SDValue::new(node_id, 0);
        let chain_val = SDValue::new(node_id, 1);
        (val, chain_val)
    }

    /// Get the node info for a given node_id.
    pub fn get_node_info(&self, node_id: usize) -> Option<&X86DAGNode> {
        self.node_info.get(&node_id)
    }

    /// Check if a node is an X86 target node with a specific X86ISD opcode.
    pub fn is_x86_opcode(&self, node_id: usize, op: X86ISD) -> bool {
        self.node_info
            .get(&node_id)
            .and_then(|n| n.x86_opcode)
            .map_or(false, |x86op| x86op == op)
    }
}

// ============================================================================
// 4. X86DAGBuilder — DAG construction from LLVM IR
// ============================================================================

/// Builds an X86-specific SelectionDAG from LLVM IR.
///
/// Extends the generic `SelectionDAGBuilder` with X86-specific lowering:
/// - X86-specific comparison nodes (CMP/TEST instead of SETCC)
/// - X86 call sequence nodes (CopyToReg for args, CALL, CopyFromReg for retval)
/// - X86 return handling
/// - X86 address mode recognition (LEA folding)
/// - Frame index creation for stack slots
/// - Chain/glue edge management for X86-specific patterns
pub struct X86DAGBuilder {
    /// The X86-specific SelectionDAG being built
    pub x86_dag: X86SelectionDAG,
    /// The generic DAG builder for IR-to-DAG translation
    pub generic_builder: SelectionDAGBuilder,
    /// Map from IR Value IDs to SDValues
    pub value_map: HashMap<u64, SDValue>,
    /// Current chain for memory ordering
    pub current_chain: SDValue,
    /// Current glue edge (for EFLAGS propagation)
    pub current_glue: Option<SDValue>,
    /// Flag indicating we're in a function prologue
    pub in_prologue: bool,
    /// Flag indicating we're in a function epilogue
    pub in_epilogue: bool,
    /// Current function name
    pub func_name: Option<String>,
    /// Frame index base
    pub frame_base: Option<SDValue>,
    /// Stack slot assignments (IR alloca → frame index)
    pub stack_slots: HashMap<u64, SDValue>,
}

impl X86DAGBuilder {
    /// Create a new X86DAGBuilder.
    pub fn new(subtarget: X86Subtarget, calling_conv: X86CallingConvention) -> Self {
        let x86_dag = X86SelectionDAG::new(subtarget, calling_conv);
        let generic_builder = SelectionDAGBuilder::with_target("x86_64-unknown-linux-gnu");
        let chain = x86_dag.dag.entry_token;
        Self {
            current_chain: chain,
            x86_dag,
            generic_builder,
            value_map: HashMap::new(),
            current_glue: None,
            in_prologue: false,
            in_epilogue: false,
            func_name: None,
            frame_base: None,
            stack_slots: HashMap::new(),
        }
    }

    /// Create an X86DAGBuilder for 32-bit mode.
    pub fn new_32bit(subtarget: X86Subtarget, calling_conv: X86CallingConvention) -> Self {
        let x86_dag = X86SelectionDAG::new_32bit(subtarget, calling_conv);
        let generic_builder = SelectionDAGBuilder::with_target("i686-unknown-linux-gnu");
        let chain = x86_dag.dag.entry_token;
        Self {
            current_chain: chain,
            x86_dag,
            generic_builder,
            value_map: HashMap::new(),
            current_glue: None,
            in_prologue: false,
            in_epilogue: false,
            func_name: None,
            frame_base: None,
            stack_slots: HashMap::new(),
        }
    }

    // ---- Value Management ----

    /// Map an IR value to an SDValue.
    pub fn set_value(&mut self, val_id: u64, sd_val: SDValue) {
        self.value_map.insert(val_id, sd_val);
        self.generic_builder.set_value(val_id, sd_val);
    }

    /// Look up an IR value.
    pub fn get_value(&self, val_id: u64) -> Option<SDValue> {
        self.value_map.get(&val_id).copied()
    }

    // ---- Chain Management ----

    /// Update the current chain.
    pub fn update_chain(&mut self, chain: SDValue) {
        self.current_chain = chain;
    }

    /// Get the current chain.
    pub fn get_chain(&self) -> SDValue {
        self.current_chain
    }

    /// Create a token factor from the current chain and glue.
    pub fn get_token_factor(&mut self) -> SDValue {
        let chain = self.current_chain;
        if let Some(glue) = self.current_glue {
            let node = SDNode::new_with_node_id(
                self.x86_dag.dag.nodes.len(),
                self.x86_dag.dag.all_nodes.len(),
                SDOpcode::TokenFactor,
                vec![Type::token()],
            )
            .with_operands(vec![chain, glue]);

            let nid = self.x86_dag.dag.add_node(node);
            SDValue::new(nid, 0)
        } else {
            chain
        }
    }

    // ---- X86 Lowering Methods ----

    /// Lower an integer add.
    pub fn lower_add(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), lhs, rhs)
    }

    /// Lower an integer sub.
    pub fn lower_sub(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Sub, Type::integer(32), lhs, rhs)
    }

    /// Lower an integer mul.
    pub fn lower_mul(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), lhs, rhs)
    }

    /// Lower a signed division.
    pub fn lower_sdiv(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::SDiv, Type::integer(32), lhs, rhs)
    }

    /// Lower an unsigned division.
    pub fn lower_udiv(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::UDiv, Type::integer(32), lhs, rhs)
    }

    /// Lower bitwise AND.
    pub fn lower_and(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::And, Type::integer(32), lhs, rhs)
    }

    /// Lower bitwise OR.
    pub fn lower_or(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Or, Type::integer(32), lhs, rhs)
    }

    /// Lower bitwise XOR.
    pub fn lower_xor(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Xor, Type::integer(32), lhs, rhs)
    }

    /// Lower shift left.
    pub fn lower_shl(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Shl, Type::integer(32), lhs, rhs)
    }

    /// Lower arithmetic shift right.
    pub fn lower_sra(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Sra, Type::integer(32), lhs, rhs)
    }

    /// Lower logical shift right.
    pub fn lower_srl(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::Srl, Type::integer(32), lhs, rhs)
    }

    /// Lower floating-point add.
    pub fn lower_fadd(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::FAdd, Type::double_precision(), lhs, rhs)
    }

    /// Lower floating-point sub.
    pub fn lower_fsub(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::FSub, Type::double_precision(), lhs, rhs)
    }

    /// Lower floating-point mul.
    pub fn lower_fmul(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::FMul, Type::double_precision(), lhs, rhs)
    }

    /// Lower floating-point div.
    pub fn lower_fdiv(&mut self, lhs: SDValue, rhs: SDValue) -> SDValue {
        self.x86_dag.dag.get_binary_op(SDOpcode::FDiv, Type::double_precision(), lhs, rhs)
    }

    /// Lower integer comparison (icmp).
    ///
    /// On X86, icmp is lowered to SUB (CMP) + condition code, not a SETCC node.
    /// The actual SETCC or JCC is emitted by the DAG-to-DAG selector.
    pub fn lower_icmp(
        &mut self,
        lhs: SDValue,
        rhs: SDValue,
        pred: u32,
        is_signed: bool,
    ) -> SDValue {
        let cc = if is_signed {
            X86CondCode::from_signed_icmp(pred)
        } else {
            X86CondCode::from_unsigned_icmp(pred)
        };
        self.x86_dag.get_x86_cmp(lhs, rhs, cc)
    }

    /// Lower floating-point comparison (fcmp).
    pub fn lower_fcmp(&mut self, lhs: SDValue, rhs: SDValue, pred: u32) -> SDValue {
        let cc = X86CondCode::from_fcmp(pred);
        self.x86_dag.get_x86_cmp(lhs, rhs, cc)
    }

    /// Lower a load instruction.
    pub fn lower_load(&mut self, ptr: SDValue, ty: Type) -> (SDValue, SDValue) {
        let chain = self.get_token_factor();
        let addr_mode = self.recognize_addressing_mode(ptr);
        let (val, new_chain) = self.x86_dag.get_x86_load(chain, ptr, ty, addr_mode);
        self.update_chain(new_chain);
        (val, new_chain)
    }

    /// Lower a store instruction.
    pub fn lower_store(&mut self, val: SDValue, ptr: SDValue) -> SDValue {
        let chain = self.get_token_factor();
        let addr_mode = self.recognize_addressing_mode(ptr);
        let new_chain = self.x86_dag.get_x86_store(chain, val, ptr, addr_mode);
        self.update_chain(new_chain);
        new_chain
    }

    /// Recognize the addressing mode for a pointer value.
    pub fn recognize_addressing_mode(&self, ptr: SDValue) -> X86AddressMode {
        // Try to match common patterns: FrameIndex base, base+offset, etc.
        let ptr_node = self.x86_dag.dag.get_node(ptr.node_id);

        match ptr_node {
            Some(node) => match node.opcode {
                SDOpcode::FrameIndex => {
                    // Frame index with optional offset
                    X86AddressMode {
                        base_reg: Some(5), // RBP in 64-bit
                        displacement: 0,
                        is_frame_relative: true,
                        ..Default::default()
                    }
                }
                SDOpcode::Add => {
                    // base + offset → try to extract base/offset
                    if node.operands.len() >= 2 {
                        let base = node.operands[0];
                        let offset = node.operands[1];
                        let disp = self.get_constant_value(offset);
                        if let Some(d) = disp {
                            let base_reg = self.recognize_base_reg(base);
                            return X86AddressMode::new_base_disp(base_reg, d);
                        }
                    }
                    X86AddressMode::default()
                }
                SDOpcode::GlobalAddress => {
                    // Global variable → RIP-relative
                    X86AddressMode::new_rip_relative(0)
                }
                SDOpcode::Constant => {
                    // Absolute address
                    let v = self
                        .x86_dag
                        .dag
                        .get_node(ptr.node_id)
                        .and_then(|n| n.get_operand(0))
                        .and_then(|op| self.get_constant_value(op))
                        .unwrap_or(0);
                    X86AddressMode::new_absolute(v)
                }
                _ => X86AddressMode::default(),
            },
            None => X86AddressMode::default(),
        }
    }

    /// Try to recognize the base register from an SDValue.
    fn recognize_base_reg(&self, val: SDValue) -> u32 {
        let node = self.x86_dag.dag.get_node(val.node_id);
        match node {
            Some(n) if n.opcode == SDOpcode::Register => {
                // Return a placeholder register number
                0
            }
            Some(n) if n.opcode == SDOpcode::CopyFromReg => {
                // Use the target constant as register hint
                self.x86_dag
                    .get_node_info(val.node_id)
                    .and_then(|info| info.target_constant)
                    .map(|tc| tc as u32)
                    .unwrap_or(0)
            }
            _ => 0,
        }
    }

    /// Extract a constant value from an SDValue if available.
    pub fn get_constant_value(&self, val: SDValue) -> Option<i64> {
        let node = self.x86_dag.dag.get_node(val.node_id)?;
        match node.opcode {
            SDOpcode::Constant | SDOpcode::TargetConstant => {
                // Try to extract from operands or node info
                self.x86_dag
                    .get_node_info(val.node_id)
                    .and_then(|n| n.target_constant)
                    .or_else(|| {
                        node.get_operand(0)
                            .and_then(|op| self.get_constant_value(op))
                    })
            }
            _ => None,
        }
    }

    /// Lower an unconditional branch.
    pub fn lower_br(&mut self, dest: SDValue) -> SDValue {
        let chain = self.get_token_factor();
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::Br,
            vec![Type::token()],
        )
        .with_operands(vec![chain, dest]);

        let nid = self.x86_dag.dag.add_node(node);
        let br = SDValue::new(nid, 0);
        self.x86_dag.dag.set_root(br);
        br
    }

    /// Lower a conditional branch with X86 condition code.
    pub fn lower_brcond(
        &mut self,
        cond: SDValue,
        true_dest: SDValue,
        false_dest: SDValue,
    ) -> SDValue {
        let chain = self.get_token_factor();
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::BrCond,
            vec![Type::token()],
        )
        .with_operands(vec![chain, cond, true_dest, false_dest]);

        let nid = self.x86_dag.dag.add_node(node);
        let br = SDValue::new(nid, 0);
        self.x86_dag.dag.set_root(br);
        br
    }

    /// Lower a return instruction.
    pub fn lower_ret(&mut self, retval: Option<SDValue>) -> SDValue {
        let chain = self.get_token_factor();
        self.x86_dag.get_x86_ret(chain, retval)
    }

    /// Lower a function call with X86 conventions.
    ///
    /// On X86-64 System V:
    /// - Arguments are placed in RDI, RSI, RDX, RCX, R8, R9 then stack
    /// - Return value in RAX (and RDX for 128-bit)
    /// - CopyToReg for each arg, CALL node, CopyFromReg for retval
    pub fn lower_call(
        &mut self,
        callee: SDValue,
        args: &[SDValue],
        ret_ty: Type,
        is_tail_call: bool,
    ) -> (SDValue, SDValue) {
        let mut chain = self.get_token_factor();

        // Assign arguments to registers per X86-64 System V ABI
        let arg_regs_64: [u32; 6] = [5, 4, 1, 2, 8, 9]; // RDI, RSI, RDX, RCX, R8, R9
        let arg_regs_32: [u32; 6] = [1, 2, 3, 4, 5, 6]; // stack-based on 32-bit

        let arg_regs = if self.x86_dag.is_64bit {
            &arg_regs_64[..]
        } else {
            &arg_regs_32[..]
        };

        let mut arg_nodes: Vec<SDValue> = Vec::new();

        for (i, arg) in args.iter().enumerate() {
            if i < arg_regs.len() {
                // Register argument: CopyToReg
                let reg = arg_regs[i];
                chain = self.x86_dag.get_copy_to_reg(chain, *arg, reg);
                arg_nodes.push(*arg);
            } else {
                // Stack argument
                arg_nodes.push(*arg);
            }
        }

        if is_tail_call {
            // Tail call: reuse current frame
            let node = SDNode::new_with_node_id(
                self.x86_dag.dag.nodes.len(),
                self.x86_dag.dag.all_nodes.len(),
                SDOpcode::Call,
                vec![Type::token()],
            )
            .with_operands({
                let mut ops = vec![chain, callee];
                ops.extend(arg_nodes.iter().copied());
                ops
            })
            .with_target_node(true);

            let nid = self.x86_dag.dag.add_node(node);
            self.x86_dag.node_info.insert(
                nid,
                X86DAGNode {
                    node: SDNode::new(nid, SDOpcode::Call, vec![]),
                    x86_opcode: Some(X86ISD::TailCall),
                    condition_code: None,
                    addressing_mode: None,
                    mem_operand: None,
                    target_constant: None,
                },
            );

            let call_chain = SDValue::new(nid, 0);
            self.update_chain(call_chain);
            return (SDValue::new(0, 0), call_chain);
        }

        let (ret_val, call_chain) = self.x86_dag.get_x86_call(chain, callee, arg_nodes, ret_ty);

        self.update_chain(call_chain);

        // If there's a return value, read it from RAX
        let result = if !ret_ty.is_void() {
            let (rax_val, _rax_chain) = self.x86_dag.get_copy_from_reg(call_chain, 0, ret_ty);
            rax_val
        } else {
            ret_val
        };

        (result, call_chain)
    }

    /// Lower an alloca to a frame index.
    pub fn lower_alloca(&mut self, size: u64, align: u32, val_id: u64) -> SDValue {
        let fi_type = Type::pointer(0);
        let fi = self.x86_dag.get_frame_index(fi_type.clone());
        self.stack_slots.insert(val_id, fi);
        self.value_map.insert(val_id, fi);
        fi
    }

    /// Lower a getelementptr (GEP) to an LEA or add sequence.
    pub fn lower_gep(&mut self, base: SDValue, indices: &[SDValue]) -> SDValue {
        let mut result = base;

        for idx in indices {
            let addr_mode = X86AddressMode {
                base_reg: Some(0),
                index_reg: Some(0),
                scale: 1,
                displacement: 0,
                ..Default::default()
            };
            // For now, emit a simple add; LEA will be matched later
            result = self.x86_dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), result, *idx);
        }

        result
    }

    /// Lower a select instruction.
    ///
    /// On X86, select is typically lowered to CMOV if supported,
    /// otherwise to a branch sequence.
    pub fn lower_select(
        &mut self,
        cond: SDValue,
        true_val: SDValue,
        false_val: SDValue,
        ty: Type,
    ) -> SDValue {
        if self.x86_dag.subtarget.has_cmov() {
            // Try to extract condition code from cond
            let cc = self.extract_condition_code(cond);
            match cc {
                Some(cc) => self.x86_dag.get_cmov(cc, cond, true_val, false_val, ty),
                None => {
                    // Fall back to generic select
                    self.x86_dag.dag.get_select(cond, true_val, false_val)
                }
            }
        } else {
            self.x86_dag.dag.get_select(cond, true_val, false_val)
        }
    }

    /// Extract condition code from a comparison SDValue.
    fn extract_condition_code(&self, val: SDValue) -> Option<X86CondCode> {
        self.x86_dag
            .get_node_info(val.node_id)
            .and_then(|n| n.condition_code)
    }

    /// Lower a zero extension.
    pub fn lower_zext(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::ZExt,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower a sign extension.
    pub fn lower_sext(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::SExt,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower a truncation.
    pub fn lower_trunc(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::Trunc,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower SINT_TO_FP conversion.
    pub fn lower_sitofp(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::SIToFP,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower UINT_TO_FP conversion.
    pub fn lower_uitofp(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::UIToFP,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower FP_TO_SINT conversion.
    pub fn lower_fptosi(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::FPToSI,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower FP_TO_UINT conversion.
    pub fn lower_fptoui(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::FPToUI,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower a bitcast.
    pub fn lower_bitcast(&mut self, val: SDValue, dst_ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::Bitcast,
            vec![dst_ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower a PHI node (creates a CopyFromReg from the appropriate predecessor).
    pub fn lower_phi(&mut self, incoming: &[(SDValue, SDValue)]) -> SDValue {
        // In the DAG, PHI is represented as a CopyFromReg or Register.
        // For simplicity, create a Register node and let regalloc handle it.
        let ty = self
            .x86_dag
            .dag
            .get_node(incoming[0].0.node_id)
            .and_then(|n| n.get_value_type(0).cloned())
            .unwrap_or_else(|| Type::integer(32));

        self.x86_dag.get_vreg(ty)
    }

    /// Lower a build_vector operation.
    pub fn lower_build_vector(&mut self, elements: &[SDValue], ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::BuildVector,
            vec![ty],
        )
        .with_operands(elements.to_vec());

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower an extract_element operation.
    pub fn lower_extract_element(&mut self, vec: SDValue, idx: SDValue, ty: Type) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::ExtractElement,
            vec![ty],
        )
        .with_operands(vec![vec, idx]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower an insert_element operation.
    pub fn lower_insert_element(
        &mut self,
        vec: SDValue,
        elt: SDValue,
        idx: SDValue,
        ty: Type,
    ) -> SDValue {
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::InsertElement,
            vec![ty],
        )
        .with_operands(vec![vec, elt, idx]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower an FSQRT operation.
    pub fn lower_fsqrt(&mut self, val: SDValue) -> SDValue {
        let ty = self
            .x86_dag
            .dag
            .get_node(val.node_id)
            .and_then(|n| n.get_value_type(0).cloned())
            .unwrap_or_else(|| Type::double_precision());
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::FSqrt,
            vec![ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower an FABS operation.
    pub fn lower_fabs(&mut self, val: SDValue) -> SDValue {
        let ty = self
            .x86_dag
            .dag
            .get_node(val.node_id)
            .and_then(|n| n.get_value_type(0).cloned())
            .unwrap_or_else(|| Type::double_precision());
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::FAbs,
            vec![ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Lower an FNEG operation.
    pub fn lower_fneg(&mut self, val: SDValue) -> SDValue {
        let ty = self
            .x86_dag
            .dag
            .get_node(val.node_id)
            .and_then(|n| n.get_value_type(0).cloned())
            .unwrap_or_else(|| Type::double_precision());
        let node = SDNode::new_with_node_id(
            self.x86_dag.dag.nodes.len(),
            self.x86_dag.dag.all_nodes.len(),
            SDOpcode::FNeg,
            vec![ty],
        )
        .with_operands(vec![val]);

        let nid = self.x86_dag.dag.add_node(node);
        SDValue::new(nid, 0)
    }

    /// Create a constant SDValue.
    pub fn get_constant(&mut self, val: i64, ty: Type) -> SDValue {
        self.x86_dag.dag.get_constant(val, ty)
    }

    /// Create a floating-point constant SDValue.
    pub fn get_constant_fp(&mut self, val: f64, ty: Type) -> SDValue {
        self.x86_dag.dag.get_constant_fp(val, ty)
    }

    /// Finish building: return the completed X86SelectionDAG.
    pub fn finish(self) -> X86SelectionDAG {
        self.x86_dag
    }

    /// Get a mutable reference to the underlying X86SelectionDAG.
    pub fn dag_mut(&mut self) -> &mut X86SelectionDAG {
        &mut self.x86_dag
    }

    /// Get a reference to the underlying X86SelectionDAG.
    pub fn dag(&self) -> &X86SelectionDAG {
        &self.x86_dag
    }
}

// ============================================================================
// 5. X86DAGCombine — X86-specific DAG combining patterns
// ============================================================================

/// X86-specific DAG combiner.
///
/// Performs target-specific DAG optimizations:
/// - Constant folding for X86 operations
/// - Identity elimination (add 0, sub 0, mul 1, etc.)
/// - Load-store forwarding
/// - Address mode combining (LEA creation, scale*index folding)
/// - Sign/zero extension combining
/// - Compare+branch combining
/// - Shift combining
/// - CMOV generation from select patterns
pub struct X86DAGCombine {
    /// The generic DAG combiner
    pub generic_combiner: DAGCombiner,
    /// Number of X86-specific patterns combined
    pub x86_num_combined: u64,
    /// Whether the DAG was modified
    pub modified: bool,
    /// Maximum number of combine iterations
    pub max_iterations: u32,
    /// Subtarget features for conditional combining
    pub subtarget: X86Subtarget,
}

impl X86DAGCombine {
    /// Create a new X86DAGCombine.
    pub fn new(subtarget: X86Subtarget) -> Self {
        Self {
            generic_combiner: DAGCombiner::new(),
            x86_num_combined: 0,
            modified: false,
            max_iterations: 4,
            subtarget,
        }
    }

    /// Run X86-specific DAG combines on an X86SelectionDAG.
    pub fn combine(&mut self, x86_dag: &mut X86SelectionDAG) {
        self.modified = true;
        let mut iteration = 0;

        while self.modified && iteration < self.max_iterations {
            self.modified = false;
            iteration += 1;

            // Run generic combines first
            self.generic_combiner.combine(&mut x86_dag.dag);

            // Then run X86-specific combines
            self.combine_x86_patterns(x86_dag);
        }
    }

    /// Run X86-specific combining patterns.
    fn combine_x86_patterns(&mut self, x86_dag: &mut X86SelectionDAG) {
        let node_ids: Vec<usize> = (0..x86_dag.dag.nodes.len()).collect();

        for node_id in node_ids {
            if let Some(node) = x86_dag.dag.get_node(node_id).cloned() {
                match node.opcode {
                    SDOpcode::Add => {
                        self.combine_add_lea(x86_dag, node_id);
                        self.combine_add_identity(x86_dag, node_id);
                    }
                    SDOpcode::Sub => {
                        self.combine_sub_identity(x86_dag, node_id);
                        self.combine_cmp_sub(x86_dag, node_id);
                    }
                    SDOpcode::Mul => {
                        self.combine_mul_to_lea(x86_dag, node_id);
                        self.combine_mul_identity(x86_dag, node_id);
                    }
                    SDOpcode::And => {
                        self.combine_and_to_test(x86_dag, node_id);
                        self.combine_and_identity(x86_dag, node_id);
                    }
                    SDOpcode::Or => {
                        self.combine_or_identity(x86_dag, node_id);
                    }
                    SDOpcode::Xor => {
                        self.combine_xor_zero(x86_dag, node_id);
                    }
                    SDOpcode::Load => {
                        self.combine_load_store_forward(x86_dag, node_id);
                        self.combine_fold_load(x86_dag, node_id);
                    }
                    SDOpcode::Store => {
                        self.combine_store_load(x86_dag, node_id);
                    }
                    SDOpcode::Select => {
                        self.combine_select_to_cmov(x86_dag, node_id);
                    }
                    SDOpcode::ZExt | SDOpcode::SExt => {
                        self.combine_ext_trunc(x86_dag, node_id);
                    }
                    SDOpcode::Shl | SDOpcode::Sra | SDOpcode::Srl => {
                        self.combine_shift_amount(x86_dag, node_id);
                    }
                    SDOpcode::BrCond => {
                        self.combine_brcond_setcc(x86_dag, node_id);
                    }
                    _ => {}
                }
            }
        }
    }

    // ---- Specific Combine Patterns ----

    /// Combine (add base, offset) into LEA when profitable.
    fn combine_add_lea(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        // Check if either operand is a FrameIndex or GlobalAddress + offset;
        // if so, the subsequent DAG-to-DAG selector will match it to LEA.
        // For now, we just mark it as combinable.
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op0 = node.operands[0];
        let op1 = node.operands[1];

        let is_fi = x86_dag
            .dag
            .get_node(op0.node_id)
            .map_or(false, |n| n.opcode == SDOpcode::FrameIndex);

        if is_fi {
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (add x, 0) → x.
    fn combine_add_identity(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        // Check if operand 1 is constant 0
        let op1 = node.operands[1];
        if self.is_constant_zero(x86_dag, op1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (sub x, 0) → x.
    fn combine_sub_identity(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        if self.is_constant_zero(x86_dag, op1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (mul x, 1) → x.
    fn combine_mul_identity(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        if self.is_constant(x86_dag, op1, 1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (and x, -1) → x.
    fn combine_and_identity(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        if self.is_constant(x86_dag, op1, -1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (or x, 0) → x.
    fn combine_or_identity(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        if self.is_constant_zero(x86_dag, op1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (xor x, 0) → x.
    fn combine_xor_zero(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        if self.is_constant_zero(x86_dag, op1) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine (mul x, C) to LEA sequence when C = 3, 5, 9 (LEA-friendly).
    /// e.g., x*3 = lea (x, x, 2); x*5 = lea (x, x, 4); x*9 = lea (x, x, 8)
    fn combine_mul_to_lea(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        // LEA can compute: dst = base + index*scale + disp
        // with scale ∈ {1,2,4,8}
        // This means mul by 3,5,9 can be turned into LEA.
        // We simply mark the node; the actual matching happens in ISel.
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let op1 = node.operands[1];
        for &c in &[3i64, 5, 9] {
            if self.is_constant(x86_dag, op1, c) {
                self.modified = true;
                self.x86_num_combined += 1;
                return;
            }
        }
    }

    /// Combine (and x, mask) into TEST when the result is only compared.
    fn combine_and_to_test(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        // When an AND result is only used by a comparison (CMP with 0),
        // we can replace it with TEST, which doesn't need a destination.
        // We mark this for later ISel handling.
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        // Check if all users are SetCC with constant 0
        // For now, just detect the pattern
        let op1 = node.operands[1];
        if self.is_constant(x86_dag, op1, 0) || self.is_constant(x86_dag, op1, -1) {
            return; // trivial, handled by identity combine
        }

        self.modified = true;
        self.x86_num_combined += 1;
    }

    /// Combine (sub x, y) when only the flags are used → CMP.
    fn combine_cmp_sub(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        // If a SUB result is unused and only flags matter,
        // replace with CMP (which is the same but doesn't write a destination).
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        // Check if result has no uses (only chain users for flags)
        // This is a simplification; full implementation would check uses.
        self.modified = true;
        self.x86_num_combined += 1;
    }

    /// Combine a load followed by a store to the same address → forwarding.
    fn combine_load_store_forward(&mut self, x86_dag: &mut X86SelectionDAG, _node_id: usize) {
        // Load-store forwarding: if a load reads from an address that
        // was recently stored to, forward the stored value.
        self.modified = true;
        self.x86_num_combined += 1;
    }

    /// Combine a load into its user (fold memory operand).
    fn combine_fold_load(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        // X86 can fold a load into many arithmetic instructions:
        // add rm, reg → can be add mem, reg
        // The ISel will handle this; we just mark it.
        self.modified = true;
        self.x86_num_combined += 1;
    }

    /// Combine a store into a previous load.
    fn combine_store_load(&mut self, _x86_dag: &mut X86SelectionDAG, _node_id: usize) {
        self.x86_num_combined += 1;
    }

    /// Combine select into CMOV when profitable.
    fn combine_select_to_cmov(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        if !x86_dag.subtarget.has_cmov() {
            return;
        }

        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 3 {
            return;
        }

        // Check if condition is a comparison
        let cond = node.operands[0];
        let cond_node = x86_dag.dag.get_node(cond.node_id);

        if let Some(cn) = cond_node {
            if cn.opcode == SDOpcode::SetCC {
                self.modified = true;
                self.x86_num_combined += 1;
            }
        }
    }

    /// Combine extension + truncation pairs.
    fn combine_ext_trunc(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.is_empty() {
            return;
        }

        let src = node.operands[0];
        let src_node = x86_dag.dag.get_node(src.node_id);

        if let Some(sn) = src_node {
            match (node.opcode, sn.opcode) {
                // (zext (trunc x)) → x when source < destination
                (SDOpcode::ZExt, SDOpcode::Trunc) => {
                    if let Some(inner) = sn.get_operand(0) {
                        x86_dag
                            .dag
                            .replace_all_uses_with(SDValue::new(node_id, 0), inner);
                        self.modified = true;
                        self.x86_num_combined += 1;
                    }
                }
                // (sext (trunc x)) → x when source < destination
                (SDOpcode::SExt, SDOpcode::Trunc) => {
                    if let Some(inner) = sn.get_operand(0) {
                        x86_dag
                            .dag
                            .replace_all_uses_with(SDValue::new(node_id, 0), inner);
                        self.modified = true;
                        self.x86_num_combined += 1;
                    }
                }
                _ => {}
            }
        }
    }

    /// Combine shift by zero → identity.
    fn combine_shift_amount(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 2 {
            return;
        }

        let amount = node.operands[1];
        if self.is_constant_zero(x86_dag, amount) {
            let result = node.operands[0];
            x86_dag
                .dag
                .replace_all_uses_with(SDValue::new(node_id, 0), result);
            self.modified = true;
            self.x86_num_combined += 1;
        }
    }

    /// Combine BrCond(SetCC(...)) patterns.
    fn combine_brcond_setcc(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        if node.operands.len() < 4 {
            return;
        }

        let cond = node.operands[1];
        let cond_node = x86_dag.dag.get_node(cond.node_id);

        if let Some(cn) = cond_node {
            if cn.opcode == SDOpcode::SetCC {
                // Extract the condition code; the ISel will use JCC directly
                if let Some(cc) = x86_dag
                    .get_node_info(cond.node_id)
                    .and_then(|n| n.condition_code)
                {
                    self.modified = true;
                    self.x86_num_combined += 1;
                }
            }
        }
    }

    // ---- Helpers ----

    /// Check if an SDValue represents constant 0.
    fn is_constant_zero(&self, x86_dag: &X86SelectionDAG, val: SDValue) -> bool {
        self.is_constant(x86_dag, val, 0)
    }

    /// Check if an SDValue represents a specific constant value.
    fn is_constant(&self, x86_dag: &X86SelectionDAG, val: SDValue, expected: i64) -> bool {
        let node = match x86_dag.dag.get_node(val.node_id) {
            Some(n) => n,
            None => return false,
        };

        if node.opcode == SDOpcode::Constant || node.opcode == SDOpcode::TargetConstant {
            // Try to read the constant value from operand or node info
            if let Some(tc) = x86_dag
                .get_node_info(val.node_id)
                .and_then(|n| n.target_constant)
            {
                return tc == expected;
            }
        }
        false
    }

    /// Get constant value from an SDValue.
    fn get_const_val(&self, x86_dag: &X86SelectionDAG, val: SDValue) -> Option<i64> {
        let node = x86_dag.dag.get_node(val.node_id)?;
        if node.opcode == SDOpcode::Constant || node.opcode == SDOpcode::TargetConstant {
            x86_dag
                .get_node_info(val.node_id)
                .and_then(|n| n.target_constant)
        } else {
            None
        }
    }
}

// ============================================================================
// 6. X86DAGLegalize — DAG legalization for X86
// ============================================================================

/// X86-specific DAG legalizer.
///
/// Handles type legalization and operation legalization for X86:
/// - Type legalization: i1 → i8, i128 → 2× i64 (or libcall), vector splitting
/// - Operation legalization: 64-bit ops on 32-bit, libcalls for unsupported ops
/// - Vector legalization: SSE/AVX/AVX-512 rules
pub struct X86DAGLegalize {
    /// The generic target legalizer
    pub target_legalizer: TargetLegalizer,
    /// Type legalizer for X86
    pub type_legalizer: TypeLegalizer,
    /// Subtarget for feature checks
    pub subtarget: X86Subtarget,
}

impl X86DAGLegalize {
    /// Create a new X86DAGLegalize with X86-64 defaults.
    pub fn new(subtarget: X86Subtarget) -> Self {
        let target_legalizer = TargetLegalizer::x86_64();
        let type_legalizer = Self::create_type_legalizer(&subtarget);
        Self {
            target_legalizer,
            type_legalizer,
            subtarget,
        }
    }

    /// Create a new X86DAGLegalize for 32-bit X86.
    pub fn new_32bit(subtarget: X86Subtarget) -> Self {
        let target_legalizer = TargetLegalizer::minimal_32bit();
        let type_legalizer = Self::create_type_legalizer_32(&subtarget);
        Self {
            target_legalizer,
            type_legalizer,
            subtarget,
        }
    }

    /// Create a type legalizer for X86-64.
    fn create_type_legalizer(subtarget: &X86Subtarget) -> TypeLegalizer {
        let mut tl = TypeLegalizer::new();
        tl.target_pointer_size = 64;
        tl.max_legal_int_size = 64;
        tl.min_legal_int_size = 8;
        tl.supports_i1 = false; // i1 is promoted to i8

        // Setup vector widths based on feature set
        if subtarget.has_avx512() {
            tl.legal_vector_widths = vec![128, 256, 512];
            tl = tl.with_avx512();
            // tl.has_avx2 = true; // set via with_avx
            // tl.has_avx = true; // set via with_avx
        } else if subtarget.has_avx2() || subtarget.has_avx() {
            tl.legal_vector_widths = vec![128, 256];
            // tl.has_avx2 set via with_avx method
            // tl.has_avx = true; // set via with_avx
        } else {
            tl.legal_vector_widths = vec![128]; // SSE2 minimum
        }

        tl
    }

    /// Create a type legalizer for 32-bit X86.
    fn create_type_legalizer_32(subtarget: &X86Subtarget) -> TypeLegalizer {
        let mut tl = Self::create_type_legalizer(subtarget);
        tl.target_pointer_size = 32;
        tl.max_legal_int_size = 32;
        tl
    }

    /// Legalize an X86SelectionDAG.
    pub fn legalize(&mut self, x86_dag: &mut X86SelectionDAG) {
        // Step 1: Type legalization
        self.type_legalizer
            .legalize_dag(&mut x86_dag.dag, &x86_dag.dag.nodes.clone());

        // Step 2: Operation legalization
        self.target_legalizer.legalize(&mut x86_dag.dag);

        // Step 3: X86-specific operation legalization
        self.legalize_x86_ops(x86_dag);
    }

    /// X86-specific operation legalization.
    fn legalize_x86_ops(&mut self, x86_dag: &mut X86SelectionDAG) {
        let node_ids: Vec<usize> = (0..x86_dag.dag.nodes.len()).collect();

        for node_id in node_ids {
            if let Some(node) = x86_dag.dag.get_node(node_id).cloned() {
                match node.opcode {
                    // 64-bit operations on 32-bit target need expansion
                    SDOpcode::Add
                    | SDOpcode::Sub
                    | SDOpcode::Mul
                    | SDOpcode::And
                    | SDOpcode::Or
                    | SDOpcode::Xor => {
                        self.legalize_wide_int_op(x86_dag, node_id);
                    }

                    // Division may need libcalls
                    SDOpcode::SDiv | SDOpcode::UDiv => {
                        self.legalize_div(x86_dag, node_id);
                    }

                    // Select may need branch conversion
                    SDOpcode::Select => {
                        self.legalize_select(x86_dag, node_id);
                    }

                    // Vector operations
                    SDOpcode::BuildVector => {
                        self.legalize_build_vector(x86_dag, node_id);
                    }

                    SDOpcode::ExtractElement => {
                        self.legalize_extract_element(x86_dag, node_id);
                    }

                    _ => {}
                }
            }
        }
    }

    /// Legalize wide integer operations (e.g., i64 on 32-bit target).
    fn legalize_wide_int_op(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        let ty = match node.get_value_type(0) {
            Some(t) => t.clone(),
            None => return,
        };

        let ty_bits = Self::type_size_bits(&ty);
        let max_bits = if x86_dag.is_64bit { 64 } else { 32 };

        if ty_bits <= max_bits {
            return; // already legal
        }

        // For i128 → split into two i64 operations
        if ty_bits == 128 {
            // Would emit: lo = op(lo1, lo2); hi = op_with_carry(hi1, hi2)
            // For now, replace with libcall for division or expand for others
            if node.opcode == SDOpcode::SDiv || node.opcode == SDOpcode::UDiv {
                self.replace_with_libcall_128_div(x86_dag, node_id);
            }
        }
    }

    /// Replace a 128-bit division with a libcall.
    fn replace_with_libcall_128_div(&mut self, _x86_dag: &mut X86SelectionDAG, _node_id: usize) {
        // Would emit: call __divti3 / __udivti3
    }

    /// Legalize division operations.
    fn legalize_div(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        let ty = match node.get_value_type(0) {
            Some(t) => t.clone(),
            None => return,
        };

        let ty_bits = Self::type_size_bits(&ty);

        // i8/i16 division needs promotion to i32 on X86
        if ty_bits < 32 {
            // Would promote and then truncate
        }
    }

    /// Legalize select (may need CMOV).
    fn legalize_select(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        if x86_dag.subtarget.has_cmov() {
            return; // CMOV handles it
        }

        // Without CMOV, expand to branch sequence
        // Would replace select with: c = cond; br c ? true_label : false_label
    }

    /// Legalize build_vector for SSE/AVX.
    fn legalize_build_vector(&mut self, x86_dag: &mut X86SelectionDAG, node_id: usize) {
        let node = match x86_dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        let ty = match node.get_value_type(0) {
            Some(t) => t.clone(),
            None => return,
        };

        let num_elems = Self::vector_element_count(&ty);
        let max_elems = if x86_dag.subtarget.has_avx512() {
            16
        } else if x86_dag.subtarget.has_avx() || x86_dag.subtarget.has_avx2() {
            8
        } else {
            4
        }; // SSE: max 4 elements (128-bit)

        if num_elems > max_elems {
            // Need to split or scalarize
        }
    }

    /// Legalize extract_element.
    fn legalize_extract_element(&mut self, _x86_dag: &mut X86SelectionDAG, _node_id: usize) {
        // X86 supports extract_element via PEXTR* instructions for SSE4.1+
    }

    // ---- Helpers ----

    /// Get the size of a type in bits.
    fn type_size_bits(ty: &Type) -> u32 {
        match &ty.kind {
            crate::types::TypeKind::Integer { bits } => *bits,
            crate::types::TypeKind::Float => 32,
            crate::types::TypeKind::Double => 64,
            crate::types::TypeKind::Pointer { .. } => 64,
            _ => 32,
        }
    }

    /// Get the number of elements in a vector type.
    fn vector_element_count(ty: &Type) -> u32 {
        match &ty.kind {
            crate::types::TypeKind::FixedVector { len, .. } => *len,
            _ => 1,
        }
    }
}

// ============================================================================
// 7. X86DAGToDAGISel — DAG-to-DAG instruction selection
// ============================================================================

/// X86 DAG-to-DAG instruction selector.
///
/// Walks the SelectionDAG and matches SDNode patterns against
/// X86 instruction patterns, emitting MachineInstr nodes.
///
/// This is a pattern-matching ISel (not table-driven in this implementation,
/// but designed to be compatible with X86GenDAGISel.inc table patterns).
pub struct X86DAGToDAGISel {
    /// The X86 SelectionDAG being selected from
    dag: Option<X86SelectionDAG>,
    /// The output MachineFunction
    mf: Option<MachineFunction>,
    /// Current MachineBasicBlock being processed
    current_mbb: Option<MachineBasicBlock>,
    /// X86 instruction info for lookup
    instr_info: X86InstrInfo,
    /// Register info for register assignment
    reg_info: X86RegisterInfo,
    /// Subtarget for feature-based selection
    subtarget: X86Subtarget,
    /// Map from SDValue node_id to virtual register number
    vreg_map: HashMap<usize, u32>,
    /// Next available virtual register number
    next_vreg: u32,
    /// Number of selected instructions
    num_selected: u64,
    /// Whether this is 64-bit mode
    is_64bit: bool,
}

impl X86DAGToDAGISel {
    /// Create a new X86DAGToDAGISel.
    pub fn new(subtarget: X86Subtarget) -> Self {
        Self {
            dag: None,
            mf: None,
            current_mbb: None,
            instr_info: X86InstrInfo::default(),
            reg_info: X86RegisterInfo::default(),
            subtarget,
            vreg_map: HashMap::new(),
            next_vreg: 0,
            num_selected: 0,
            is_64bit: true,
        }
    }

    /// Create for 32-bit mode.
    pub fn new_32bit(subtarget: X86Subtarget) -> Self {
        Self {
            dag: None,
            mf: None,
            current_mbb: None,
            instr_info: X86InstrInfo::default(),
            reg_info: X86RegisterInfo::default(),
            subtarget,
            vreg_map: HashMap::new(),
            next_vreg: 0,
            num_selected: 0,
            is_64bit: false,
        }
    }

    /// Select instructions from an X86SelectionDAG into a MachineFunction.
    pub fn select(&mut self, x86_dag: X86SelectionDAG, mf: &mut MachineFunction) {
        self.dag = Some(x86_dag);
        self.num_selected = 0;

        // Walk the DAG in topological order
        self.select_dag_nodes();
    }

    /// Walk DAG nodes and select each.
    fn select_dag_nodes(&mut self) {
        let dag = match &self.dag {
            Some(d) => d,
            None => return,
        };

        let node_count = dag.dag.nodes.len();
        let mut selected: Vec<bool> = vec![false; node_count];

        // Process nodes in order (roughly topological since built in order)
        for node_id in 0..node_count {
            if selected[node_id] {
                continue;
            }
            self.select_node(node_id, &mut selected);
        }

        // Process all_nodes for any unvisited nodes
        for node_id in 0..dag.dag.all_nodes.len() {
            if node_id < selected.len() && selected[node_id] {
                continue;
            }
            // Access via get_node if within range
        }
    }

    /// Select a single DAG node.
    fn select_node(&mut self, node_id: usize, selected: &mut Vec<bool>) {
        // First, recursively select operand nodes
        let dag = match &self.dag {
            Some(d) => d,
            None => return,
        };

        let node = match dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return,
        };

        // Select operands first (bottom-up)
        for op in &node.operands {
            if op.node_id < selected.len() && !selected[op.node_id] {
                self.select_node(op.node_id, selected);
            }
        }

        // Now select this node
        if let Some(instrs) = self.select_instruction(node_id) {
            for instr in instrs {
                if let Some(ref mut mbb) = self.current_mbb {
                    mbb.instructions.push(instr);
                    self.num_selected += 1;
                }
            }
        }

        if node_id < selected.len() {
            selected[node_id] = true;
        }
    }

    /// Select the instruction(s) for a given DAG node.
    fn select_instruction(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;

        // Check if this is an X86 target node
        if let Some(info) = dag.get_node_info(node_id) {
            if let Some(x86_op) = info.x86_opcode {
                return self.select_target_node(node_id, x86_op, info);
            }
        }

        // Generic node selection
        match node.opcode {
            SDOpcode::Add => self.select_add(node_id),
            SDOpcode::Sub => self.select_sub(node_id),
            SDOpcode::Mul => self.select_mul(node_id),
            SDOpcode::SDiv => self.select_sdiv(node_id),
            SDOpcode::UDiv => self.select_udiv(node_id),
            SDOpcode::And => self.select_and(node_id),
            SDOpcode::Or => self.select_or(node_id),
            SDOpcode::Xor => self.select_xor(node_id),
            SDOpcode::Shl => self.select_shl(node_id),
            SDOpcode::Sra => self.select_sra(node_id),
            SDOpcode::Srl => self.select_srl(node_id),
            SDOpcode::Load => self.select_load(node_id),
            SDOpcode::Store => self.select_store(node_id),
            SDOpcode::Br => self.select_br(node_id),
            SDOpcode::BrCond => self.select_brcond(node_id),
            SDOpcode::Ret => self.select_ret(node_id),
            SDOpcode::Call => self.select_call(node_id),
            SDOpcode::SetCC => self.select_setcc(node_id),
            SDOpcode::Select => self.select_select(node_id),
            SDOpcode::ZExt => self.select_zext(node_id),
            SDOpcode::SExt => self.select_sext(node_id),
            SDOpcode::Trunc => self.select_trunc(node_id),
            SDOpcode::FAdd => self.select_fadd(node_id),
            SDOpcode::FSub => self.select_fsub(node_id),
            SDOpcode::FMul => self.select_fmul(node_id),
            SDOpcode::FDiv => self.select_fdiv(node_id),
            SDOpcode::FSqrt => self.select_fsqrt(node_id),
            SDOpcode::FAbs => self.select_fabs(node_id),
            SDOpcode::FNeg => self.select_fneg(node_id),
            SDOpcode::SIToFP => self.select_sitofp(node_id),
            SDOpcode::UIToFP => self.select_uitofp(node_id),
            SDOpcode::FPToSI => self.select_fptosi(node_id),
            SDOpcode::FPToUI => self.select_fptoui(node_id),
            SDOpcode::FrameIndex => self.select_frameindex(node_id),
            SDOpcode::Constant => self.select_constant(node_id),
            SDOpcode::ConstantFP => self.select_constant_fp(node_id),
            SDOpcode::CopyToReg => self.select_copy_to_reg(node_id),
            SDOpcode::CopyFromReg => self.select_copy_from_reg(node_id),
            SDOpcode::BuildVector => self.select_build_vector(node_id),
            SDOpcode::ExtractElement => self.select_extract_element(node_id),
            SDOpcode::InsertElement => self.select_insert_element(node_id),
            SDOpcode::TokenFactor | SDOpcode::EntryToken => Some(Vec::new()),
            _ => None,
        }
    }

    /// Select an X86 target-specific node.
    fn select_target_node(
        &mut self,
        node_id: usize,
        x86_op: X86ISD,
        info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        match x86_op {
            X86ISD::Cmp | X86ISD::Test => self.select_x86_cmp(node_id, info),
            X86ISD::FCmp => self.select_x86_fcmp(node_id, info),
            X86ISD::SetCC => self.select_x86_setcc(node_id, info),
            X86ISD::CMov => self.select_x86_cmov(node_id, info),
            X86ISD::Call => self.select_x86_call(node_id, info),
            X86ISD::Ret => self.select_x86_ret(node_id, info),
            X86ISD::TailCall => self.select_x86_tail_call(node_id, info),
            X86ISD::LeaAddr => self.select_x86_lea(node_id, info),
            X86ISD::Shld => self.select_x86_shld(node_id, info),
            X86ISD::Shrd => self.select_x86_shrd(node_id, info),
            X86ISD::AddCarry => self.select_x86_adc(node_id, info),
            X86ISD::SubBorrow => self.select_x86_sbb(node_id, info),
            X86ISD::VBroadcast => self.select_x86_vbroadcast(node_id, info),
            X86ISD::VShuffle => self.select_x86_vshuffle(node_id, info),
            X86ISD::Fmadd => self.select_x86_fmadd(node_id, info),
            X86ISD::Fmsub => self.select_x86_fmsub(node_id, info),
            X86ISD::Gather => self.select_x86_gather(node_id, info),
            _ => None,
        }
    }

    // ---- Integer Arithmetic Selection ----

    fn select_add(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = node.operands[1];

        // Check if RHS is an immediate
        if let Some(imm) = self.get_immediate(rhs) {
            let dst = self.new_vreg();
            let mut instr = MachineInstr::new(
                X86Opcode::ADD as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(lhs),
                    MachineOperand::Imm(imm),
                ],
                false,
            );
            self.set_vreg(node_id, dst);
            return Some(vec![instr]);
        }

        let rhs_vreg = self.get_vreg_for(rhs);
        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::ADD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs_vreg),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_sub(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = node.operands[1];

        if let Some(imm) = self.get_immediate(rhs) {
            let dst = self.new_vreg();
            let mut instr = MachineInstr::new(
                X86Opcode::SUB as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(lhs),
                    MachineOperand::Imm(imm),
                ],
                false,
            );
            self.set_vreg(node_id, dst);
            return Some(vec![instr]);
        }

        let rhs_vreg = self.get_vreg_for(rhs);
        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::SUB as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs_vreg),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_mul(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = node.operands[1];
        let dst = self.new_vreg();

        if let Some(imm) = self.get_immediate(rhs) {
            // IMUL r, r/m, imm is available
            let mut instr = MachineInstr::new(
                X86Opcode::IMUL as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(lhs),
                    MachineOperand::Imm(imm),
                ],
                false,
            );
            self.set_vreg(node_id, dst);
            return Some(vec![instr]);
        }

        let rhs_vreg = self.get_vreg_for(rhs);
        let mut instr = MachineInstr::new(
            X86Opcode::IMUL as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs_vreg),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_sdiv(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        // IDIV: uses EDX:EAX / op → quotient in EAX, remainder in EDX
        // Need to emit: CDQ (sign-extend EAX→EDX:EAX), then IDIV
        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instrs = Vec::new();
        // CDQ / CQO
        let cdq = MachineInstr::new(
            X86Opcode::ADD as u32, // placeholder for CDQ
            vec![MachineOperand::Reg(lhs)],
            false,
        );
        instrs.push(cdq);

        let idiv = MachineInstr::new(
            X86Opcode::IDIV as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        instrs.push(idiv);

        self.set_vreg(node_id, dst);
        Some(instrs)
    }

    fn select_udiv(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instrs = Vec::new();
        // XOR EDX, EDX to zero high part
        let zero_edx = MachineInstr::new(
            X86Opcode::XOR as u32,
            vec![
                MachineOperand::Reg(self.new_vreg()),
                MachineOperand::Reg(self.new_vreg()),
            ],
            false,
        );
        instrs.push(zero_edx);

        let div = MachineInstr::new(
            X86Opcode::DIV as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        instrs.push(div);

        self.set_vreg(node_id, dst);
        Some(instrs)
    }

    fn select_and(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_binary_op(node_id, X86Opcode::AND)
    }

    fn select_or(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_binary_op(node_id, X86Opcode::OR)
    }

    fn select_xor(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_binary_op(node_id, X86Opcode::XOR)
    }

    fn select_shl(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_shift_op(node_id, X86Opcode::SHL)
    }

    fn select_sra(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_shift_op(node_id, X86Opcode::SAR)
    }

    fn select_srl(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_shift_op(node_id, X86Opcode::SHR)
    }

    fn select_binary_op(&mut self, node_id: usize, opcode: X86Opcode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = node.operands[1];
        let dst = self.new_vreg();

        if let Some(imm) = self.get_immediate(rhs) {
            let mut instr = MachineInstr::new(
                opcode as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(lhs),
                    MachineOperand::Imm(imm),
                ],
                false,
            );
            self.set_vreg(node_id, dst);
            return Some(vec![instr]);
        }

        let rhs_vreg = self.get_vreg_for(rhs);
        let mut instr = MachineInstr::new(
            opcode as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs_vreg),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_shift_op(&mut self, node_id: usize, opcode: X86Opcode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let amount = node.operands[1];

        // SHL/SHR/SAR can only shift by CL or an immediate
        let dst = self.new_vreg();

        if let Some(imm) = self.get_immediate(amount) {
            let shift_imm = imm & 0x3F; // mask to 6 bits (64-bit) or 5 bits (32-bit)
            let mut instr = MachineInstr::new(
                opcode as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(lhs),
                    MachineOperand::Imm(shift_imm),
                ],
                false,
            );
            self.set_vreg(node_id, dst);
            return Some(vec![instr]);
        }

        // Need to move shift amount to CL
        let amount_vreg = self.get_vreg_for(amount);
        let cl_vreg = self.new_vreg();

        // MOV CL, amount
        let mov_cl = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![
                MachineOperand::Reg(cl_vreg),
                MachineOperand::Reg(amount_vreg),
            ],
            false,
        );

        let shift = MachineInstr::new(
            opcode as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(cl_vreg),
            ],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov_cl, shift])
    }

    // ---- Memory Operations ----

    fn select_load(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let ptr = node.operands[1]; // operand[0] is chain
        let ptr_vreg = self.get_vreg_for(ptr);

        // Build addressing mode
        if let Some(info) = dag.get_node_info(node_id) {
            if let Some(ref addr_mode) = info.addressing_mode {
                return self.select_load_with_addr(node_id, ptr_vreg, addr_mode);
            }
        }

        // Simple MOV from [ptr]
        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(ptr_vreg)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_load_with_addr(
        &mut self,
        node_id: usize,
        base_vreg: u32,
        _addr_mode: &X86AddressMode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(base_vreg)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_store(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let val = node.operands[1];
        let ptr = node.operands[2];
        let val_vreg = self.get_vreg_for(val);
        let ptr_vreg = self.get_vreg_for(ptr);

        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(ptr_vreg), MachineOperand::Reg(val_vreg)],
            false,
        );
        // Note: semantics are [dest] = src, but MOV r/m, r stores to memory
        // For simplicity, we use MOV with the platform convention
        self.set_vreg(node_id, 0);
        Some(vec![instr])
    }

    // ---- Control Flow ----

    fn select_br(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let target = node.operands[1];
        let target_name = self.get_label(target);

        let mut instr = MachineInstr::new(
            X86Opcode::JMP as u32,
            vec![MachineOperand::Label(target_name)],
            false,
        );
        Some(vec![instr])
    }

    fn select_brcond(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 4 {
            return None;
        }

        let cond = node.operands[1];
        let true_dest = node.operands[2];
        let false_dest = node.operands[3];

        let true_label = self.get_label(true_dest);
        let false_label = self.get_label(false_dest);

        // Extract condition code from cond node
        let cc = dag
            .get_node_info(cond.node_id)
            .and_then(|n| n.condition_code)
            .unwrap_or(X86CondCode::E);

        let jcc_opcode = self.cond_code_to_jcc(cc);

        let mut instrs = Vec::new();

        // Jcc true_label
        let jcc = MachineInstr::new(
            jcc_opcode as u32,
            vec![MachineOperand::Label(true_label)],
            false,
        );
        instrs.push(jcc);

        // JMP false_label
        let jmp = MachineInstr::new(
            X86Opcode::JMP as u32,
            vec![MachineOperand::Label(false_label)],
            false,
        );
        instrs.push(jmp);

        Some(instrs)
    }

    fn select_ret(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let mut instr = MachineInstr::new(X86Opcode::RET as u32, Vec::new(), false);
        Some(vec![instr])
    }

    fn select_call(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;

        if node.operands.len() < 2 {
            return None;
        }

        let callee = node.operands[1];
        let callee_name = self.get_label(callee);

        let mut instr = MachineInstr::new(
            X86Opcode::CALL as u32,
            vec![MachineOperand::Label(callee_name)],
            false,
        );
        Some(vec![instr])
    }

    // ---- Comparison ----

    fn select_setcc(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let info = dag.get_node_info(node_id)?;
        let cc = info.condition_code?;

        let setcc_opcode = self.cond_code_to_setcc(cc);
        let dst = self.new_vreg();

        let mut instr =
            MachineInstr::new(setcc_opcode as u32, vec![MachineOperand::Reg(dst)], false);
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_select(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        // If we have CMOV and the condition is suitable, use it
        if self.subtarget.has_cmov() {
            return self.select_cmov(node_id);
        }

        // Fallback: emit branch sequence
        self.select_select_as_branch(node_id)
    }

    fn select_cmov(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        let info = dag.get_node_info(node_id)?;
        let cc = info.condition_code.unwrap_or(X86CondCode::E);

        let true_val = node.operands[1];
        let false_val = node.operands[2];

        let true_vreg = self.get_vreg_for(true_val);
        let false_vreg = self.get_vreg_for(false_val);
        let dst = self.new_vreg();

        // MOV dst, false_val (set default)
        let mov = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(false_vreg)],
            false,
        );

        let cmov_opcode = self.cond_code_to_cmov(cc);
        let cmov = MachineInstr::new(
            cmov_opcode as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(true_vreg)],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov, cmov])
    }

    fn select_select_as_branch(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // Without CMOV: emit compare + branch + mov
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let cond = node.operands[0];
        let true_val = node.operands[1];
        let false_val = node.operands[2];

        let cond_vreg = self.get_vreg_for(cond);
        let true_vreg = self.get_vreg_for(true_val);
        let false_vreg = self.get_vreg_for(false_val);
        let dst = self.new_vreg();

        // CMP cond, 0
        let cmp = MachineInstr::new(
            X86Opcode::CMP as u32,
            vec![MachineOperand::Reg(cond_vreg), MachineOperand::Imm(0)],
            false,
        );

        // JE .true_label (labels not emitted here; simplified)
        let dst2 = self.new_vreg();
        let mov_true = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst2), MachineOperand::Reg(true_vreg)],
            false,
        );

        let mov_false = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst2), MachineOperand::Reg(false_vreg)],
            false,
        );

        // Simplified: just use the false path (in practice would emit branches)
        self.set_vreg(node_id, dst2);
        Some(vec![cmp, mov_false, mov_true])
    }

    // ---- Extensions ----

    fn select_zext(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::MOVZX as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_sext(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::MOVSX as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_trunc(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // Truncation on X86 is implicit: just use the low part of the register
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        // Truncation is a no-op: the low bits are already there
        self.set_vreg(node_id, src);
        Some(Vec::new())
    }

    // ---- Floating Point ----

    fn select_fadd(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_fp_binary_op(node_id, X86Opcode::ADDSS, X86Opcode::ADDSD)
    }

    fn select_fsub(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_fp_binary_op(node_id, X86Opcode::SUBSS, X86Opcode::SUBSD)
    }

    fn select_fmul(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_fp_binary_op(node_id, X86Opcode::MULSS, X86Opcode::MULSD)
    }

    fn select_fdiv(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_fp_binary_op(node_id, X86Opcode::DIVSS, X86Opcode::DIVSD)
    }

    fn select_fsqrt(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        // Check if float or double
        let opcode = X86Opcode::SQRTSS; // default to float

        let mut instr = MachineInstr::new(
            opcode as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_fabs(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // FABS on X86 SSE: ANDPS with sign-mask (0x7FFFFFFF...)
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();
        let mask_vreg = self.new_vreg();

        // MOV mask, 0x7FFFFFFF (or 0x7FFFFFFFFFFFFFFF for double)
        let mov_mask = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![
                MachineOperand::Reg(mask_vreg),
                MachineOperand::Imm(0x7FFFFFFF),
            ],
            false,
        );

        // ANDPS dst, src, mask
        let andps = MachineInstr::new(
            X86Opcode::ANDPS as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(src),
                MachineOperand::Reg(mask_vreg),
            ],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov_mask, andps])
    }

    fn select_fneg(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // FNEG on X86 SSE: XORPS with sign-bit mask (0x80000000...)
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();
        let sign_mask_vreg = self.new_vreg();

        let mov_mask = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![
                MachineOperand::Reg(sign_mask_vreg),
                MachineOperand::Imm(0x80000000u64 as i64),
            ],
            false,
        );

        let xorps = MachineInstr::new(
            X86Opcode::XORPS as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(src),
                MachineOperand::Reg(sign_mask_vreg),
            ],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov_mask, xorps])
    }

    fn select_fp_binary_op(
        &mut self,
        node_id: usize,
        sse_op: X86Opcode,
        sse2_op: X86Opcode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        // Pick opcode based on type (float = SSE, double = SSE2)
        let opcode = sse2_op; // default to double

        let mut instr = MachineInstr::new(
            opcode as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    // ---- Conversions ----

    fn select_sitofp(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::CVTSI2SD as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_uitofp(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // UINT_TO_FP is more complex on X86 (needs special handling)
        // For now, use CVTSI2SD (works for positive values < 2^63)
        self.select_sitofp(node_id)
    }

    fn select_fptosi(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::CVTSD2SI as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_fptoui(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        self.select_fptosi(node_id)
    }

    // ---- Address / Frame ----

    fn select_frameindex(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // Frame index is resolved during register allocation / frame lowering
        // Emit LEA r, [rbp + offset]
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::LEA as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(5), // RBP
                MachineOperand::Imm(node_id as i64),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_constant(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let info = dag.get_node_info(node_id);
        let val = info.and_then(|n| n.target_constant).unwrap_or(0);

        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Imm(val)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_constant_fp(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        // FP constants are loaded from constant pool
        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::MOVSD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Imm(node_id as i64),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    // ---- Register Copy ----

    fn select_copy_to_reg(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let val = node.operands[2];
        let val_vreg = self.get_vreg_for(val);

        // Get target register from node info
        let target_reg = dag
            .get_node_info(node_id)
            .and_then(|n| n.target_constant)
            .map(|tc| tc as u32)
            .unwrap_or(0);

        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![
                MachineOperand::Reg(target_reg),
                MachineOperand::Reg(val_vreg),
            ],
            false,
        );
        Some(vec![instr])
    }

    fn select_copy_from_reg(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let source_reg = dag
            .get_node_info(node_id)
            .and_then(|n| n.target_constant)
            .map(|tc| tc as u32)
            .unwrap_or(0);

        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(source_reg)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    // ---- Vector ----

    fn select_build_vector(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        let dst = self.new_vreg();

        // Emit a sequence of MOVD/INSERTPS or MOVUPS
        let mut instrs = Vec::new();

        // First element: MOVD xmm, r/m
        if let Some(&first) = node.operands.first() {
            let first_vreg = self.get_vreg_for(first);
            let movd = MachineInstr::new(
                X86Opcode::MOVD as u32,
                vec![MachineOperand::Reg(dst), MachineOperand::Reg(first_vreg)],
                false,
            );
            instrs.push(movd);
        }

        // Remaining elements: PINSRD / PINSRQ
        for (i, &elem) in node.operands.iter().enumerate().skip(1) {
            let elem_vreg = self.get_vreg_for(elem);
            let pinsr = MachineInstr::new(
                X86Opcode::PINSRD as u32,
                vec![
                    MachineOperand::Reg(dst),
                    MachineOperand::Reg(elem_vreg),
                    MachineOperand::Imm(i as i64),
                ],
                false,
            );
            instrs.push(pinsr);
        }

        self.set_vreg(node_id, dst);
        Some(instrs)
    }

    fn select_extract_element(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let vec = self.get_vreg_for(node.operands[0]);
        let idx = self.get_immediate(node.operands[1]).unwrap_or(0);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::PEXTRD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(vec),
                MachineOperand::Imm(idx),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_insert_element(&mut self, node_id: usize) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let vec = self.get_vreg_for(node.operands[0]);
        let elt = self.get_vreg_for(node.operands[1]);
        let idx = self.get_immediate(node.operands[2]).unwrap_or(0);
        let dst = self.new_vreg();

        // MOVAPS dst, vec (copy first)
        let mov = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(vec)],
            false,
        );

        let pinsr = MachineInstr::new(
            X86Opcode::PINSRD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(elt),
                MachineOperand::Imm(idx),
            ],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov, pinsr])
    }

    // ---- X86 Target-Specific Selection ----

    fn select_x86_cmp(&mut self, node_id: usize, info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = node.operands[1];

        if let Some(imm) = self.get_immediate(rhs) {
            let mut instr = MachineInstr::new(
                X86Opcode::CMP as u32,
                vec![MachineOperand::Reg(lhs), MachineOperand::Imm(imm)],
                false,
            );
            return Some(vec![instr]);
        }

        let rhs_vreg = self.get_vreg_for(rhs);
        let mut instr = MachineInstr::new(
            X86Opcode::CMP as u32,
            vec![MachineOperand::Reg(lhs), MachineOperand::Reg(rhs_vreg)],
            false,
        );
        Some(vec![instr])
    }

    fn select_x86_fcmp(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);

        // UCOMISD for double, UCOMISS for float
        let mut instr = MachineInstr::new(
            X86Opcode::UCOMISD as u32,
            vec![MachineOperand::Reg(lhs), MachineOperand::Reg(rhs)],
            false,
        );
        Some(vec![instr])
    }

    fn select_x86_setcc(&mut self, node_id: usize, info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let cc = info.condition_code?;
        let setcc_opcode = self.cond_code_to_setcc(cc);
        let dst = self.new_vreg();

        let mut instr =
            MachineInstr::new(setcc_opcode as u32, vec![MachineOperand::Reg(dst)], false);
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_cmov(&mut self, node_id: usize, info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let cc = info.condition_code?;
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;

        if node.operands.len() < 3 {
            return None;
        }

        let flag = node.operands[0];
        let true_val = node.operands[1];
        let false_val = node.operands[2];

        let true_vreg = self.get_vreg_for(true_val);
        let false_vreg = self.get_vreg_for(false_val);
        let dst = self.new_vreg();

        // MOV dst, false_val
        let mov = MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(false_vreg)],
            false,
        );

        let cmov_opcode = self.cond_code_to_cmov(cc);
        let cmov = MachineInstr::new(
            cmov_opcode as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(true_vreg)],
            false,
        );

        self.set_vreg(node_id, dst);
        Some(vec![mov, cmov])
    }

    fn select_x86_call(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let callee = node.operands[1];
        let callee_name = self.get_label(callee);

        let mut instr = MachineInstr::new(
            X86Opcode::CALL as u32,
            vec![MachineOperand::Label(callee_name)],
            false,
        );
        Some(vec![instr])
    }

    fn select_x86_ret(&mut self, _node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let mut instr = MachineInstr::new(X86Opcode::RET as u32, Vec::new(), false);
        Some(vec![instr])
    }

    fn select_x86_tail_call(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        // Tail call: JMP to callee instead of CALL
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let callee = node.operands[1];
        let callee_name = self.get_label(callee);

        let mut instr = MachineInstr::new(
            X86Opcode::JMP as u32,
            vec![MachineOperand::Label(callee_name)],
            false,
        );
        Some(vec![instr])
    }

    fn select_x86_lea(&mut self, node_id: usize, info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let addr_mode = match &info.addressing_mode {
            Some(am) => am.clone(),
            None => X86AddressMode::default(),
        };

        let dst = self.new_vreg();
        let mut instr = MachineInstr::new(
            X86Opcode::LEA as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(0), // placeholder base
                MachineOperand::Imm(addr_mode.displacement),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_shld(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::SHLD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_shrd(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::SHRD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_adc(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::ADC as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_sbb(&mut self, node_id: usize, _info: &X86DAGNode) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let lhs = self.get_vreg_for(node.operands[0]);
        let rhs = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::SBB as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_vbroadcast(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.is_empty() {
            return None;
        }

        let src = self.get_vreg_for(node.operands[0]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::VBROADCASTSS as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_vshuffle(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let src1 = self.get_vreg_for(node.operands[0]);
        let src2 = self.get_vreg_for(node.operands[1]);
        let mask = self.get_immediate(node.operands[2]).unwrap_or(0);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::SHUFPS as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(src1),
                MachineOperand::Reg(src2),
                MachineOperand::Imm(mask),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_fmadd(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let a = self.get_vreg_for(node.operands[0]);
        let b = self.get_vreg_for(node.operands[1]);
        let c = self.get_vreg_for(node.operands[2]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::VFMADD132PD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(a),
                MachineOperand::Reg(b),
                MachineOperand::Reg(c),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_fmsub(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 3 {
            return None;
        }

        let a = self.get_vreg_for(node.operands[0]);
        let b = self.get_vreg_for(node.operands[1]);
        let c = self.get_vreg_for(node.operands[2]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::VFMSUB132PD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(a),
                MachineOperand::Reg(b),
                MachineOperand::Reg(c),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    fn select_x86_gather(
        &mut self,
        node_id: usize,
        _info: &X86DAGNode,
    ) -> Option<Vec<MachineInstr>> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(node_id)?;
        if node.operands.len() < 2 {
            return None;
        }

        let base = self.get_vreg_for(node.operands[0]);
        let index = self.get_vreg_for(node.operands[1]);
        let dst = self.new_vreg();

        let mut instr = MachineInstr::new(
            X86Opcode::VPGATHERDD as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(base),
                MachineOperand::Reg(index),
            ],
            false,
        );
        self.set_vreg(node_id, dst);
        Some(vec![instr])
    }

    // ---- Condition Code Helpers ----

    fn cond_code_to_jcc(&self, cc: X86CondCode) -> X86Opcode {
        match cc {
            X86CondCode::O => X86Opcode::JO,
            X86CondCode::NO => X86Opcode::JNO,
            X86CondCode::B => X86Opcode::JB,
            X86CondCode::AE => X86Opcode::JAE,
            X86CondCode::E => X86Opcode::JE,
            X86CondCode::NE => X86Opcode::JNE,
            X86CondCode::BE => X86Opcode::JBE,
            X86CondCode::A => X86Opcode::JA,
            X86CondCode::S => X86Opcode::JS,
            X86CondCode::NS => X86Opcode::JNS,
            X86CondCode::P => X86Opcode::JP,
            X86CondCode::NP => X86Opcode::JNP,
            X86CondCode::L => X86Opcode::JL,
            X86CondCode::GE => X86Opcode::JGE,
            X86CondCode::LE => X86Opcode::JLE,
            X86CondCode::G => X86Opcode::JG,
        }
    }

    fn cond_code_to_setcc(&self, cc: X86CondCode) -> X86Opcode {
        match cc {
            X86CondCode::O => X86Opcode::SETO,
            X86CondCode::NO => X86Opcode::SETNO,
            X86CondCode::B => X86Opcode::SETB,
            X86CondCode::AE => X86Opcode::SETAE,
            X86CondCode::E => X86Opcode::SETE,
            X86CondCode::NE => X86Opcode::SETNE,
            X86CondCode::BE => X86Opcode::SETBE,
            X86CondCode::A => X86Opcode::SETA,
            X86CondCode::S => X86Opcode::SETS,
            X86CondCode::NS => X86Opcode::SETNS,
            X86CondCode::P => X86Opcode::SETP,
            X86CondCode::NP => X86Opcode::SETNP,
            X86CondCode::L => X86Opcode::SETL,
            X86CondCode::GE => X86Opcode::SETGE,
            X86CondCode::LE => X86Opcode::SETLE,
            X86CondCode::G => X86Opcode::SETG,
        }
    }

    fn cond_code_to_cmov(&self, cc: X86CondCode) -> X86Opcode {
        match cc {
            X86CondCode::O => X86Opcode::CMOVO,
            X86CondCode::NO => X86Opcode::CMOVNO,
            X86CondCode::B => X86Opcode::CMOVB,
            X86CondCode::AE => X86Opcode::CMOVAE,
            X86CondCode::E => X86Opcode::CMOVE,
            X86CondCode::NE => X86Opcode::CMOVNE,
            X86CondCode::BE => X86Opcode::CMOVBE,
            X86CondCode::A => X86Opcode::CMOVA,
            X86CondCode::S => X86Opcode::CMOVS,
            X86CondCode::NS => X86Opcode::CMOVNS,
            X86CondCode::P => X86Opcode::CMOVP,
            X86CondCode::NP => X86Opcode::CMOVNP,
            X86CondCode::L => X86Opcode::CMOVL,
            X86CondCode::GE => X86Opcode::CMOVGE,
            X86CondCode::LE => X86Opcode::CMOVLE,
            X86CondCode::G => X86Opcode::CMOVG,
        }
    }

    // ---- Virtual Register Management ----

    fn new_vreg(&mut self) -> u32 {
        let vreg = self.next_vreg;
        self.next_vreg += 1;
        vreg
    }

    fn set_vreg(&mut self, node_id: usize, vreg: u32) {
        self.vreg_map.insert(node_id, vreg);
    }

    fn get_vreg_for(&mut self, val: SDValue) -> u32 {
        if let Some(&vreg) = self.vreg_map.get(&val.node_id) {
            return vreg;
        }
        // Allocate a new vreg for this value
        let vreg = self.new_vreg();
        self.vreg_map.insert(val.node_id, vreg);
        vreg
    }

    fn get_immediate(&self, val: SDValue) -> Option<i64> {
        let dag = self.dag.as_ref()?;
        let node = dag.dag.get_node(val.node_id)?;

        if node.opcode == SDOpcode::Constant || node.opcode == SDOpcode::TargetConstant {
            dag.get_node_info(val.node_id)
                .and_then(|n| n.target_constant)
                .or_else(|| {
                    // Try reading from constant pool
                    let fp_bits = dag
                        .dag
                        .constant_fp_pool
                        .iter()
                        .find(|(_, sv)| sv.node_id == val.node_id)
                        .map(|(k, _)| k.0);
                    fp_bits.map(|b| b as i64)
                })
        } else {
            None
        }
    }

    fn get_label(&self, val: SDValue) -> String {
        let dag = match self.dag.as_ref() {
            Some(d) => d,
            None => return format!("label_{}", val.node_id),
        };

        if let Some(node) = dag.dag.get_node(val.node_id) {
            if node.opcode == SDOpcode::GlobalAddress
                || node.opcode == SDOpcode::ExternalSymbol
                || node.opcode == SDOpcode::BlockAddress
            {
                return format!("symbol_{}", val.node_id);
            }
        }

        format!("bb_{}", val.node_id)
    }
}

// ============================================================================
// 8. X86SchedModel — Scheduling model for DAG nodes
// ============================================================================

/// X86 scheduling model for DAG-to-MI scheduling.
///
/// Provides latency, throughput, and resource usage for DAG nodes
/// based on the target microarchitecture.
pub struct X86DAGSchedModel {
    /// The microarchitecture scheduling model
    pub model: SchedModel,
    /// The specific model kind
    pub model_kind: X86SchedModelKind,
    /// Cache of SDNode opcode → itinerary mappings
    pub opcode_cache: HashMap<SDOpcode, Option<InstrItinerary>>,
    /// Cache of X86ISD → itinerary mappings
    pub x86_opcode_cache: HashMap<X86ISD, Option<InstrItinerary>>,
}

impl X86DAGSchedModel {
    /// Create a scheduling model for a specific X86 microarchitecture.
    pub fn new(model_kind: X86SchedModelKind) -> Self {
        let model = model_kind.model();
        Self {
            model,
            model_kind,
            opcode_cache: HashMap::new(),
            x86_opcode_cache: HashMap::new(),
        }
    }

    /// Create the default scheduling model (Zen3).
    pub fn default_x86() -> Self {
        Self::new(X86SchedModelKind::Zen3)
    }

    /// Get the latency for an SDNode opcode.
    pub fn get_latency(&mut self, opcode: SDOpcode) -> u32 {
        if let Some(&Some(ref itin)) = self.opcode_cache.get(&opcode) {
            return itin.latency;
        }

        let x86_opcode = self.map_sdopcode_to_x86(opcode);
        let itin = lookup_itinerary(&self.model, x86_opcode as u32);
        let latency = itin.as_ref().map(|i| i.latency).unwrap_or(1);

        self.opcode_cache.insert(opcode, itin);
        latency
    }

    /// Get the latency for an X86ISD node.
    pub fn get_x86_latency(&mut self, x86_op: X86ISD) -> u32 {
        if let Some(&Some(ref itin)) = self.x86_opcode_cache.get(&x86_op) {
            return itin.latency;
        }

        let x86_opcode = x86_op.to_x86_opcode().unwrap_or(X86Opcode::NOP);
        let itin = lookup_itinerary(&self.model, x86_opcode as u32);
        let latency = itin.as_ref().map(|i| i.latency).unwrap_or(1);

        self.x86_opcode_cache.insert(x86_op, itin);
        latency
    }

    /// Get the resource usage (ports) for an SDNode opcode.
    pub fn get_resources(&mut self, opcode: SDOpcode) -> Vec<ProcResource> {
        let x86_opcode = self.map_sdopcode_to_x86(opcode);
        instruction_resources(&self.model, x86_opcode as u32)
    }

    /// Get the number of µops for an SDNode opcode.
    pub fn get_uops(&mut self, opcode: SDOpcode) -> u32 {
        let x86_opcode = self.map_sdopcode_to_x86(opcode);
        instruction_uops(&self.model, x86_opcode as u32)
    }

    /// Map an SDNode opcode to a representative X86 opcode for scheduling.
    fn map_sdopcode_to_x86(&self, opcode: SDOpcode) -> X86Opcode {
        match opcode {
            SDOpcode::Add => X86Opcode::ADD,
            SDOpcode::Sub => X86Opcode::SUB,
            SDOpcode::Mul => X86Opcode::IMUL,
            SDOpcode::SDiv => X86Opcode::IDIV,
            SDOpcode::UDiv => X86Opcode::DIV,
            SDOpcode::And => X86Opcode::AND,
            SDOpcode::Or => X86Opcode::OR,
            SDOpcode::Xor => X86Opcode::XOR,
            SDOpcode::Shl => X86Opcode::SHL,
            SDOpcode::Sra => X86Opcode::SAR,
            SDOpcode::Srl => X86Opcode::SHR,
            SDOpcode::Load => X86Opcode::MOV,
            SDOpcode::Store => X86Opcode::MOV,
            SDOpcode::Br => X86Opcode::JMP,
            SDOpcode::BrCond => X86Opcode::JE,
            SDOpcode::Call => X86Opcode::CALL,
            SDOpcode::Ret => X86Opcode::RET,
            SDOpcode::FAdd => X86Opcode::ADDSS,
            SDOpcode::FSub => X86Opcode::SUBSS,
            SDOpcode::FMul => X86Opcode::MULSS,
            SDOpcode::FDiv => X86Opcode::DIVSS,
            SDOpcode::FSqrt => X86Opcode::SQRTSS,
            SDOpcode::ZExt | SDOpcode::SExt => X86Opcode::MOVSX,
            SDOpcode::Trunc => X86Opcode::MOV,
            SDOpcode::SIToFP | SDOpcode::UIToFP => X86Opcode::CVTSI2SD,
            SDOpcode::FPToSI | SDOpcode::FPToUI => X86Opcode::CVTSD2SI,
            SDOpcode::Select => X86Opcode::CMOVE,
            SDOpcode::SetCC => X86Opcode::SETE,
            _ => X86Opcode::NOP,
        }
    }

    /// Compute the critical path latency of a basic block DAG.
    pub fn compute_critical_path(&mut self, dag: &X86SelectionDAG) -> u32 {
        let mut latency: HashMap<usize, u32> = HashMap::new();
        let mut max_lat = 0;

        for node_id in 0..dag.dag.nodes.len() {
            let node = match dag.dag.get_node(node_id) {
                Some(n) => n,
                None => continue,
            };

            let node_lat = self.get_latency(node.opcode);

            // Compute max incoming latency
            let mut incoming_max = 0;
            for op in &node.operands {
                if let Some(&op_lat) = latency.get(&op.node_id) {
                    if op_lat > incoming_max {
                        incoming_max = op_lat;
                    }
                }
            }

            let total_lat = incoming_max + node_lat;
            latency.insert(node_id, total_lat);
            if total_lat > max_lat {
                max_lat = total_lat;
            }
        }

        max_lat
    }
}

// ============================================================================
// 9. X86InstrEmitter — Machine instruction emission from DAG
// ============================================================================

/// Emits MachineInstr from the SelectionDAG.
///
/// Takes the output of X86DAGToDAGISel and produces a fully formed
/// MachineFunction with MachineBasicBlock and MachineInstr nodes.
pub struct X86InstrEmitter {
    /// The X86 DAG-to-DAG ISel
    pub isel: X86DAGToDAGISel,
    /// The output machine function
    pub mf: MachineFunction,
    /// The X86 instruction info
    pub instr_info: X86InstrInfo,
    /// Virtual register counter for the machine function
    pub vreg_counter: u32,
}

impl X86InstrEmitter {
    /// Create a new X86InstrEmitter.
    pub fn new(subtarget: X86Subtarget, func_name: &str) -> Self {
        Self {
            isel: X86DAGToDAGISel::new(subtarget),
            mf: MachineFunction::new(func_name),
            instr_info: X86InstrInfo::default(),
            vreg_counter: 0,
        }
    }

    /// Create for 32-bit mode.
    pub fn new_32bit(subtarget: X86Subtarget, func_name: &str) -> Self {
        Self {
            isel: X86DAGToDAGISel::new_32bit(subtarget),
            mf: MachineFunction::new(func_name),
            instr_info: X86InstrInfo::default(),
            vreg_counter: 0,
        }
    }

    /// Run the full emission pipeline: ISel → MachineFunction.
    pub fn emit(&mut self, x86_dag: X86SelectionDAG) -> &MachineFunction {
        // Create a basic block for the function body
        let mbb_name = x86_dag
            .dag
            .nodes
            .first()
            .and_then(|n| n.debug_loc.clone())
            .unwrap_or_else(|| "entry".to_string());

        self.mf.push_block(MachineBasicBlock {
            name: mbb_name,
            instructions: Vec::new(),
            successors: Vec::new(),
        });
        self.isel.current_mbb = self.mf.blocks.last().cloned();

        // Run instruction selection
        self.isel.select(x86_dag, &mut self.mf);

        &self.mf
    }

    /// Emit a single machine instruction.
    pub fn emit_instr(&self, opcode: X86Opcode, operands: Vec<MachineOperand>) -> MachineInstr {
        MachineInstr::new(opcode as u32, operands, false)
    }

    /// Emit a MOV instruction.
    pub fn emit_mov(&self, dst: u32, src: u32) -> MachineInstr {
        MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        )
    }

    /// Emit a MOV with immediate.
    pub fn emit_mov_imm(&self, dst: u32, imm: i64) -> MachineInstr {
        MachineInstr::new(
            X86Opcode::MOV as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Imm(imm)],
            false,
        )
    }

    /// Emit a binary operation.
    pub fn emit_binary(&self, opcode: X86Opcode, dst: u32, lhs: u32, rhs: u32) -> MachineInstr {
        MachineInstr::new(
            opcode as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Reg(rhs),
            ],
            false,
        )
    }

    /// Emit a binary operation with immediate.
    pub fn emit_binary_imm(&self, opcode: X86Opcode, dst: u32, lhs: u32, imm: i64) -> MachineInstr {
        MachineInstr::new(
            opcode as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(lhs),
                MachineOperand::Imm(imm),
            ],
            false,
        )
    }

    /// Emit a unary operation.
    pub fn emit_unary(&self, opcode: X86Opcode, dst: u32, src: u32) -> MachineInstr {
        MachineInstr::new(
            opcode as u32,
            vec![MachineOperand::Reg(dst), MachineOperand::Reg(src)],
            false,
        )
    }

    /// Emit a comparison.
    pub fn emit_cmp(&self, lhs: u32, rhs: u32) -> MachineInstr {
        MachineInstr::new(
            X86Opcode::CMP as u32,
            vec![MachineOperand::Reg(lhs), MachineOperand::Reg(rhs)],
            false,
        )
    }

    /// Emit a RET instruction.
    pub fn emit_ret(&self) -> MachineInstr {
        MachineInstr::new(X86Opcode::RET as u32, Vec::new(), false)
    }

    /// Emit a CALL instruction.
    pub fn emit_call(&self, target: &str) -> MachineInstr {
        MachineInstr::new(
            X86Opcode::CALL as u32,
            vec![MachineOperand::Label(target.to_string())],
            false,
        )
    }

    /// Emit a JMP instruction.
    pub fn emit_jmp(&self, target: &str) -> MachineInstr {
        MachineInstr::new(
            X86Opcode::JMP as u32,
            vec![MachineOperand::Label(target.to_string())],
            false,
        )
    }

    /// Emit a conditional jump.
    pub fn emit_jcc(&self, cc: X86CondCode, target: &str) -> MachineInstr {
        let opcode = match cc {
            X86CondCode::E => X86Opcode::JE,
            X86CondCode::NE => X86Opcode::JNE,
            X86CondCode::L => X86Opcode::JL,
            X86CondCode::G => X86Opcode::JG,
            X86CondCode::LE => X86Opcode::JLE,
            X86CondCode::GE => X86Opcode::JGE,
            X86CondCode::B => X86Opcode::JB,
            X86CondCode::A => X86Opcode::JA,
            X86CondCode::BE => X86Opcode::JBE,
            X86CondCode::AE => X86Opcode::JAE,
            _ => X86Opcode::JE,
        };

        MachineInstr::new(
            opcode as u32,
            vec![MachineOperand::Label(target.to_string())],
            false,
        )
    }

    /// Emit a SETcc instruction.
    pub fn emit_setcc(&self, cc: X86CondCode, dst: u32) -> MachineInstr {
        let opcode = match cc {
            X86CondCode::E => X86Opcode::SETE,
            X86CondCode::NE => X86Opcode::SETNE,
            X86CondCode::L => X86Opcode::SETL,
            X86CondCode::G => X86Opcode::SETG,
            X86CondCode::LE => X86Opcode::SETLE,
            X86CondCode::GE => X86Opcode::SETGE,
            X86CondCode::B => X86Opcode::SETB,
            X86CondCode::A => X86Opcode::SETA,
            X86CondCode::BE => X86Opcode::SETBE,
            X86CondCode::AE => X86Opcode::SETAE,
            _ => X86Opcode::SETE,
        };

        MachineInstr::new(opcode as u32, vec![MachineOperand::Reg(dst)], false)
    }

    /// Emit an LEA instruction.
    pub fn emit_lea(&self, dst: u32, addr_mode: &X86AddressMode) -> MachineInstr {
        let base = addr_mode.base_reg.unwrap_or(0);
        let index = addr_mode.index_reg.unwrap_or(0);
        let scale = addr_mode.scale as i64;
        let disp = addr_mode.displacement;

        MachineInstr::new(
            X86Opcode::LEA as u32,
            vec![
                MachineOperand::Reg(dst),
                MachineOperand::Reg(base),
                MachineOperand::Reg(index),
                MachineOperand::Imm(scale),
                MachineOperand::Imm(disp),
            ],
            false,
        )
    }

    /// Consume the emitter and return the MachineFunction.
    pub fn finish(self) -> MachineFunction {
        self.mf
    }
}

// ============================================================================
// 10. Complete Pipeline Entry Point
// ============================================================================

/// Run the complete X86 SelectionDAG pipeline:
/// 1. Build DAG from IR
/// 2. Run DAG combines
/// 3. Legalize DAG
/// 4. Select instructions
/// 5. Emit machine instructions
pub fn run_x86_dag_pipeline(
    subtarget: &X86Subtarget,
    func_name: &str,
    build_fn: impl FnOnce(&mut X86DAGBuilder),
) -> MachineFunction {
    let calling_conv = X86CallingConvention::default();
    let mut builder = X86DAGBuilder::new(subtarget.clone(), calling_conv.clone());

    // Step 1: Build DAG
    build_fn(&mut builder);

    let mut x86_dag = builder.finish();

    // Step 2: Run DAG combines
    {
        let mut combiner = X86DAGCombine::new(subtarget.clone());
        combiner.combine(&mut x86_dag);
    }

    // Step 3: Legalize
    {
        let mut legalizer = X86DAGLegalize::new(subtarget.clone());
        legalizer.legalize(&mut x86_dag);
    }

    // Step 4-5: ISel + Emit
    let mut emitter = X86InstrEmitter::new(subtarget.clone(), func_name);
    emitter.emit(x86_dag);
    emitter.finish()
}

/// Run on 32-bit X86.
pub fn run_x86_dag_pipeline_32bit(
    subtarget: &X86Subtarget,
    func_name: &str,
    build_fn: impl FnOnce(&mut X86DAGBuilder),
) -> MachineFunction {
    let calling_conv = X86CallingConvention::default();
    let mut builder = X86DAGBuilder::new_32bit(subtarget.clone(), calling_conv.clone());

    build_fn(&mut builder);

    let mut x86_dag = builder.finish();

    {
        let mut combiner = X86DAGCombine::new(subtarget.clone());
        combiner.combine(&mut x86_dag);
    }

    {
        let mut legalizer = X86DAGLegalize::new_32bit(subtarget.clone());
        legalizer.legalize(&mut x86_dag);
    }

    let mut emitter = X86InstrEmitter::new_32bit(subtarget.clone(), func_name);
    emitter.emit(x86_dag);
    emitter.finish()
}

// ============================================================================
// 10.5. X86 Complex Pattern Matcher
// ============================================================================

/// Complex pattern matcher for X86 DAG-to-DAG ISel.
///
/// Handles complex addressing mode recognition, LEA formation,
/// and instruction folding patterns that require multi-node pattern
/// matching (e.g., `(add (shl x, 2), y)` → `lea (y, x, 4)`).
pub struct X86ComplexPatternMatcher {
    /// Current addressing mode being built
    pub addr_mode: X86AddressMode,
    /// Whether the pattern was successfully matched
    pub matched: bool,
    /// The resulting SDValue from the pattern match
    pub result: Option<SDValue>,
    /// Accumulated displacement
    pub displacement: i64,
    /// Recognized base register node_id
    pub base_node_id: Option<usize>,
    /// Recognized index register node_id
    pub index_node_id: Option<usize>,
    /// Recognized scale factor
    pub scale: u8,
}

impl X86ComplexPatternMatcher {
    /// Create a new complex pattern matcher.
    pub fn new() -> Self {
        Self {
            addr_mode: X86AddressMode::default(),
            matched: false,
            result: None,
            displacement: 0,
            base_node_id: None,
            index_node_id: None,
            scale: 1,
        }
    }

    /// Try to match a DAG subtree as an X86 addressing mode.
    ///
    /// Patterns matched:
    /// - `(FrameIndex)` → `[frame + 0]`
    /// - `(add FrameIndex, C)` → `[frame + C]`
    /// - `(add x, y)` → `[x + y]`
    /// - `(shl x, C)` where C ∈ {1,2,3} → `x * 2^C`
    /// - `(add (shl x, C), y)` → `[y + x*2^C]` → LEA
    /// - `(add x, (shl y, C))` → `[x + y*2^C]` → LEA
    /// - `GlobalAddress` → `[RIP + offset]`
    pub fn match_addressing_mode(&mut self, dag: &X86SelectionDAG, node_id: usize) -> bool {
        let node = match dag.dag.get_node(node_id) {
            Some(n) => n.clone(),
            None => return false,
        };

        match node.opcode {
            SDOpcode::FrameIndex => {
                self.base_node_id = Some(node_id);
                self.addr_mode = X86AddressMode {
                    base_reg: Some(5), // RBP
                    displacement: 0,
                    is_frame_relative: true,
                    ..Default::default()
                };
                self.matched = true;
                true
            }
            SDOpcode::GlobalAddress => {
                self.addr_mode = X86AddressMode::new_rip_relative(0);
                self.matched = true;
                true
            }
            SDOpcode::Add => self.match_add_pattern(dag, &node),
            SDOpcode::Shl => self.match_shl_pattern(dag, &node),
            SDOpcode::Constant => {
                // Absolute address
                if let Some(val) = self.get_constant_val(dag, node_id) {
                    self.addr_mode = X86AddressMode::new_absolute(val);
                    self.matched = true;
                    return true;
                }
                false
            }
            _ => false,
        }
    }

    /// Match `(add base, offset)` or `(add (shl idx, C), base)`.
    fn match_add_pattern(&mut self, dag: &X86SelectionDAG, node: &SDNode) -> bool {
        if node.operands.len() < 2 {
            return false;
        }

        let op0 = node.operands[0];
        let op1 = node.operands[1];

        // Try to match op0 as a scale*index and op1 as base+displacement
        if self.try_match_scale_index(dag, op0) {
            if self.try_match_base_disp(dag, op1) {
                self.build_address_mode();
                self.matched = true;
                return true;
            }
        }

        // Try reversed: op1 as scale*index, op0 as base
        if self.try_match_scale_index(dag, op1) {
            if self.try_match_base_disp(dag, op0) {
                self.build_address_mode();
                self.matched = true;
                return true;
            }
        }

        // Try both as base+offset
        if self.try_match_base_disp(dag, op0) {
            if let Some(disp) = self.get_constant_val(dag, op1.node_id) {
                self.displacement += disp;
                self.build_address_mode();
                self.matched = true;
                return true;
            }
        }

        if self.try_match_base_disp(dag, op1) {
            if let Some(disp) = self.get_constant_val(dag, op0.node_id) {
                self.displacement += disp;
                self.build_address_mode();
                self.matched = true;
                return true;
            }
        }

        false
    }

    /// Try to match `(shl x, C)` as a scaled index.
    fn match_shl_pattern(&mut self, dag: &X86SelectionDAG, node: &SDNode) -> bool {
        if node.operands.len() < 2 {
            return false;
        }

        let idx = node.operands[0];
        let amount = node.operands[1];

        if let Some(shift_amt) = self.get_constant_val(dag, amount.node_id) {
            match shift_amt {
                0 => {
                    self.index_node_id = Some(idx.node_id);
                    self.scale = 1;
                }
                1 => {
                    self.index_node_id = Some(idx.node_id);
                    self.scale = 2;
                }
                2 => {
                    self.index_node_id = Some(idx.node_id);
                    self.scale = 4;
                }
                3 => {
                    self.index_node_id = Some(idx.node_id);
                    self.scale = 8;
                }
                _ => return false, // scale factor not representable
            }
            return true;
        }

        false
    }

    /// Try to recognize an operand as a scaled index.
    fn try_match_scale_index(&mut self, dag: &X86SelectionDAG, val: SDValue) -> bool {
        let node = match dag.dag.get_node(val.node_id) {
            Some(n) => n,
            None => return false,
        };

        if node.opcode == SDOpcode::Shl {
            return self.match_shl_pattern(dag, node);
        }

        // Direct register → index with scale 1
        if node.opcode == SDOpcode::Register || node.opcode == SDOpcode::CopyFromReg {
            self.index_node_id = Some(val.node_id);
            self.scale = 1;
            return true;
        }

        false
    }

    /// Try to recognize an operand as a base plus displacement.
    fn try_match_base_disp(&mut self, dag: &X86SelectionDAG, val: SDValue) -> bool {
        let node = match dag.dag.get_node(val.node_id) {
            Some(n) => n,
            None => return false,
        };

        match node.opcode {
            SDOpcode::FrameIndex => {
                if self.base_node_id.is_none() {
                    self.base_node_id = Some(val.node_id);
                    self.addr_mode.is_frame_relative = true;
                    return true;
                }
                false
            }
            SDOpcode::Register | SDOpcode::CopyFromReg => {
                if self.base_node_id.is_none() {
                    self.base_node_id = Some(val.node_id);
                    return true;
                }
                false
            }
            SDOpcode::Add => {
                // Nested add: extract base + offset
                if node.operands.len() >= 2 {
                    let inner_op0 = node.operands[0];
                    let inner_op1 = node.operands[1];

                    if let Some(disp) = self.get_constant_val(dag, inner_op1.node_id) {
                        self.displacement += disp;
                        return self.try_match_base_disp(dag, inner_op0);
                    }
                    if let Some(disp) = self.get_constant_val(dag, inner_op0.node_id) {
                        self.displacement += disp;
                        return self.try_match_base_disp(dag, inner_op1);
                    }
                }
                false
            }
            _ => false,
        }
    }

    /// Build the final X86AddressMode from accumulated state.
    fn build_address_mode(&mut self) {
        self.addr_mode = X86AddressMode {
            base_reg: self.base_node_id.map(|_| 0u32), // Will be resolved by ISel
            index_reg: self.index_node_id.map(|_| 0u32),
            scale: self.scale,
            displacement: self.displacement,
            is_rip_relative: self.addr_mode.is_rip_relative,
            is_frame_relative: self.addr_mode.is_frame_relative,
            ..Default::default()
        };
    }

    /// Get a constant value from a DAG node.
    fn get_constant_val(&self, dag: &X86SelectionDAG, node_id: usize) -> Option<i64> {
        let node = dag.dag.get_node(node_id)?;
        match node.opcode {
            SDOpcode::Constant | SDOpcode::TargetConstant => {
                dag.get_node_info(node_id)
                    .and_then(|n| n.target_constant)
                    .or_else(|| {
                        // Try the constant pool
                        dag.dag
                            .constant_pool
                            .iter()
                            .find(|(_, sv)| sv.node_id == node_id)
                            .map(|((val, _), _)| *val as i64)
                    })
            }
            _ => None,
        }
    }

    /// Reset the matcher for another pattern.
    pub fn reset(&mut self) {
        self.addr_mode = X86AddressMode::default();
        self.matched = false;
        self.result = None;
        self.displacement = 0;
        self.base_node_id = None;
        self.index_node_id = None;
        self.scale = 1;
    }
}

impl Default for X86ComplexPatternMatcher {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// 10.6. X86 Immediate Folding
// ============================================================================

/// Immediate folding support for X86.
///
/// Many X86 instructions can fold an immediate operand:
/// - `ADD r/m, imm` → `ADD r, imm`
/// - `IMUL r, r/m, imm` → `IMUL r, r, imm`
/// - `CMP r/m, imm` → `CMP r, imm`
pub struct X86ImmediateFolder {
    /// Whether folding is enabled
    pub enabled: bool,
    /// Maximum immediate bit width for folding
    pub max_imm_bits: u32,
    /// Whether 64-bit immediates can be folded
    pub allow_imm64: bool,
}

impl X86ImmediateFolder {
    /// Create a new immediate folder.
    pub fn new(is_64bit: bool) -> Self {
        Self {
            enabled: true,
            max_imm_bits: if is_64bit { 64 } else { 32 },
            allow_imm64: is_64bit,
        }
    }

    /// Check if an immediate value can be folded.
    pub fn can_fold_immediate(&self, imm: i64) -> bool {
        if !self.enabled {
            return false;
        }

        let bits_needed = if imm >= 0 {
            64 - imm.leading_zeros()
        } else {
            64 - (!imm).leading_zeros() + 1
        };

        bits_needed <= self.max_imm_bits
    }

    /// Check if an immediate fits in 8 bits (sign-extended).
    pub fn fits_imm8(&self, imm: i64) -> bool {
        imm >= -128 && imm <= 127
    }

    /// Check if an immediate fits in 32 bits (sign-extended).
    pub fn fits_imm32(&self, imm: i64) -> bool {
        imm >= -2_147_483_648 && imm <= 2_147_483_647
    }

    /// Try to fold an immediate into a binary operation.
    /// Returns Some(X86Opcode) if folding is possible.
    pub fn try_fold_imm_binary(&self, opcode: SDOpcode, imm_val: i64) -> Option<X86Opcode> {
        if !self.can_fold_immediate(imm_val) {
            return None;
        }

        match opcode {
            SDOpcode::Add => Some(X86Opcode::ADD),
            SDOpcode::Sub => Some(X86Opcode::SUB),
            SDOpcode::And => Some(X86Opcode::AND),
            SDOpcode::Or => Some(X86Opcode::OR),
            SDOpcode::Xor => Some(X86Opcode::XOR),
            SDOpcode::Mul => Some(X86Opcode::IMUL),
            _ => None,
        }
    }

    /// Try to fold an immediate into a shift operation.
    pub fn try_fold_imm_shift(
        &self,
        opcode: SDOpcode,
        shift_amount: i64,
    ) -> Option<(X86Opcode, i64)> {
        let masked = if self.allow_imm64 {
            shift_amount & 0x3F
        } else {
            shift_amount & 0x1F
        };

        let x86_op = match opcode {
            SDOpcode::Shl => X86Opcode::SHL,
            SDOpcode::Sra => X86Opcode::SAR,
            SDOpcode::Srl => X86Opcode::SHR,
            _ => return None,
        };

        Some((x86_op, masked))
    }

    /// Fold a CMP with immediate.
    pub fn try_fold_cmp_imm(&self, imm_val: i64) -> Option<X86Opcode> {
        if self.can_fold_immediate(imm_val) {
            Some(X86Opcode::CMP)
        } else {
            None
        }
    }
}

impl Default for X86ImmediateFolder {
    fn default() -> Self {
        Self::new(true)
    }
}

// ============================================================================
// 10.7. X86 Table-Driven ISel Support
// ============================================================================

/// An instruction selection pattern entry.
///
/// Designed to be compatible with auto-generated patterns from
/// TableGen (X86GenDAGISel.inc). Each entry describes a DAG
/// pattern that maps to an X86 instruction.
#[derive(Debug, Clone)]
pub struct X86ISelPattern {
    /// The SDNode opcode this pattern matches (root of pattern)
    pub sd_opcode: SDOpcode,
    /// The X86 instruction opcode to emit
    pub x86_opcode: X86Opcode,
    /// Number of operands expected
    pub num_operands: u32,
    /// Pattern name for debugging
    pub name: String,
    /// Whether this pattern requires a specific CPU feature
    pub feature: Option<String>,
    /// Whether this pattern produces EFLAGS
    pub sets_flags: bool,
    /// Whether this is a memory fold pattern
    pub is_memory_fold: bool,
    /// Whether this is a 3-address form (AVX)
    pub is_3addr: bool,
    /// Condition code for conditional instructions
    pub condition_code: Option<X86CondCode>,
    /// The addressing mode pattern for memory folds
    pub addr_pattern: Option<AddressingModePattern>,
}

/// A collection of X86 instruction selection patterns.
///
/// Represents the logical content of X86GenDAGISel.inc.
pub struct X86ISelPatternTable {
    /// All known patterns
    pub patterns: Vec<X86ISelPattern>,
    /// Index: SDNode opcode → list of pattern indices
    pub by_opcode: HashMap<SDOpcode, Vec<usize>>,
    /// Index: X86 opcode → list of pattern indices
    pub by_x86_opcode: HashMap<X86Opcode, Vec<usize>>,
}

impl X86ISelPatternTable {
    /// Create and populate the X86 ISel pattern table.
    pub fn new() -> Self {
        let patterns = Self::build_patterns();
        let mut by_opcode: HashMap<SDOpcode, Vec<usize>> = HashMap::new();
        let mut by_x86_opcode: HashMap<X86Opcode, Vec<usize>> = HashMap::new();

        for (i, p) in patterns.iter().enumerate() {
            by_opcode.entry(p.sd_opcode).or_default().push(i);
            by_x86_opcode.entry(p.x86_opcode).or_default().push(i);
        }

        Self {
            patterns,
            by_opcode,
            by_x86_opcode,
        }
    }

    /// Build the complete pattern table.
    fn build_patterns() -> Vec<X86ISelPattern> {
        let mut p = Vec::new();

        // Integer arithmetic → ADD
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Add,
            x86_opcode: X86Opcode::ADD,
            num_operands: 2,
            name: "add_rr".into(),
            feature: None,
            sets_flags: true,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Integer arithmetic → SUB
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Sub,
            x86_opcode: X86Opcode::SUB,
            num_operands: 2,
            name: "sub_rr".into(),
            feature: None,
            sets_flags: true,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Integer multiply → IMUL
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Mul,
            x86_opcode: X86Opcode::IMUL,
            num_operands: 2,
            name: "imul_rr".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Division
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::SDiv,
            x86_opcode: X86Opcode::IDIV,
            num_operands: 2,
            name: "idiv".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::UDiv,
            x86_opcode: X86Opcode::DIV,
            num_operands: 2,
            name: "div".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Bitwise
        for (sd_op, x86_op, name) in &[
            (SDOpcode::And, X86Opcode::AND, "and_rr"),
            (SDOpcode::Or, X86Opcode::OR, "or_rr"),
            (SDOpcode::Xor, X86Opcode::XOR, "xor_rr"),
        ] {
            p.push(X86ISelPattern {
                sd_opcode: *sd_op,
                x86_opcode: *x86_op,
                num_operands: 2,
                name: name.to_string(),
                feature: None,
                sets_flags: true,
                is_memory_fold: true,
                is_3addr: false,
                condition_code: None,
                addr_pattern: None,
            });
        }

        // Shifts
        for (sd_op, x86_op, name) in &[
            (SDOpcode::Shl, X86Opcode::SHL, "shl"),
            (SDOpcode::Sra, X86Opcode::SAR, "sar"),
            (SDOpcode::Srl, X86Opcode::SHR, "shr"),
        ] {
            p.push(X86ISelPattern {
                sd_opcode: *sd_op,
                x86_opcode: *x86_op,
                num_operands: 2,
                name: name.to_string(),
                feature: None,
                sets_flags: true,
                is_memory_fold: false,
                is_3addr: false,
                condition_code: None,
                addr_pattern: None,
            });
        }

        // Load / Store
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Load,
            x86_opcode: X86Opcode::MOV,
            num_operands: 2,
            name: "load".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: Some(AddressingModePattern::BaseDisp),
        });
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Store,
            x86_opcode: X86Opcode::MOV,
            num_operands: 3,
            name: "store".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: Some(AddressingModePattern::BaseDisp),
        });

        // SSE FP arithmetic
        for (sd_op, sse_op, sse2_op, name) in &[
            (SDOpcode::FAdd, X86Opcode::ADDSS, X86Opcode::ADDSD, "fadd"),
            (SDOpcode::FSub, X86Opcode::SUBSS, X86Opcode::SUBSD, "fsub"),
            (SDOpcode::FMul, X86Opcode::MULSS, X86Opcode::MULSD, "fmul"),
            (SDOpcode::FDiv, X86Opcode::DIVSS, X86Opcode::DIVSD, "fdiv"),
        ] {
            p.push(X86ISelPattern {
                sd_opcode: *sd_op,
                x86_opcode: *sse2_op,
                num_operands: 2,
                name: name.to_string(),
                feature: Some("sse2".into()),
                sets_flags: false,
                is_memory_fold: true,
                is_3addr: false,
                condition_code: None,
                addr_pattern: None,
            });
        }

        // SIMD packed arithmetic (SSE)
        for (sd_op, x86_op, name) in &[
            (SDOpcode::FAdd, X86Opcode::ADDPS, "addps"),
            (SDOpcode::FSub, X86Opcode::SUBPS, "subps"),
            (SDOpcode::FMul, X86Opcode::MULPS, "mulps"),
            (SDOpcode::FDiv, X86Opcode::DIVPS, "divps"),
            (SDOpcode::And, X86Opcode::ANDPS, "andps"),
            (SDOpcode::Or, X86Opcode::ORPS, "orps"),
            (SDOpcode::Xor, X86Opcode::XORPS, "xorps"),
        ] {
            p.push(X86ISelPattern {
                sd_opcode: *sd_op,
                x86_opcode: *x86_op,
                num_operands: 2,
                name: name.to_string(),
                feature: Some("sse".into()),
                sets_flags: false,
                is_memory_fold: true,
                is_3addr: false,
                condition_code: None,
                addr_pattern: None,
            });
        }

        // AVX 3-address forms
        for (sd_op, x86_op, name) in &[
            (SDOpcode::FAdd, X86Opcode::VADDPS, "vaddps"),
            (SDOpcode::FSub, X86Opcode::VSUBPS, "vsubps"),
            (SDOpcode::FMul, X86Opcode::VMULPS, "vmulps"),
            (SDOpcode::FDiv, X86Opcode::VDIVPS, "vdivps"),
            (SDOpcode::And, X86Opcode::VANDPS, "vandps"),
            (SDOpcode::Or, X86Opcode::VORPS, "vorps"),
            (SDOpcode::Xor, X86Opcode::VXORPS, "vxorps"),
        ] {
            p.push(X86ISelPattern {
                sd_opcode: *sd_op,
                x86_opcode: *x86_op,
                num_operands: 3,
                name: name.to_string(),
                feature: Some("avx".into()),
                sets_flags: false,
                is_memory_fold: true,
                is_3addr: true,
                condition_code: None,
                addr_pattern: None,
            });
        }

        // Extensions
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::ZExt,
            x86_opcode: X86Opcode::MOVZX,
            num_operands: 1,
            name: "movzx".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::SExt,
            x86_opcode: X86Opcode::MOVSX,
            num_operands: 1,
            name: "movsx".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Conversions
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::SIToFP,
            x86_opcode: X86Opcode::CVTSI2SD,
            num_operands: 1,
            name: "cvtsi2sd".into(),
            feature: Some("sse2".into()),
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::FPToSI,
            x86_opcode: X86Opcode::CVTSD2SI,
            num_operands: 1,
            name: "cvtsd2si".into(),
            feature: Some("sse2".into()),
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Branch / Jump
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Br,
            x86_opcode: X86Opcode::JMP,
            num_operands: 1,
            name: "jmp".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::BrCond,
            x86_opcode: X86Opcode::JE,
            num_operands: 1,
            name: "je".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: Some(X86CondCode::E),
            addr_pattern: None,
        });

        // Return
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Ret,
            x86_opcode: X86Opcode::RET,
            num_operands: 0,
            name: "ret".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Call
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Call,
            x86_opcode: X86Opcode::CALL,
            num_operands: 1,
            name: "call".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        });

        // Select → CMOV
        p.push(X86ISelPattern {
            sd_opcode: SDOpcode::Select,
            x86_opcode: X86Opcode::CMOVE,
            num_operands: 3,
            name: "cmove".into(),
            feature: Some("cmov".into()),
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: Some(X86CondCode::E),
            addr_pattern: None,
        });

        p
    }

    /// Look up patterns matching a given SDNode opcode.
    pub fn lookup(&self, sd_opcode: SDOpcode) -> &[usize] {
        self.by_opcode
            .get(&sd_opcode)
            .map(|v| v.as_slice())
            .unwrap_or(&[])
    }

    /// Look up patterns producing a given X86 opcode.
    pub fn lookup_by_x86(&self, x86_opcode: X86Opcode) -> &[usize] {
        self.by_x86_opcode
            .get(&x86_opcode)
            .map(|v| v.as_slice())
            .unwrap_or(&[])
    }

    /// Get the total number of patterns.
    pub fn len(&self) -> usize {
        self.patterns.len()
    }

    /// Check if the table is empty.
    pub fn is_empty(&self) -> bool {
        self.patterns.is_empty()
    }
}

impl Default for X86ISelPatternTable {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// 10.8. X86 ABI Lowering Detail
// ============================================================================

/// X86 ABI argument layout helper.
///
/// Describes how function arguments are assigned to registers
/// or stack slots according to the X86-64 System V ABI.
pub struct X86ABIArgLayout {
    /// Registers used for integer/pointer arguments (in order)
    pub int_regs: Vec<u32>,
    /// Registers used for FP/SSE arguments (in order)
    pub sse_regs: Vec<u32>,
    /// Number of arguments passed in registers
    pub num_int_reg_args: u32,
    /// Number of FP arguments passed in registers
    pub num_sse_reg_args: u32,
    /// Stack argument offset (bytes from RSP at call)
    pub stack_arg_offset: u32,
    /// Total stack space needed for arguments
    pub stack_arg_size: u32,
    /// Return value register(s)
    pub ret_regs: Vec<u32>,
}

impl X86ABIArgLayout {
    /// Create for X86-64 System V ABI.
    pub fn x86_64_sysv() -> Self {
        Self {
            int_regs: vec![5, 4, 1, 2, 8, 9], // RDI, RSI, RDX, RCX, R8, R9
            sse_regs: (0..8).collect(),       // XMM0-XMM7
            num_int_reg_args: 6,
            num_sse_reg_args: 8,
            stack_arg_offset: 8, // after return address
            stack_arg_size: 0,
            ret_regs: vec![0, 1], // RAX, RDX
        }
    }

    /// Create for X86-64 Microsoft x64 ABI.
    pub fn x86_64_win64() -> Self {
        Self {
            int_regs: vec![1, 2, 8, 9], // RCX, RDX, R8, R9
            sse_regs: (0..4).collect(), // XMM0-XMM3
            num_int_reg_args: 4,
            num_sse_reg_args: 4,
            stack_arg_offset: 32, // shadow space + return address
            stack_arg_size: 0,
            ret_regs: vec![0],
        }
    }

    /// Create for 32-bit X86 cdecl ABI.
    pub fn x86_32_cdecl() -> Self {
        Self {
            int_regs: Vec::new(), // all stack-passed
            sse_regs: Vec::new(),
            num_int_reg_args: 0,
            num_sse_reg_args: 0,
            stack_arg_offset: 4, // after return address
            stack_arg_size: 0,
            ret_regs: vec![0, 1], // EAX, EDX
        }
    }

    /// Get the integer register for argument index i (if any).
    pub fn get_int_arg_reg(&self, i: u32) -> Option<u32> {
        self.int_regs.get(i as usize).copied()
    }

    /// Get the SSE register for argument index i (if any).
    pub fn get_sse_arg_reg(&self, i: u32) -> Option<u32> {
        self.sse_regs.get(i as usize).copied()
    }

    /// Compute stack offset for the N-th stack argument.
    pub fn stack_offset_for_arg(&self, n: u32) -> u32 {
        self.stack_arg_offset + n * 8
    }
}

impl Default for X86ABIArgLayout {
    fn default() -> Self {
        Self::x86_64_sysv()
    }
}

// ============================================================================
// 10.9. X86 SelectionDAG Utilities
// ============================================================================

/// Utility functions for working with X86 SelectionDAGs.
pub struct X86DAGUtils;

impl X86DAGUtils {
    /// Check if a type is legal on X86.
    pub fn is_type_legal(ty: &Type, is_64bit: bool) -> bool {
        match &ty.kind {
            crate::types::TypeKind::Integer { bits } => match bits {
                8 | 16 | 32 => true,
                64 => is_64bit,
                _ => false,
            },
            crate::types::TypeKind::Float => true,
            crate::types::TypeKind::Double => true,
            crate::types::TypeKind::Pointer { .. } => true,
            _ => false,
        }
    }

    /// Get the register class for a type on X86.
    pub fn get_reg_class_for_type(ty: &Type, is_64bit: bool) -> X86RegClass {
        match &ty.kind {
            crate::types::TypeKind::Integer { bits } => match bits {
                8 => X86RegClass::Gpr8,
                16 => X86RegClass::Gpr16,
                32 => X86RegClass::Gpr32,
                64 if is_64bit => X86RegClass::Gpr64,
                _ => X86RegClass::Gpr32,
            },
            crate::types::TypeKind::Float | crate::types::TypeKind::Double => X86RegClass::Xmm,
            crate::types::TypeKind::Pointer { .. } => {
                if is_64bit {
                    X86RegClass::Gpr64
                } else {
                    X86RegClass::Gpr32
                }
            }
            _ => X86RegClass::Gpr32,
        }
    }

    /// Get the size in bytes for a type.
    pub fn type_size_bytes(ty: &Type) -> u32 {
        match &ty.kind {
            crate::types::TypeKind::Integer { bits } => (*bits + 7) / 8,
            crate::types::TypeKind::Float => 4,
            crate::types::TypeKind::Double => 8,
            crate::types::TypeKind::Pointer { .. } => 8,
            _ => 4,
        }
    }
}

/// X86 register classes for SelectionDAG.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86RegClass {
    Gpr8,
    Gpr16,
    Gpr32,
    Gpr64,
    Xmm,
    Ymm,
    Zmm,
    Mask,
}

impl X86RegClass {
    /// Get the size in bits of this register class.
    pub fn size_bits(&self) -> u32 {
        match self {
            X86RegClass::Gpr8 => 8,
            X86RegClass::Gpr16 => 16,
            X86RegClass::Gpr32 => 32,
            X86RegClass::Gpr64 => 64,
            X86RegClass::Xmm => 128,
            X86RegClass::Ymm => 256,
            X86RegClass::Zmm => 512,
            X86RegClass::Mask => 64,
        }
    }

    /// Get the name of this register class.
    pub fn name(&self) -> &'static str {
        match self {
            X86RegClass::Gpr8 => "GR8",
            X86RegClass::Gpr16 => "GR16",
            X86RegClass::Gpr32 => "GR32",
            X86RegClass::Gpr64 => "GR64",
            X86RegClass::Xmm => "VR128",
            X86RegClass::Ymm => "VR256",
            X86RegClass::Zmm => "VR512",
            X86RegClass::Mask => "MASK",
        }
    }
}

// ============================================================================
// 11. Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    // ---- Helper Functions ----

    fn make_subtarget() -> X86Subtarget {
        X86Subtarget::new("x86-64", "generic")
    }

    fn make_x86_dag() -> X86SelectionDAG {
        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        X86SelectionDAG::new(subtarget, cc)
    }

    fn make_builder() -> X86DAGBuilder {
        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        X86DAGBuilder::new(subtarget, cc)
    }

    fn make_combiner() -> X86DAGCombine {
        X86DAGCombine::new(make_subtarget())
    }

    fn make_legalizer() -> X86DAGLegalize {
        X86DAGLegalize::new(make_subtarget())
    }

    fn make_isel() -> X86DAGToDAGISel {
        X86DAGToDAGISel::new(make_subtarget())
    }

    fn make_emitter() -> X86InstrEmitter {
        X86InstrEmitter::new(make_subtarget(), "test_func")
    }

    // ---- X86ISD Tests ----

    #[test]
    fn test_x86isd_as_str() {
        assert_eq!(X86ISD::Cmp.as_str(), "X86ISD::Cmp");
        assert_eq!(X86ISD::Test.as_str(), "X86ISD::Test");
        assert_eq!(X86ISD::FCmp.as_str(), "X86ISD::FCmp");
        assert_eq!(X86ISD::SetCC.as_str(), "X86ISD::SetCC");
        assert_eq!(X86ISD::CMov.as_str(), "X86ISD::CMov");
        assert_eq!(X86ISD::Call.as_str(), "X86ISD::Call");
        assert_eq!(X86ISD::Ret.as_str(), "X86ISD::Ret");
        assert_eq!(X86ISD::TailCall.as_str(), "X86ISD::TailCall");
        assert_eq!(X86ISD::Fmadd.as_str(), "X86ISD::Fmadd");
        assert_eq!(X86ISD::Gather.as_str(), "X86ISD::Gather");
    }

    #[test]
    fn test_x86isd_is_comparison() {
        assert!(X86ISD::Cmp.is_comparison());
        assert!(X86ISD::Test.is_comparison());
        assert!(X86ISD::FCmp.is_comparison());
        assert!(!X86ISD::Call.is_comparison());
        assert!(!X86ISD::SetCC.is_comparison());
    }

    #[test]
    fn test_x86isd_sets_flags() {
        assert!(X86ISD::Cmp.sets_flags());
        assert!(X86ISD::Test.sets_flags());
        assert!(X86ISD::FCmp.sets_flags());
        assert!(X86ISD::AddCarry.sets_flags());
        assert!(X86ISD::SubBorrow.sets_flags());
        assert!(!X86ISD::Call.sets_flags());
    }

    #[test]
    fn test_x86isd_to_x86_opcode() {
        assert_eq!(X86ISD::Cmp.to_x86_opcode(), Some(X86Opcode::CMP));
        assert_eq!(X86ISD::Test.to_x86_opcode(), Some(X86Opcode::TEST));
        assert_eq!(X86ISD::Shld.to_x86_opcode(), Some(X86Opcode::SHLD));
        assert_eq!(X86ISD::Shrd.to_x86_opcode(), Some(X86Opcode::SHRD));
        assert_eq!(X86ISD::AddCarry.to_x86_opcode(), Some(X86Opcode::ADC));
        assert_eq!(X86ISD::SubBorrow.to_x86_opcode(), Some(X86Opcode::SBB));
    }

    // ---- X86CondCode Tests ----

    #[test]
    fn test_cond_code_as_str() {
        assert_eq!(X86CondCode::E.as_str(), "e");
        assert_eq!(X86CondCode::NE.as_str(), "ne");
        assert_eq!(X86CondCode::L.as_str(), "l");
        assert_eq!(X86CondCode::G.as_str(), "g");
        assert_eq!(X86CondCode::B.as_str(), "b");
        assert_eq!(X86CondCode::A.as_str(), "a");
    }

    #[test]
    fn test_cond_code_complement() {
        assert_eq!(X86CondCode::E.complement(), X86CondCode::NE);
        assert_eq!(X86CondCode::NE.complement(), X86CondCode::E);
        assert_eq!(X86CondCode::L.complement(), X86CondCode::GE);
        assert_eq!(X86CondCode::G.complement(), X86CondCode::LE);
        assert_eq!(X86CondCode::B.complement(), X86CondCode::AE);
        assert_eq!(X86CondCode::A.complement(), X86CondCode::BE);
    }

    #[test]
    fn test_cond_code_swap_operands() {
        assert_eq!(X86CondCode::B.swap_operands(), X86CondCode::A);
        assert_eq!(X86CondCode::A.swap_operands(), X86CondCode::B);
        assert_eq!(X86CondCode::L.swap_operands(), X86CondCode::G);
        assert_eq!(X86CondCode::G.swap_operands(), X86CondCode::L);
        assert_eq!(X86CondCode::E.swap_operands(), X86CondCode::E); // symmetric
    }

    #[test]
    fn test_cond_code_from_icmp_unsigned() {
        assert_eq!(X86CondCode::from_unsigned_icmp(0), X86CondCode::E);
        assert_eq!(X86CondCode::from_unsigned_icmp(1), X86CondCode::NE);
        assert_eq!(X86CondCode::from_unsigned_icmp(2), X86CondCode::A); // ugt
        assert_eq!(X86CondCode::from_unsigned_icmp(5), X86CondCode::B); // ult
    }

    #[test]
    fn test_cond_code_from_icmp_signed() {
        assert_eq!(X86CondCode::from_signed_icmp(0), X86CondCode::E);
        assert_eq!(X86CondCode::from_signed_icmp(2), X86CondCode::G); // sgt
        assert_eq!(X86CondCode::from_signed_icmp(5), X86CondCode::L); // slt
    }

    // ---- X86AddressMode Tests ----

    #[test]
    fn test_address_mode_base_disp() {
        let am = X86AddressMode::new_base_disp(5, -8);
        assert!(am.has_base());
        assert!(!am.has_index());
        assert_eq!(am.displacement, -8);
        assert!(am.fits_disp8());
        assert!(am.fits_disp32());
    }

    #[test]
    fn test_address_mode_base_index_scale() {
        let am = X86AddressMode::new_base_index_scale(5, 2, 4, 0);
        assert!(am.has_base());
        assert!(am.has_index());
        assert_eq!(am.scale, 4);
        assert_eq!(am.classify(), AddressingModePattern::BaseIndexScale);
    }

    #[test]
    fn test_address_mode_rip_relative() {
        let am = X86AddressMode::new_rip_relative(42);
        assert!(am.is_rip_relative);
        assert_eq!(am.classify(), AddressingModePattern::RIPRelative);
    }

    #[test]
    fn test_address_mode_absolute() {
        let am = X86AddressMode::new_absolute(0x1000);
        assert!(!am.has_base());
        assert!(!am.has_index());
        assert_eq!(am.classify(), AddressingModePattern::Absolute);
    }

    #[test]
    fn test_address_mode_classify() {
        assert_eq!(
            X86AddressMode::new_base_disp(5, 0).classify(),
            AddressingModePattern::BaseOnly
        );
        assert_eq!(
            X86AddressMode::new_base_disp(5, 16).classify(),
            AddressingModePattern::BaseDisp
        );
        assert_eq!(
            X86AddressMode::new_base_index_scale(5, 2, 4, 0).classify(),
            AddressingModePattern::BaseIndexScale
        );
        assert_eq!(
            X86AddressMode::new_base_index_scale(5, 2, 4, 32).classify(),
            AddressingModePattern::BaseIndexScaleDisp
        );
    }

    #[test]
    fn test_address_mode_fits_disp8() {
        assert!(X86AddressMode::new_base_disp(5, 0).fits_disp8());
        assert!(X86AddressMode::new_base_disp(5, 127).fits_disp8());
        assert!(X86AddressMode::new_base_disp(5, -128).fits_disp8());
        assert!(!X86AddressMode::new_base_disp(5, 128).fits_disp8());
        assert!(!X86AddressMode::new_base_disp(5, -129).fits_disp8());
    }

    #[test]
    fn test_address_mode_hash_key() {
        let am1 = X86AddressMode::new_base_disp(5, 8);
        let am2 = X86AddressMode::new_base_disp(5, 8);
        assert_eq!(am1.hash_key(), am2.hash_key());

        let am3 = X86AddressMode::new_base_disp(5, 16);
        assert_ne!(am1.hash_key(), am3.hash_key());
    }

    // ---- X86SelectionDAG Tests ----

    #[test]
    fn test_x86_dag_creation() {
        let dag = make_x86_dag();
        assert!(dag.is_64bit);
        assert!(!dag.is_32bit);
        assert_eq!(dag.next_vreg, 0);
        assert_eq!(dag.next_frame_index, 0);
    }

    #[test]
    fn test_x86_dag_32bit() {
        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        let dag = X86SelectionDAG::new_32bit(subtarget, cc);
        assert!(!dag.is_64bit);
        assert!(dag.is_32bit);
    }

    #[test]
    fn test_x86_dag_pointer_type() {
        let dag = make_x86_dag();
        let ptr_ty = dag.pointer_type();
        assert!(matches!(
            ptr_ty.kind,
            crate::types::TypeKind::Pointer { .. }
        ));
    }

    #[test]
    fn test_x86_dag_int_reg_width() {
        let dag = make_x86_dag();
        assert_eq!(dag.int_reg_width(), 64);

        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        let dag32 = X86SelectionDAG::new_32bit(subtarget, cc);
        assert_eq!(dag32.int_reg_width(), 32);
    }

    #[test]
    fn test_x86_dag_vreg() {
        let mut dag = make_x86_dag();
        let vreg1 = dag.get_vreg(Type::integer(32));
        let vreg2 = dag.get_vreg(Type::integer(64));
        assert_ne!(vreg1.node_id, vreg2.node_id);
    }

    #[test]
    fn test_x86_dag_frame_index() {
        let mut dag = make_x86_dag();
        let fi1 = dag.get_frame_index(Type::pointer(0));
        let fi2 = dag.get_frame_index(Type::pointer(0));
        assert_ne!(fi1.node_id, fi2.node_id);
    }

    #[test]
    fn test_x86_dag_get_target_node() {
        let mut dag = make_x86_dag();
        let node = dag.get_target_node(X86ISD::LeaAddr, vec![Type::integer(64)], Vec::new());
        assert!(dag.is_x86_opcode(node.node_id, X86ISD::LeaAddr));
        assert!(!dag.is_x86_opcode(node.node_id, X86ISD::Call));
    }

    #[test]
    fn test_x86_dag_get_cmp() {
        let mut dag = make_x86_dag();
        let constant = dag.dag.get_constant(42u64, Type::integer(32));
        let vreg = dag.get_vreg(Type::integer(32));
        let cmp = dag.get_x86_cmp(vreg, constant, X86CondCode::E);
        assert!(dag.is_x86_opcode(cmp.node_id, X86ISD::Cmp));

        let info = dag.get_node_info(cmp.node_id).unwrap();
        assert_eq!(info.condition_code, Some(X86CondCode::E));
    }

    #[test]
    fn test_x86_dag_get_setcc() {
        let mut dag = make_x86_dag();
        let vreg = dag.get_vreg(Type::integer(32));
        let flag = dag.get_x86_cmp(vreg, vreg, X86CondCode::NE);
        let setcc = dag.get_setcc(X86CondCode::NE, flag, Type::integer(8));
        assert!(dag.is_x86_opcode(setcc.node_id, X86ISD::SetCC));
    }

    #[test]
    fn test_x86_dag_get_cmov() {
        let mut dag = make_x86_dag();
        let vreg = dag.get_vreg(Type::integer(32));
        let flag = dag.get_x86_cmp(vreg, vreg, X86CondCode::G);
        let cmov = dag.get_cmov(X86CondCode::G, flag, vreg, vreg, Type::integer(32));
        assert!(dag.is_x86_opcode(cmov.node_id, X86ISD::CMov));
    }

    #[test]
    fn test_x86_dag_get_call() {
        let mut dag = make_x86_dag();
        let chain = dag.dag.entry_token;
        let callee = dag.dag.get_constant(0u64, Type::pointer(0));
        let (val, call_chain) = dag.get_x86_call(chain, callee, Vec::new(), Type::integer(32));
        assert_ne!(val.node_id, 0);
        assert_ne!(call_chain.node_id, 0);
    }

    #[test]
    fn test_x86_dag_get_ret() {
        let mut dag = make_x86_dag();
        let chain = dag.dag.entry_token;
        let ret = dag.get_x86_ret(chain, None);
        assert!(dag.is_x86_opcode(ret.node_id, X86ISD::Ret));
    }

    #[test]
    fn test_x86_dag_copy_to_from_reg() {
        let mut dag = make_x86_dag();
        let chain = dag.dag.entry_token;
        let val = dag.get_vreg(Type::integer(32));

        let ctr = dag.get_copy_to_reg(chain, val, 0); // RAX
        assert_ne!(ctr.node_id, chain.node_id);

        let (cfr_val, cfr_chain) = dag.get_copy_from_reg(ctr, 0, Type::integer(32));
        assert_ne!(cfr_val.node_id, 0);
    }

    // ---- X86DAGBuilder Tests ----

    #[test]
    fn test_builder_creation() {
        let builder = make_builder();
        assert!(builder.x86_dag.is_64bit);
    }

    #[test]
    fn test_builder_32bit_creation() {
        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        let builder = X86DAGBuilder::new_32bit(subtarget, cc);
        assert!(!builder.x86_dag.is_64bit);
    }

    #[test]
    fn test_builder_lower_add() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let result = builder.lower_add(a, b);
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_sub() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let result = builder.lower_sub(a, b);
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_mul() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let result = builder.lower_mul(a, b);
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_sdiv() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let result = builder.lower_sdiv(a, b);
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_udiv() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let result = builder.lower_udiv(a, b);
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_and_or_xor() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));

        let and_r = builder.lower_and(a, b);
        let or_r = builder.lower_or(a, b);
        let xor_r = builder.lower_xor(a, b);

        assert_ne!(and_r.node_id, 0);
        assert_ne!(or_r.node_id, 0);
        assert_ne!(xor_r.node_id, 0);
    }

    #[test]
    fn test_builder_lower_shifts() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));

        let shl = builder.lower_shl(a, b);
        let sra = builder.lower_sra(a, b);
        let srl = builder.lower_srl(a, b);

        assert_ne!(shl.node_id, 0);
        assert_ne!(sra.node_id, 0);
        assert_ne!(srl.node_id, 0);
    }

    #[test]
    fn test_builder_lower_icmp() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));

        let eq = builder.lower_icmp(a, b, 0, false); // eq
        assert!(builder.x86_dag.is_x86_opcode(eq.node_id, X86ISD::Cmp));

        let slt = builder.lower_icmp(a, b, 5, true); // slt
        assert!(builder.x86_dag.is_x86_opcode(slt.node_id, X86ISD::Cmp));
    }

    #[test]
    fn test_builder_lower_fadd_fsub_fmul_fdiv() {
        let mut builder = make_builder();
        let a = builder.x86_dag.get_vreg(Type::double_precision());
        let b = builder.x86_dag.get_vreg(Type::double_precision());

        let fadd = builder.lower_fadd(a, b);
        let fsub = builder.lower_fsub(a, b);
        let fmul = builder.lower_fmul(a, b);
        let fdiv = builder.lower_fdiv(a, b);

        assert_ne!(fadd.node_id, 0);
        assert_ne!(fsub.node_id, 0);
        assert_ne!(fmul.node_id, 0);
        assert_ne!(fdiv.node_id, 0);
    }

    #[test]
    fn test_builder_lower_zext_sext_trunc() {
        let mut builder = make_builder();
        let val = builder.x86_dag.get_vreg(Type::integer(32));

        let zext = builder.lower_zext(val, Type::integer(64));
        let sext = builder.lower_sext(val, Type::integer(64));
        let trunc = builder.lower_trunc(val, Type::integer(16));

        assert_ne!(zext.node_id, 0);
        assert_ne!(sext.node_id, 0);
        assert_ne!(trunc.node_id, 0);
    }

    #[test]
    fn test_builder_lower_sitofp_fptosi() {
        let mut builder = make_builder();
        let ival = builder.x86_dag.get_vreg(Type::integer(32));
        let fval = builder.x86_dag.get_vreg(Type::float_precision());

        let sitofp = builder.lower_sitofp(ival, Type::float_precision());
        let fptosi = builder.lower_fptosi(fval, Type::integer(32));

        assert_ne!(sitofp.node_id, 0);
        assert_ne!(fptosi.node_id, 0);
    }

    #[test]
    fn test_builder_lower_select() {
        let mut builder = make_builder();
        let cond = builder.x86_dag.get_vreg(Type::integer(1));
        let tval = builder.x86_dag.get_vreg(Type::integer(32));
        let fval = builder.x86_dag.get_vreg(Type::integer(32));

        let result = builder.lower_select(cond, tval, fval, Type::integer(32));
        assert_ne!(result.node_id, 0);
    }

    #[test]
    fn test_builder_lower_br() {
        let mut builder = make_builder();
        let dest = builder.x86_dag.get_vreg(Type::label());
        let br = builder.lower_br(dest);
        assert_ne!(br.node_id, 0);
    }

    #[test]
    fn test_builder_lower_brcond() {
        let mut builder = make_builder();
        let cond = builder.x86_dag.get_vreg(Type::integer(1));
        let tdest = builder.x86_dag.get_vreg(Type::label());
        let fdest = builder.x86_dag.get_vreg(Type::label());

        let br = builder.lower_brcond(cond, tdest, fdest);
        assert_ne!(br.node_id, 0);
    }

    #[test]
    fn test_builder_lower_ret() {
        let mut builder = make_builder();
        let ret = builder.lower_ret(None);
        assert!(builder.x86_dag.is_x86_opcode(ret.node_id, X86ISD::Ret));
    }

    #[test]
    fn test_builder_lower_call() {
        let mut builder = make_builder();
        let callee = builder.x86_dag.get_vreg(Type::pointer(0));
        let (result, chain) = builder.lower_call(callee, &[], Type::integer(32), false);
        assert_ne!(chain.node_id, 0);
    }

    #[test]
    fn test_builder_lower_tail_call() {
        let mut builder = make_builder();
        let callee = builder.x86_dag.get_vreg(Type::pointer(0));
        let (result, chain) = builder.lower_call(callee, &[], Type::integer(32), true);
        assert_ne!(chain.node_id, 0);
    }

    #[test]
    fn test_builder_lower_alloca() {
        let mut builder = make_builder();
        let fi = builder.lower_alloca(16, 16, 100);
        assert_ne!(fi.node_id, 0);
    }

    #[test]
    fn test_builder_lower_load_store() {
        let mut builder = make_builder();
        let ptr = builder.x86_dag.get_vreg(Type::pointer(0));
        let (val, chain) = builder.lower_load(ptr, Type::integer(32));
        assert_ne!(val.node_id, 0);
        assert_ne!(chain.node_id, 0);
    }

    #[test]
    fn test_builder_lower_fsqrt_fabs_fneg() {
        let mut builder = make_builder();
        let val = builder.x86_dag.get_vreg(Type::double_precision());

        let sqrt = builder.lower_fsqrt(val);
        let fabs = builder.lower_fabs(val);
        let fneg = builder.lower_fneg(val);

        assert_ne!(sqrt.node_id, 0);
        assert_ne!(fabs.node_id, 0);
        assert_ne!(fneg.node_id, 0);
    }

    #[test]
    fn test_builder_lower_build_vector() {
        let mut builder = make_builder();
        let e0 = builder.x86_dag.get_vreg(Type::integer(32));
        let e1 = builder.x86_dag.get_vreg(Type::integer(32));
        let e2 = builder.x86_dag.get_vreg(Type::integer(32));
        let e3 = builder.x86_dag.get_vreg(Type::integer(32));

        let vec = builder.lower_build_vector(
            &[e0, e1, e2, e3],
            Type::fixed_vector(4, 0), // 4 × i32
        );
        assert_ne!(vec.node_id, 0);
    }

    #[test]
    fn test_builder_lower_extract_insert_element() {
        let mut builder = make_builder();
        let vec = builder.x86_dag.get_vreg(Type::fixed_vector(4, 0));
        let idx = builder.x86_dag.get_vreg(Type::integer(32));
        let elt = builder.x86_dag.get_vreg(Type::integer(32));

        let extract = builder.lower_extract_element(vec, idx, Type::integer(32));
        let insert = builder.lower_insert_element(vec, elt, idx, Type::fixed_vector(4, 0));

        assert_ne!(extract.node_id, 0);
        assert_ne!(insert.node_id, 0);
    }

    #[test]
    fn test_builder_value_map() {
        let mut builder = make_builder();
        let val = builder.x86_dag.get_vreg(Type::integer(32));
        builder.set_value(42, val);
        assert_eq!(builder.get_value(42), Some(val));
        assert_eq!(builder.get_value(99), None);
    }

    #[test]
    fn test_builder_chain_management() {
        let mut builder = make_builder();
        let chain = builder.get_chain();
        assert_ne!(chain.node_id, 0);
    }

    #[test]
    fn test_builder_recognize_addressing_mode_frame_index() {
        let mut builder = make_builder();
        let fi = builder.x86_dag.get_frame_index(Type::pointer(0));
        let am = builder.recognize_addressing_mode(fi);
        assert!(am.is_frame_relative);
    }

    #[test]
    fn test_builder_get_constant() {
        let mut builder = make_builder();
        let c = builder.get_constant(42u64, Type::integer(32));
        assert_ne!(c.node_id, 0);

        let cfp = builder.get_constant_fp(f64::to_bits(3.14), Type::double_precision());
        assert_ne!(cfp.node_id, 0);
    }

    // ---- X86DAGCombine Tests ----

    #[test]
    fn test_combiner_creation() {
        let combiner = make_combiner();
        assert_eq!(combiner.x86_num_combined, 0);
        assert!(!combiner.modified);
    }

    #[test]
    fn test_combine_add_identity() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, zero);

        let mut combiner = make_combiner();
        combiner.combine_add_identity(&mut dag, add.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_sub_identity() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let sub = dag.dag.get_binary_op(SDOpcode::Sub, Type::integer(32), a, zero);

        let mut combiner = make_combiner();
        combiner.combine_sub_identity(&mut dag, sub.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_mul_identity() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let one = dag.dag.get_constant(1u64, Type::integer(32));
        let mul = dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), a, one);

        let mut combiner = make_combiner();
        combiner.combine_mul_identity(&mut dag, mul.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_and_identity() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let all_ones = dag.dag.get_constant((-1i64) as u64, Type::integer(32));
        let and = dag.dag.get_binary_op(SDOpcode::And, Type::integer(32), a, all_ones);

        let mut combiner = make_combiner();
        combiner.combine_and_identity(&mut dag, and.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_or_identity() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let or_op = dag.dag.get_binary_op(SDOpcode::Or, Type::integer(32), a, zero);

        let mut combiner = make_combiner();
        combiner.combine_or_identity(&mut dag, or_op.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_xor_zero() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let xor_op = dag.dag.get_binary_op(SDOpcode::Xor, Type::integer(32), a, zero);

        let mut combiner = make_combiner();
        combiner.combine_xor_zero(&mut dag, xor_op.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_mul_to_lea() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));

        for &c in &[3, 5, 9] {
            let const_val = dag.dag.get_constant(c, Type::integer(32));
            let mul = dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), a, const_val);

            let mut combiner = make_combiner();
            combiner.combine_mul_to_lea(&mut dag, mul.node_id);
            assert!(combiner.modified);
        }
    }

    #[test]
    fn test_combine_shift_amount_zero() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));

        for opcode in &[SDOpcode::Shl, SDOpcode::Sra, SDOpcode::Srl] {
            let shift = dag.dag.get_binary_op(*opcode, a, zero);
            let mut combiner = make_combiner();
            combiner.combine_shift_amount(&mut dag, shift.node_id);
            assert!(combiner.modified);
        }
    }

    #[test]
    fn test_combine_ext_trunc() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let trunc = dag
            .dag
            .get_binary_op(SDOpcode::Trunc, a, SDValue::new(0, 0));
        // Manually create trunc → zext pattern
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Trunc,
            vec![Type::integer(16)],
        )
        .with_operands(vec![a]);
        let trunc_id = dag.dag.add_node(node);

        let zext_node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::ZExt,
            vec![Type::integer(32)],
        )
        .with_operands(vec![SDValue::new(trunc_id, 0)]);
        let zext_id = dag.dag.add_node(zext_node);

        let mut combiner = make_combiner();
        combiner.combine_ext_trunc(&mut dag, zext_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_is_constant_zero() {
        let combiner = make_combiner();
        let mut dag = make_x86_dag();
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let one = dag.dag.get_constant(1u64, Type::integer(32));

        // Explicitly set target_constant in node_info
        dag.node_info.insert(
            zero.node_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(0),
            },
        );
        dag.node_info.insert(
            one.node_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(1),
            },
        );

        assert!(combiner.is_constant_zero(&dag, zero));
        assert!(!combiner.is_constant_zero(&dag, one));
    }

    #[test]
    fn test_combine_full_run() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let _add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, zero);

        let mut combiner = make_combiner();
        combiner.combine(&mut dag);
        assert!(combiner.x86_num_combined > 0 || combiner.modified);
    }

    // ---- X86DAGLegalize Tests ----

    #[test]
    fn test_legalizer_creation() {
        let legalizer = make_legalizer();
        assert_eq!(legalizer.type_legalizer.target_pointer_size, 64);
    }

    #[test]
    fn test_legalizer_32bit() {
        let subtarget = make_subtarget();
        let legalizer = X86DAGLegalize::new_32bit(subtarget);
        assert_eq!(legalizer.type_legalizer.target_pointer_size, 32);
    }

    #[test]
    fn test_legalize_x86_dag() {
        let mut dag = make_x86_dag();
        let mut legalizer = make_legalizer();
        legalizer.legalize(&mut dag);
        // Should not panic
    }

    #[test]
    fn test_type_size_bits() {
        assert_eq!(X86DAGLegalize::type_size_bits(&Type::integer(8)), 8);
        assert_eq!(X86DAGLegalize::type_size_bits(&Type::integer(32)), 32);
        assert_eq!(X86DAGLegalize::type_size_bits(&Type::integer(64)), 64);
        assert_eq!(X86DAGLegalize::type_size_bits(&Type::float_precision()), 32);
        assert_eq!(
            X86DAGLegalize::type_size_bits(&Type::double_precision()),
            64
        );
    }

    // ---- X86DAGToDAGISel Tests ----

    #[test]
    fn test_isel_creation() {
        let isel = make_isel();
        assert!(isel.is_64bit);
        assert_eq!(isel.num_selected, 0);
    }

    #[test]
    fn test_isel_32bit() {
        let isel = X86DAGToDAGISel::new_32bit(make_subtarget());
        assert!(!isel.is_64bit);
    }

    #[test]
    fn test_isel_select_add() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, b);

        let result = isel.select_add(add.node_id);
        assert!(result.is_some());
        let instrs = result.unwrap();
        assert!(!instrs.is_empty());
    }

    #[test]
    fn test_isel_select_add_imm() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let imm = dag.dag.get_constant(5u64, Type::integer(32));
        let add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, imm);

        let result = isel.select_add(add.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_sub() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let sub = dag.dag.get_binary_op(SDOpcode::Sub, Type::integer(32), a, b);

        let result = isel.select_sub(sub.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_mul() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let mul = dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), a, b);

        let result = isel.select_mul(mul.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_sdiv() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let sdiv = dag.dag.get_binary_op(SDOpcode::SDiv, Type::integer(32), a, b);

        let result = isel.select_sdiv(sdiv.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_udiv() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let udiv = dag.dag.get_binary_op(SDOpcode::UDiv, Type::integer(32), a, b);

        let result = isel.select_udiv(udiv.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_bitwise_ops() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));

        for opcode in &[SDOpcode::And, SDOpcode::Or, SDOpcode::Xor] {
            let op = dag.dag.get_binary_op(*opcode, a, b);
            let result = match opcode {
                SDOpcode::And => isel.select_and(op.node_id),
                SDOpcode::Or => isel.select_or(op.node_id),
                SDOpcode::Xor => isel.select_xor(op.node_id),
                _ => None,
            };
            assert!(result.is_some(), "Failed for opcode: {:?}", opcode);
        }
    }

    #[test]
    fn test_isel_select_shifts() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let amount = dag.dag.get_constant(3u64, Type::integer(32));

        let shl = isel.select_shl(dag.dag.get_binary_op(SDOpcode::Shl, Type::integer(32), a, amount).node_id);
        let sra = isel.select_sra(dag.dag.get_binary_op(SDOpcode::Sra, Type::integer(32), a, amount).node_id);
        let srl = isel.select_srl(dag.dag.get_binary_op(SDOpcode::Srl, Type::integer(32), a, amount).node_id);

        assert!(shl.is_some());
        assert!(sra.is_some());
        assert!(srl.is_some());
    }

    #[test]
    fn test_isel_select_zext_sext() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::integer(32));

        let node_zext = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::ZExt,
            vec![Type::integer(64)],
        )
        .with_operands(vec![val]);
        let zext_id = dag.dag.add_node(node_zext);

        let node_sext = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::SExt,
            vec![Type::integer(64)],
        )
        .with_operands(vec![val]);
        let sext_id = dag.dag.add_node(node_sext);

        assert!(isel.select_zext(zext_id).is_some());
        assert!(isel.select_sext(sext_id).is_some());
    }

    #[test]
    fn test_isel_select_trunc() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::integer(32));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Trunc,
            vec![Type::integer(16)],
        )
        .with_operands(vec![val]);
        let trunc_id = dag.dag.add_node(node);

        assert!(isel.select_trunc(trunc_id).is_some());
    }

    #[test]
    fn test_isel_select_fadd() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::double_precision());
        let b = dag.get_vreg(Type::double_precision());
        let fadd = dag.dag.get_binary_op(SDOpcode::FAdd, Type::double_precision(), a, b);

        let result = isel.select_fadd(fadd.node_id);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_fsqrt() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::double_precision());

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::FSqrt,
            vec![Type::double_precision()],
        )
        .with_operands(vec![val]);
        let sqrt_id = dag.dag.add_node(node);

        assert!(isel.select_fsqrt(sqrt_id).is_some());
    }

    #[test]
    fn test_isel_select_fabs() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::double_precision());

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::FAbs,
            vec![Type::double_precision()],
        )
        .with_operands(vec![val]);
        let fabs_id = dag.dag.add_node(node);

        assert!(isel.select_fabs(fabs_id).is_some());
    }

    #[test]
    fn test_isel_select_fneg() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::double_precision());

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::FNeg,
            vec![Type::double_precision()],
        )
        .with_operands(vec![val]);
        let fneg_id = dag.dag.add_node(node);

        assert!(isel.select_fneg(fneg_id).is_some());
    }

    #[test]
    fn test_isel_select_sitofp() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::integer(32));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::SIToFP,
            vec![Type::double_precision()],
        )
        .with_operands(vec![val]);
        let sitofp_id = dag.dag.add_node(node);

        assert!(isel.select_sitofp(sitofp_id).is_some());
    }

    #[test]
    fn test_isel_select_fptosi() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let val = dag.get_vreg(Type::double_precision());

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::FPToSI,
            vec![Type::integer(32)],
        )
        .with_operands(vec![val]);
        let fptosi_id = dag.dag.add_node(node);

        assert!(isel.select_fptosi(fptosi_id).is_some());
    }

    #[test]
    fn test_isel_select_br() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let dest = dag.get_vreg(Type::label());

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Br,
            vec![Type::token()],
        )
        .with_operands(vec![dag.dag.entry_token, dest]);
        let br_id = dag.dag.add_node(node);

        assert!(isel.select_br(br_id).is_some());
    }

    #[test]
    fn test_isel_select_ret() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Ret,
            vec![Type::token()],
        )
        .with_operands(vec![dag.dag.entry_token]);
        let ret_id = dag.dag.add_node(node);

        assert!(isel.select_ret(ret_id).is_some());
    }

    #[test]
    fn test_isel_select_call() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let callee = dag.get_vreg(Type::pointer(0));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Call,
            vec![Type::integer(32), Type::token()],
        )
        .with_operands(vec![dag.dag.entry_token, callee]);
        let call_id = dag.dag.add_node(node);

        assert!(isel.select_call(call_id).is_some());
    }

    #[test]
    fn test_isel_select_setcc() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let cmp = dag.get_x86_cmp(a, b, X86CondCode::E);

        assert!(isel.select_setcc(cmp.node_id).is_some());
    }

    #[test]
    fn test_isel_select_frameindex() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let fi = dag.get_frame_index(Type::pointer(0));

        assert!(isel.select_frameindex(fi.node_id).is_some());
    }

    #[test]
    fn test_isel_select_constant() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let c = dag.dag.get_constant(42u64, Type::integer(32));
        dag.node_info.insert(
            c.node_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(42),
            },
        );

        assert!(isel.select_constant(c.node_id).is_some());
    }

    #[test]
    fn test_isel_select_build_vector() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let e0 = dag.get_vreg(Type::integer(32));
        let e1 = dag.get_vreg(Type::integer(32));
        let e2 = dag.get_vreg(Type::integer(32));
        let e3 = dag.get_vreg(Type::integer(32));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::BuildVector,
            vec![Type::fixed_vector(4, 0)],
        )
        .with_operands(vec![e0, e1, e2, e3]);
        let bv_id = dag.dag.add_node(node);

        assert!(isel.select_build_vector(bv_id).is_some());
    }

    #[test]
    fn test_isel_select_extract_element() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let vec = dag.get_vreg(Type::fixed_vector(4, 0));
        let idx = dag.dag.get_constant(2u64, Type::integer(32));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::ExtractElement,
            vec![Type::integer(32)],
        )
        .with_operands(vec![vec, idx]);
        let ee_id = dag.dag.add_node(node);

        assert!(isel.select_extract_element(ee_id).is_some());
    }

    #[test]
    fn test_isel_select_insert_element() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let vec = dag.get_vreg(Type::fixed_vector(4, 0));
        let elt = dag.get_vreg(Type::integer(32));
        let idx = dag.dag.get_constant(1u64, Type::integer(32));

        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::InsertElement,
            vec![Type::fixed_vector(4, 0)],
        )
        .with_operands(vec![vec, elt, idx]);
        let ie_id = dag.dag.add_node(node);

        assert!(isel.select_insert_element(ie_id).is_some());
    }

    #[test]
    fn test_isel_cond_code_to_jcc() {
        let isel = make_isel();
        assert_eq!(isel.cond_code_to_jcc(X86CondCode::E), X86Opcode::JE);
        assert_eq!(isel.cond_code_to_jcc(X86CondCode::NE), X86Opcode::JNE);
        assert_eq!(isel.cond_code_to_jcc(X86CondCode::L), X86Opcode::JL);
        assert_eq!(isel.cond_code_to_jcc(X86CondCode::G), X86Opcode::JG);
    }

    #[test]
    fn test_isel_cond_code_to_setcc() {
        let isel = make_isel();
        assert_eq!(isel.cond_code_to_setcc(X86CondCode::E), X86Opcode::SETE);
        assert_eq!(isel.cond_code_to_setcc(X86CondCode::NE), X86Opcode::SETNE);
    }

    #[test]
    fn test_isel_cond_code_to_cmov() {
        let isel = make_isel();
        assert_eq!(isel.cond_code_to_cmov(X86CondCode::E), X86Opcode::CMOVE);
        assert_eq!(isel.cond_code_to_cmov(X86CondCode::G), X86Opcode::CMOVG);
    }

    #[test]
    fn test_isel_vreg_management() {
        let mut isel = make_isel();
        let vreg1 = isel.new_vreg();
        let vreg2 = isel.new_vreg();
        assert_ne!(vreg1, vreg2);
        assert!(vreg2 > vreg1);
    }

    #[test]
    fn test_isel_get_immediate() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let c = dag.dag.get_constant(42u64, Type::integer(32));
        dag.node_info.insert(
            c.node_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None,
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: Some(42),
            },
        );

        isel.dag = Some(dag);
        let imm = isel.get_immediate(c);
        assert_eq!(imm, Some(42));
    }

    #[test]
    fn test_isel_select_copy_to_from_reg() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let chain = dag.dag.entry_token;
        let val = dag.get_vreg(Type::integer(32));
        let ctr = dag.get_copy_to_reg(chain, val, 0);

        let (cfr_val, cfr_chain) = dag.get_copy_from_reg(ctr, 0, Type::integer(32));

        isel.dag = Some(dag);
        let ctr_instrs = isel.select_copy_to_reg(ctr.node_id);
        let cfr_instrs = isel.select_copy_from_reg(cfr_val.node_id);

        assert!(ctr_instrs.is_some());
        assert!(cfr_instrs.is_some());
    }

    // ---- X86DAGSchedModel Tests ----

    #[test]
    fn test_sched_model_creation() {
        let model = X86DAGSchedModel::default_x86();
        assert_eq!(model.model_kind, X86SchedModelKind::Zen3);
    }

    #[test]
    fn test_sched_model_latency() {
        let mut model = X86DAGSchedModel::default_x86();
        let lat = model.get_latency(SDOpcode::Add);
        assert!(lat > 0);
    }

    #[test]
    fn test_sched_model_x86_latency() {
        let mut model = X86DAGSchedModel::default_x86();
        let lat = model.get_x86_latency(X86ISD::Cmp);
        assert!(lat > 0);
    }

    #[test]
    fn test_sched_model_critical_path() {
        let mut model = X86DAGSchedModel::default_x86();
        let dag = make_x86_dag();
        let cp = model.compute_critical_path(&dag);
        assert!(cp >= 0);
    }

    #[test]
    fn test_sched_model_uops() {
        let mut model = X86DAGSchedModel::default_x86();
        let uops = model.get_uops(SDOpcode::Add);
        assert!(uops > 0);
    }

    #[test]
    fn test_sched_model_map_sdopcode() {
        let model = X86DAGSchedModel::default_x86();
        assert_eq!(model.map_sdopcode_to_x86(SDOpcode::Add), X86Opcode::ADD);
        assert_eq!(model.map_sdopcode_to_x86(SDOpcode::Sub), X86Opcode::SUB);
        assert_eq!(model.map_sdopcode_to_x86(SDOpcode::Mul), X86Opcode::IMUL);
        assert_eq!(model.map_sdopcode_to_x86(SDOpcode::SDiv), X86Opcode::IDIV);
    }

    // ---- X86InstrEmitter Tests ----

    #[test]
    fn test_emitter_creation() {
        let emitter = make_emitter();
        assert_eq!(emitter.mf.name, "test_func");
    }

    #[test]
    fn test_emitter_emit_mov() {
        let emitter = make_emitter();
        let instr = emitter.emit_mov(1, 2);
        assert_eq!(instr.opcode, X86Opcode::MOV as u32);
    }

    #[test]
    fn test_emitter_emit_mov_imm() {
        let emitter = make_emitter();
        let instr = emitter.emit_mov_imm(1, 42);
        assert_eq!(instr.opcode, X86Opcode::MOV as u32);
    }

    #[test]
    fn test_emitter_emit_binary() {
        let emitter = make_emitter();
        let instr = emitter.emit_binary(X86Opcode::ADD, 1, 2, 3);
        assert_eq!(instr.opcode, X86Opcode::ADD as u32);
        assert_eq!(instr.operands.len(), 3);
    }

    #[test]
    fn test_emitter_emit_binary_imm() {
        let emitter = make_emitter();
        let instr = emitter.emit_binary_imm(X86Opcode::ADD, 1, 2, 42);
        assert_eq!(instr.opcode, X86Opcode::ADD as u32);
    }

    #[test]
    fn test_emitter_emit_cmp() {
        let emitter = make_emitter();
        let instr = emitter.emit_cmp(1, 2);
        assert_eq!(instr.opcode, X86Opcode::CMP as u32);
    }

    #[test]
    fn test_emitter_emit_ret() {
        let emitter = make_emitter();
        let instr = emitter.emit_ret();
        assert_eq!(instr.opcode, X86Opcode::RET as u32);
    }

    #[test]
    fn test_emitter_emit_call() {
        let emitter = make_emitter();
        let instr = emitter.emit_call("printf");
        assert_eq!(instr.opcode, X86Opcode::CALL as u32);
    }

    #[test]
    fn test_emitter_emit_jmp() {
        let emitter = make_emitter();
        let instr = emitter.emit_jmp(".L1");
        assert_eq!(instr.opcode, X86Opcode::JMP as u32);
    }

    #[test]
    fn test_emitter_emit_jcc() {
        let emitter = make_emitter();
        let instr = emitter.emit_jcc(X86CondCode::E, ".L1");
        assert_eq!(instr.opcode, X86Opcode::JE as u32);
    }

    #[test]
    fn test_emitter_emit_setcc() {
        let emitter = make_emitter();
        let instr = emitter.emit_setcc(X86CondCode::NE, 1);
        assert_eq!(instr.opcode, X86Opcode::SETNE as u32);
    }

    #[test]
    fn test_emitter_emit_lea() {
        let emitter = make_emitter();
        let am = X86AddressMode::new_base_index_scale(5, 2, 4, 16);
        let instr = emitter.emit_lea(1, &am);
        assert_eq!(instr.opcode, X86Opcode::LEA as u32);
    }

    // ---- Pipeline Tests ----

    #[test]
    fn test_full_pipeline_simple_function() {
        let subtarget = make_subtarget();
        let mf = run_x86_dag_pipeline(&subtarget, "simple_add", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let b = builder.x86_dag.get_vreg(Type::integer(32));
            let sum = builder.lower_add(a, b);
            let _ret = builder.lower_ret(Some(sum));
        });

        assert_eq!(mf.name, "simple_add");
        assert!(!mf.blocks.is_empty());
    }

    #[test]
    fn test_full_pipeline_arithmetic() {
        let subtarget = make_subtarget();
        let mf = run_x86_dag_pipeline(&subtarget, "arith", |builder| {
            let x = builder.x86_dag.get_vreg(Type::integer(32));
            let y = builder.x86_dag.get_vreg(Type::integer(32));
            let sum = builder.lower_add(x, y);
            let diff = builder.lower_sub(sum, x);
            let prod = builder.lower_mul(diff, y);
            let _ret = builder.lower_ret(Some(prod));
        });

        assert_eq!(mf.name, "arith");
    }

    #[test]
    fn test_full_pipeline_32bit() {
        let subtarget = make_subtarget();
        let mf = run_x86_dag_pipeline_32bit(&subtarget, "simple32", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let b = builder.x86_dag.get_vreg(Type::integer(32));
            let sum = builder.lower_add(a, b);
            let _ret = builder.lower_ret(Some(sum));
        });

        assert_eq!(mf.name, "simple32");
    }

    #[test]
    fn test_full_pipeline_with_calls() {
        let subtarget = make_subtarget();
        let mf = run_x86_dag_pipeline(&subtarget, "call_func", |builder| {
            let callee = builder.x86_dag.get_vreg(Type::pointer(0));
            let arg = builder.x86_dag.get_vreg(Type::integer(32));
            let (result, _chain) = builder.lower_call(callee, &[arg], Type::integer(32), false);
            let _ret = builder.lower_ret(Some(result));
        });

        assert_eq!(mf.name, "call_func");
    }

    // ---- Integration Tests ----

    #[test]
    fn test_x86isd_enum_exhaustiveness() {
        // Verify all variants have as_str
        let variants = [
            X86ISD::Cmp,
            X86ISD::Test,
            X86ISD::FCmp,
            X86ISD::SetCC,
            X86ISD::CMov,
            X86ISD::BitTest,
            X86ISD::BitTestAndSet,
            X86ISD::BitTestAndReset,
            X86ISD::BitTestAndComplement,
            X86ISD::Shld,
            X86ISD::Shrd,
            X86ISD::UDivRem,
            X86ISD::SDivRem,
            X86ISD::MulHW,
            X86ISD::UMulH,
        ];
        for v in &variants {
            assert!(!v.as_str().is_empty());
        }
    }

    #[test]
    fn test_cond_code_from_icmp_all_predicates() {
        for pred in 0..6u32 {
            let _unsigned = X86CondCode::from_unsigned_icmp(pred);
            let _signed = X86CondCode::from_signed_icmp(pred);
        }
    }

    #[test]
    fn test_cond_code_from_fcmp_all_predicates() {
        for pred in 0..14u32 {
            let _fcmp = X86CondCode::from_fcmp(pred);
        }
    }

    #[test]
    fn test_builder_full_instruction_set() {
        let subtarget = make_subtarget();
        let cc = X86CallingConvention::default();
        let mut builder = X86DAGBuilder::new(subtarget, cc);

        // Test all builder operations don't panic
        let i32 = Type::integer(32);
        let i64 = Type::integer(64);
        let f64 = Type::double_precision();
        let ptr = Type::pointer(0);

        let a = builder.x86_dag.get_vreg(i32.clone());
        let b = builder.x86_dag.get_vreg(i32.clone());
        let fa = builder.x86_dag.get_vreg(f64.clone());
        let fb = builder.x86_dag.get_vreg(f64.clone());
        let p = builder.x86_dag.get_vreg(ptr.clone());

        // All binary ops
        let _ = builder.lower_add(a, b);
        let _ = builder.lower_sub(a, b);
        let _ = builder.lower_mul(a, b);
        let _ = builder.lower_sdiv(a, b);
        let _ = builder.lower_udiv(a, b);
        let _ = builder.lower_and(a, b);
        let _ = builder.lower_or(a, b);
        let _ = builder.lower_xor(a, b);
        let _ = builder.lower_shl(a, b);
        let _ = builder.lower_sra(a, b);
        let _ = builder.lower_srl(a, b);

        // FP ops
        let _ = builder.lower_fadd(fa, fb);
        let _ = builder.lower_fsub(fa, fb);
        let _ = builder.lower_fmul(fa, fb);
        let _ = builder.lower_fdiv(fa, fb);

        // Comparisons
        let _ = builder.lower_icmp(a, b, 0, false); // eq
        let _ = builder.lower_fcmp(fa, fb, 0); // oeq

        // Extensions
        let _ = builder.lower_zext(a, i64.clone());
        let _ = builder.lower_sext(a, i64.clone());
        let _ = builder.lower_trunc(a, Type::integer(16));

        // Conversions
        let _ = builder.lower_sitofp(a, f64.clone());
        let _ = builder.lower_fptosi(fa, i32.clone());

        // Special
        let _ = builder.lower_fsqrt(fa);
        let _ = builder.lower_fabs(fa);
        let _ = builder.lower_fneg(fa);

        // Control flow
        let _ = builder.lower_br(p);
        let _ = builder.lower_brcond(a, p, p);
        let _ = builder.lower_ret(Some(a));
        let (_, _) = builder.lower_call(p, &[a], i32.clone(), false);
    }

    #[test]
    fn test_isel_all_opcode_selection() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();

        let i32 = Type::integer(32);
        let f64 = Type::double_precision();
        let ptr = Type::pointer(0);

        let a = dag.get_vreg(i32.clone());
        let b = dag.get_vreg(i32.clone());
        let c = dag.get_vreg(f64.clone());
        let d = dag.get_vreg(f64.clone());
        let p = dag.get_vreg(ptr.clone());

        isel.dag = Some(dag);

        // Verify all select methods return Some
        let add = isel
            .dag
            .as_ref()
            .unwrap()
            .dag
            .get_binary_op(SDOpcode::Add, Type::integer(32), a, b);
        assert!(isel.select_add(add.node_id).is_some());

        let sub = isel
            .dag
            .as_ref()
            .unwrap()
            .dag
            .get_binary_op(SDOpcode::Sub, Type::integer(32), a, b);
        assert!(isel.select_sub(sub.node_id).is_some());

        let fadd = isel
            .dag
            .as_ref()
            .unwrap()
            .dag
            .get_binary_op(SDOpcode::FAdd, Type::double_precision(), c, d);
        assert!(isel.select_fadd(fadd.node_id).is_some());
    }

    #[test]
    fn test_pipeline_idempotent() {
        let subtarget = make_subtarget();
        let mf1 = run_x86_dag_pipeline(&subtarget, "idem", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let _ret = builder.lower_ret(Some(a));
        });

        let mf2 = run_x86_dag_pipeline(&subtarget, "idem", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let _ret = builder.lower_ret(Some(a));
        });

        assert_eq!(mf1.name, mf2.name);
    }

    #[test]
    fn test_emitter_finish() {
        let mut emitter = make_emitter();
        let mf = emitter.finish();
        assert_eq!(mf.name, "test_func");
    }

    #[test]
    fn test_x86dag_combine_multiple_iterations() {
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, zero);
        let _add2 = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), add, zero);

        let mut combiner = make_combiner();
        combiner.combine(&mut dag);
        assert!(combiner.x86_num_combined > 0);
    }

    // === Complex Pattern Matcher Tests ===

    #[test]
    fn test_complex_pattern_matcher_new() {
        let matcher = X86ComplexPatternMatcher::new();
        assert!(!matcher.matched);
        assert_eq!(matcher.scale, 1);
        assert_eq!(matcher.displacement, 0);
    }

    #[test]
    fn test_complex_pattern_match_frame_index() {
        let mut matcher = X86ComplexPatternMatcher::new();
        let mut dag = make_x86_dag();
        let fi = dag.get_frame_index(Type::pointer(0));
        let matched = matcher.match_addressing_mode(&dag, fi.node_id);
        assert!(matched);
        assert!(matcher.matched);
        assert!(matcher.addr_mode.is_frame_relative);
    }

    #[test]
    fn test_complex_pattern_reset() {
        let mut matcher = X86ComplexPatternMatcher::new();
        let mut dag = make_x86_dag();
        let fi = dag.get_frame_index(Type::pointer(0));
        matcher.match_addressing_mode(&dag, fi.node_id);
        assert!(matcher.matched);
        matcher.reset();
        assert!(!matcher.matched);
        assert_eq!(matcher.scale, 1);
        assert_eq!(matcher.displacement, 0);
    }

    #[test]
    fn test_complex_pattern_default() {
        let matcher = X86ComplexPatternMatcher::default();
        assert!(!matcher.matched);
    }

    // === Immediate Folder Tests ===

    #[test]
    fn test_immediate_folder_new_64bit() {
        let folder = X86ImmediateFolder::new(true);
        assert!(folder.enabled);
        assert!(folder.allow_imm64);
        assert_eq!(folder.max_imm_bits, 64);
    }

    #[test]
    fn test_immediate_folder_new_32bit() {
        let folder = X86ImmediateFolder::new(false);
        assert!(!folder.allow_imm64);
        assert_eq!(folder.max_imm_bits, 32);
    }

    #[test]
    fn test_immediate_folder_fits_imm8() {
        let folder = X86ImmediateFolder::default();
        assert!(folder.fits_imm8(0));
        assert!(folder.fits_imm8(127));
        assert!(folder.fits_imm8(-128));
        assert!(!folder.fits_imm8(128));
        assert!(!folder.fits_imm8(-129));
    }

    #[test]
    fn test_immediate_folder_fits_imm32() {
        let folder = X86ImmediateFolder::default();
        assert!(folder.fits_imm32(0));
        assert!(folder.fits_imm32(2147483647));
        assert!(folder.fits_imm32(-2147483648));
        assert!(!folder.fits_imm32(2147483648i64));
        assert!(!folder.fits_imm32(-2147483649i64));
    }

    #[test]
    fn test_immediate_folder_can_fold() {
        let folder = X86ImmediateFolder::new(true);
        assert!(folder.can_fold_immediate(0));
        assert!(folder.can_fold_immediate(42));
        assert!(folder.can_fold_immediate(-1));
    }

    #[test]
    fn test_immediate_folder_try_fold_binary() {
        let folder = X86ImmediateFolder::default();
        assert_eq!(
            folder.try_fold_imm_binary(SDOpcode::Add, 42),
            Some(X86Opcode::ADD)
        );
        assert_eq!(
            folder.try_fold_imm_binary(SDOpcode::Sub, -8),
            Some(X86Opcode::SUB)
        );
        assert_eq!(
            folder.try_fold_imm_binary(SDOpcode::And, 0xFF),
            Some(X86Opcode::AND)
        );
        assert_eq!(
            folder.try_fold_imm_binary(SDOpcode::Mul, 3),
            Some(X86Opcode::IMUL)
        );
        assert_eq!(folder.try_fold_imm_binary(SDOpcode::Load, 0), None);
    }

    #[test]
    fn test_immediate_folder_try_fold_shift() {
        let folder = X86ImmediateFolder::default();
        assert_eq!(
            folder.try_fold_imm_shift(SDOpcode::Shl, 3),
            Some((X86Opcode::SHL, 3))
        );
        assert_eq!(
            folder.try_fold_imm_shift(SDOpcode::Sra, 5),
            Some((X86Opcode::SAR, 5))
        );
        assert_eq!(
            folder.try_fold_imm_shift(SDOpcode::Srl, 7),
            Some((X86Opcode::SHR, 7))
        );
        assert_eq!(folder.try_fold_imm_shift(SDOpcode::Add, 1), None);
    }

    #[test]
    fn test_immediate_folder_try_fold_cmp() {
        let folder = X86ImmediateFolder::default();
        assert_eq!(folder.try_fold_cmp_imm(0), Some(X86Opcode::CMP));
    }

    // === ISel Pattern Table Tests ===

    #[test]
    fn test_isel_pattern_table_creation() {
        let table = X86ISelPatternTable::new();
        assert!(!table.is_empty());
        assert!(table.len() > 0);
    }

    #[test]
    fn test_isel_pattern_table_lookup() {
        let table = X86ISelPatternTable::new();
        let add_patterns = table.lookup(SDOpcode::Add);
        assert!(!add_patterns.is_empty());
    }

    #[test]
    fn test_isel_pattern_table_lookup_by_x86() {
        let table = X86ISelPatternTable::new();
        let add_patterns = table.lookup_by_x86(X86Opcode::ADD);
        assert!(!add_patterns.is_empty());
    }

    #[test]
    fn test_isel_pattern_table_lookup_unknown() {
        let table = X86ISelPatternTable::new();
        let pats = table.lookup(SDOpcode::LibCall);
        assert!(pats.is_empty());
    }

    #[test]
    fn test_isel_pattern_table_default() {
        let table = X86ISelPatternTable::default();
        assert!(!table.is_empty());
    }

    #[test]
    fn test_isel_pattern_has_avx_patterns() {
        let table = X86ISelPatternTable::new();
        let avx_patterns = table.lookup_by_x86(X86Opcode::VADDPS);
        assert!(!avx_patterns.is_empty());
    }

    #[test]
    fn test_isel_pattern_has_sse_patterns() {
        let table = X86ISelPatternTable::new();
        let sse_patterns = table.lookup_by_x86(X86Opcode::ADDPS);
        assert!(!sse_patterns.is_empty());
    }

    // === ABI Arg Layout Tests ===

    #[test]
    fn test_abi_layout_x86_64_sysv() {
        let layout = X86ABIArgLayout::x86_64_sysv();
        assert_eq!(layout.int_regs.len(), 6);
        assert_eq!(layout.sse_regs.len(), 8);
        assert_eq!(layout.get_int_arg_reg(0), Some(5));
        assert_eq!(layout.get_int_arg_reg(1), Some(4));
        assert_eq!(layout.get_int_arg_reg(2), Some(1));
        assert_eq!(layout.get_int_arg_reg(6), None);
    }

    #[test]
    fn test_abi_layout_x86_64_win64() {
        let layout = X86ABIArgLayout::x86_64_win64();
        assert_eq!(layout.int_regs.len(), 4);
        assert_eq!(layout.get_int_arg_reg(0), Some(1));
        assert_eq!(layout.get_int_arg_reg(3), Some(9));
        assert_eq!(layout.get_int_arg_reg(4), None);
    }

    #[test]
    fn test_abi_layout_x86_32_cdecl() {
        let layout = X86ABIArgLayout::x86_32_cdecl();
        assert_eq!(layout.int_regs.len(), 0);
        assert_eq!(layout.get_int_arg_reg(0), None);
    }

    #[test]
    fn test_abi_layout_stack_offset() {
        let layout = X86ABIArgLayout::x86_64_sysv();
        assert_eq!(layout.stack_offset_for_arg(0), 8);
        assert_eq!(layout.stack_offset_for_arg(1), 16);
        assert_eq!(layout.stack_offset_for_arg(2), 24);
    }

    #[test]
    fn test_abi_layout_default() {
        let layout = X86ABIArgLayout::default();
        assert_eq!(layout.int_regs.len(), 6);
    }

    // === DAG Utils Tests ===

    #[test]
    fn test_dag_utils_is_type_legal() {
        assert!(X86DAGUtils::is_type_legal(&Type::integer(8), true));
        assert!(X86DAGUtils::is_type_legal(&Type::integer(32), true));
        assert!(X86DAGUtils::is_type_legal(&Type::integer(64), true));
        assert!(!X86DAGUtils::is_type_legal(&Type::integer(64), false));
        assert!(!X86DAGUtils::is_type_legal(&Type::integer(128), true));
        assert!(X86DAGUtils::is_type_legal(&Type::float_precision(), true));
        assert!(X86DAGUtils::is_type_legal(&Type::double_precision(), true));
    }

    #[test]
    fn test_dag_utils_get_reg_class() {
        assert_eq!(
            X86DAGUtils::get_reg_class_for_type(&Type::integer(8), true),
            X86RegClass::Gpr8
        );
        assert_eq!(
            X86DAGUtils::get_reg_class_for_type(&Type::integer(32), true),
            X86RegClass::Gpr32
        );
        assert_eq!(
            X86DAGUtils::get_reg_class_for_type(&Type::integer(64), true),
            X86RegClass::Gpr64
        );
        assert_eq!(
            X86DAGUtils::get_reg_class_for_type(&Type::integer(64), false),
            X86RegClass::Gpr32
        );
        assert_eq!(
            X86DAGUtils::get_reg_class_for_type(&Type::float_precision(), true),
            X86RegClass::Xmm
        );
    }

    #[test]
    fn test_dag_utils_type_size_bytes() {
        assert_eq!(X86DAGUtils::type_size_bytes(&Type::integer(8)), 1);
        assert_eq!(X86DAGUtils::type_size_bytes(&Type::integer(32)), 4);
        assert_eq!(X86DAGUtils::type_size_bytes(&Type::integer(64)), 8);
        assert_eq!(X86DAGUtils::type_size_bytes(&Type::float_precision()), 4);
        assert_eq!(X86DAGUtils::type_size_bytes(&Type::double_precision()), 8);
    }

    // === X86RegClass Tests ===

    #[test]
    fn test_reg_class_size_bits() {
        assert_eq!(X86RegClass::Gpr8.size_bits(), 8);
        assert_eq!(X86RegClass::Gpr16.size_bits(), 16);
        assert_eq!(X86RegClass::Gpr32.size_bits(), 32);
        assert_eq!(X86RegClass::Gpr64.size_bits(), 64);
        assert_eq!(X86RegClass::Xmm.size_bits(), 128);
        assert_eq!(X86RegClass::Ymm.size_bits(), 256);
        assert_eq!(X86RegClass::Zmm.size_bits(), 512);
        assert_eq!(X86RegClass::Mask.size_bits(), 64);
    }

    #[test]
    fn test_reg_class_name() {
        assert_eq!(X86RegClass::Gpr8.name(), "GR8");
        assert_eq!(X86RegClass::Gpr64.name(), "GR64");
        assert_eq!(X86RegClass::Xmm.name(), "VR128");
        assert_eq!(X86RegClass::Ymm.name(), "VR256");
        assert_eq!(X86RegClass::Zmm.name(), "VR512");
    }

    // === X86ISelPattern Individual Tests ===

    #[test]
    fn test_isel_pattern_individual() {
        let p = X86ISelPattern {
            sd_opcode: SDOpcode::Add,
            x86_opcode: X86Opcode::ADD,
            num_operands: 2,
            name: "test_add".into(),
            feature: None,
            sets_flags: true,
            is_memory_fold: true,
            is_3addr: false,
            condition_code: None,
            addr_pattern: None,
        };
        assert_eq!(p.name, "test_add");
        assert!(p.sets_flags);
        assert!(p.is_memory_fold);
        assert!(!p.is_3addr);
    }

    #[test]
    fn test_isel_pattern_with_condition_code() {
        let p = X86ISelPattern {
            sd_opcode: SDOpcode::BrCond,
            x86_opcode: X86Opcode::JE,
            num_operands: 1,
            name: "je".into(),
            feature: None,
            sets_flags: false,
            is_memory_fold: false,
            is_3addr: false,
            condition_code: Some(X86CondCode::E),
            addr_pattern: None,
        };
        assert_eq!(p.condition_code, Some(X86CondCode::E));
    }

    // === X86-specific ISel Selection Tests ===

    #[test]
    fn test_isel_select_x86_cmp() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let cmp = dag.get_x86_cmp(a, b, X86CondCode::E);
        let info = dag.get_node_info(cmp.node_id).unwrap().clone();
        isel.dag = Some(dag);
        let result = isel.select_x86_cmp(cmp.node_id, &info);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_x86_setcc() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let flag = dag.get_vreg(Type::integer(1));
        let setcc = dag.get_setcc(X86CondCode::NE, flag, Type::integer(8));
        let info = dag.get_node_info(setcc.node_id).unwrap().clone();
        isel.dag = Some(dag);
        let result = isel.select_x86_setcc(setcc.node_id, &info);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_x86_cmov() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let flag = dag.get_vreg(Type::integer(1));
        let tval = dag.get_vreg(Type::integer(32));
        let fval = dag.get_vreg(Type::integer(32));
        let cmov = dag.get_cmov(X86CondCode::G, flag, tval, fval, Type::integer(32));
        let info = dag.get_node_info(cmov.node_id).unwrap().clone();
        isel.dag = Some(dag);
        let result = isel.select_x86_cmov(cmov.node_id, &info);
        assert!(result.is_some());
    }

    #[test]
    fn test_isel_select_x86_shld_shrd() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let node_shld = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Shl,
            vec![Type::integer(32)],
        )
        .with_operands(vec![a, b])
        .with_target_node(true);
        let shld_id = dag.dag.add_node(node_shld);
        dag.node_info.insert(
            shld_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Shl, vec![]),
                x86_opcode: Some(X86ISD::Shld),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(shld_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_shld(shld_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_adc_sbb() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let node_adc = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Add,
            vec![Type::integer(32)],
        )
        .with_operands(vec![a, b])
        .with_target_node(true);
        let adc_id = dag.dag.add_node(node_adc);
        dag.node_info.insert(
            adc_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Add, vec![]),
                x86_opcode: Some(X86ISD::AddCarry),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(adc_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_adc(adc_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_vbroadcast() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let src = dag.get_vreg(Type::float_precision());
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::ScalarToVector,
            vec![Type::fixed_vector(4, 0)],
        )
        .with_operands(vec![src])
        .with_target_node(true);
        let vb_id = dag.dag.add_node(node);
        dag.node_info.insert(
            vb_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::ScalarToVector, vec![]),
                x86_opcode: Some(X86ISD::VBroadcast),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(vb_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_vbroadcast(vb_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_vshuffle() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let src1 = dag.get_vreg(Type::fixed_vector(4, 0));
        let src2 = dag.get_vreg(Type::fixed_vector(4, 0));
        let mask = dag.dag.get_constant(0xE4, Type::integer(8));
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::VectorShuffle,
            vec![Type::fixed_vector(4, 0)],
        )
        .with_operands(vec![src1, src2, mask])
        .with_target_node(true);
        let vs_id = dag.dag.add_node(node);
        dag.node_info.insert(
            vs_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::VectorShuffle, vec![]),
                x86_opcode: Some(X86ISD::VShuffle),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(vs_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_vshuffle(vs_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_fma() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let a = dag.get_vreg(Type::double_precision());
        let b = dag.get_vreg(Type::double_precision());
        let c = dag.get_vreg(Type::double_precision());
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::FMA,
            vec![Type::double_precision()],
        )
        .with_operands(vec![a, b, c])
        .with_target_node(true);
        let fma_id = dag.dag.add_node(node);
        dag.node_info.insert(
            fma_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::FMA, vec![]),
                x86_opcode: Some(X86ISD::Fmadd),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(fma_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_fmadd(fma_id, &info).is_some());
        assert!(isel.select_x86_fmsub(fma_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_gather() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let base = dag.get_vreg(Type::pointer(0));
        let index = dag.get_vreg(Type::fixed_vector(4, 0));
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Load,
            vec![Type::fixed_vector(4, 0)],
        )
        .with_operands(vec![dag.dag.entry_token, base, index])
        .with_target_node(true);
        let gather_id = dag.dag.add_node(node);
        dag.node_info.insert(
            gather_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Load, vec![]),
                x86_opcode: Some(X86ISD::Gather),
                condition_code: None,
                addressing_mode: None,
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(gather_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_gather(gather_id, &info).is_some());
    }

    #[test]
    fn test_isel_select_x86_call_ret() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let callee = dag.get_vreg(Type::pointer(0));
        let node_call = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Call,
            vec![Type::integer(32), Type::token()],
        )
        .with_operands(vec![dag.dag.entry_token, callee])
        .with_target_node(true);
        let call_id = dag.dag.add_node(node_call);
        let info_call = X86DAGNode {
            node: SDNode::new(0, SDOpcode::Call, vec![]),
            x86_opcode: Some(X86ISD::Call),
            condition_code: None,
            addressing_mode: None,
            mem_operand: None,
            target_constant: None,
        };
        isel.dag = Some(dag);
        assert!(isel.select_x86_call(call_id, &info_call).is_some());
    }

    #[test]
    fn test_isel_select_x86_lea() {
        let mut isel = make_isel();
        let mut dag = make_x86_dag();
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(),
            dag.dag.all_nodes.len(),
            SDOpcode::Add,
            vec![Type::pointer(0)],
        )
        .with_operands(Vec::new())
        .with_target_node(true);
        let lea_id = dag.dag.add_node(node);
        dag.node_info.insert(
            lea_id,
            X86DAGNode {
                node: SDNode::new(0, SDOpcode::Add, vec![]),
                x86_opcode: Some(X86ISD::LeaAddr),
                condition_code: None,
                addressing_mode: Some(X86AddressMode::new_base_index_scale(5, 2, 4, 16)),
                mem_operand: None,
                target_constant: None,
            },
        );
        let info = dag.get_node_info(lea_id).unwrap().clone();
        isel.dag = Some(dag);
        assert!(isel.select_x86_lea(lea_id, &info).is_some());
    }
}

// ============================================================================
// 12. Extended Tests — X86-specific SelectionDAG pipeline edge cases
// ============================================================================

#[cfg(test)]
mod extended_tests {
    use super::*;

    fn make_dag() -> X86SelectionDAG {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        X86SelectionDAG::new(subtarget, cc)
    }

    fn make_builder() -> X86DAGBuilder {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        X86DAGBuilder::new(subtarget, cc)
    }

    // === Full X86ISD Enum Tests ===

    #[test]
    fn test_x86isd_full_enum_variants() {
        let all = [
            X86ISD::Cmp, X86ISD::Test, X86ISD::FCmp, X86ISD::SetCC, X86ISD::CMov,
            X86ISD::BitTest, X86ISD::BitTestAndSet, X86ISD::BitTestAndReset,
            X86ISD::BitTestAndComplement, X86ISD::Shld, X86ISD::Shrd,
            X86ISD::UDivRem, X86ISD::SDivRem, X86ISD::MulHW, X86ISD::UMulH,
            X86ISD::RepMovs, X86ISD::RepStos, X86ISD::Call, X86ISD::Ret,
            X86ISD::TailCall, X86ISD::FrameAddr, X86ISD::RetAddr,
            X86ISD::LeaAddr, X86ISD::GlobalBaseReg, X86ISD::AddCarry, X86ISD::SubBorrow,
            X86ISD::VBroadcast, X86ISD::VBroadcastLoad, X86ISD::MovdToVec,
            X86ISD::VecExtract, X86ISD::VecInsert, X86ISD::VShuffle,
            X86ISD::Unpckl, X86ISD::Unpckh, X86ISD::HAdd, X86ISD::HSub, X86ISD::AddSub,
            X86ISD::Fmadd, X86ISD::Fmsub, X86ISD::Fnmadd, X86ISD::Fnmsub, X86ISD::Fmaddsub,
            X86ISD::MaskOp, X86ISD::MaskedOp, X86ISD::Gather, X86ISD::Scatter,
            X86ISD::Compress, X86ISD::Expand, X86ISD::EhReturn, X86ISD::TlsAddr,
            X86ISD::Wrapper, X86ISD::WrapperRIP,
        ];
        for v in &all {
            let s = v.as_str();
            assert!(!s.is_empty(), "Missing as_str for {:?}", v);
            let is_cmp = v.is_comparison();
            let sets_f = v.sets_flags();
            let _ = v.to_x86_opcode();
        }
    }

    // === CopyToReg / CopyFromReg Tests ===

    #[test]
    fn test_copy_to_from_reg_chain_preservation() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let val = dag.get_vreg(Type::integer(32));
        let ctr = dag.get_copy_to_reg(chain, val, 5);
        let (cfr_val, cfr_chain) = dag.get_copy_from_reg(ctr, 0, Type::integer(32));
        assert_ne!(cfr_val.node_id, val.node_id);
        assert_ne!(cfr_chain.node_id, chain.node_id);
    }

    // === Load/Store with Addressing Modes ===

    #[test]
    fn test_load_with_addressing_mode() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let ptr = dag.get_vreg(Type::pointer(0));
        let am = X86AddressMode::new_base_disp(5, 16);
        let (val, new_chain) = dag.get_x86_load(chain, ptr, Type::integer(32), am.clone());
        assert_ne!(val.node_id, 0);
        assert_ne!(new_chain.node_id, 0);
        let info = dag.get_node_info(val.node_id).unwrap();
        assert!(info.addressing_mode.is_some());
    }

    #[test]
    fn test_store_with_addressing_mode() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let val = dag.get_vreg(Type::integer(32));
        let ptr = dag.get_vreg(Type::pointer(0));
        let am = X86AddressMode::new_base_index_scale(5, 2, 4, 8);
        let new_chain = dag.get_x86_store(chain, val, ptr, am);
        assert_ne!(new_chain.node_id, 0);
    }

    // === Call Sequence Tests ===

    #[test]
    fn test_call_with_arguments() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let callee = dag.dag.get_constant(0x4000, Type::pointer(0));
        let arg1 = dag.get_vreg(Type::integer(32));
        let arg2 = dag.get_vreg(Type::integer(32));
        let (result, call_chain) = dag.get_x86_call(
            chain, callee,
            vec![arg1, arg2],
            Type::integer(32),
        );
        assert_ne!(result.node_id, 0);
        assert_ne!(call_chain.node_id, 0);
    }

    #[test]
    fn test_call_void_return() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let callee = dag.dag.get_constant(0x4000, Type::pointer(0));
        let (result, call_chain) = dag.get_x86_call(
            chain, callee, Vec::new(),
            Type::void(),
        );
        assert_ne!(call_chain.node_id, 0);
    }

    // === Branch Tests ===

    #[test]
    fn test_branch_with_chain() {
        let mut dag = make_dag();
        let chain = dag.dag.entry_token;
        let dest = dag.get_vreg(Type::label());
        let node = SDNode::new_with_node_id(
            dag.dag.nodes.len(), dag.dag.all_nodes.len(),
            SDOpcode::Br, vec![Type::token()],
        ).with_operands(vec![chain, dest]);
        let br_id = dag.dag.add_node(node);
        dag.dag.set_root(SDValue::new(br_id, 0));
        assert_eq!(dag.dag.root, Some(SDValue::new(br_id, 0)));
    }

    // === Builder Extended Tests ===

    #[test]
    fn test_builder_recognize_multiple_addressing_modes() {
        let mut builder = make_builder();
        let fi = builder.x86_dag.get_frame_index(Type::pointer(0));
        let am = builder.recognize_addressing_mode(fi);
        assert!(am.is_frame_relative);

        let gv = SDValue::new(0, 0);
        // Build a GlobalAddress node
        let ga_node = SDNode::new_with_node_id(
            builder.x86_dag.dag.nodes.len(),
            builder.x86_dag.dag.all_nodes.len(),
            SDOpcode::GlobalAddress,
            vec![Type::pointer(0)],
        );
        let ga_id = builder.x86_dag.dag.add_node(ga_node);
        let am2 = builder.recognize_addressing_mode(SDValue::new(ga_id, 0));
        assert!(am2.is_rip_relative);
    }

    #[test]
    fn test_builder_constant_folding_in_lower() {
        let mut builder = make_builder();
        let c42 = builder.get_constant(42u64, Type::integer(32));
        let c58 = builder.get_constant(58u64, Type::integer(32));
        let sum = builder.lower_add(c42, c58);
        assert_ne!(sum.node_id, 0);
    }

    #[test]
    fn test_builder_get_constant_fp() {
        let mut builder = make_builder();
        let cfp = builder.get_constant_fp(f64::to_bits(3.14159), Type::double_precision());
        assert_ne!(cfp.node_id, 0);
    }

    // === Combiner Extended Tests ===

    #[test]
    fn test_combine_all_identity_patterns() {
        let mut dag = make_dag();
        let x = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let one = dag.dag.get_constant(1u64, Type::integer(32));
        let all_ones = dag.dag.get_constant((-1i64) as u64, Type::integer(32));

        // Set target_constant in node_info for each constant
        for (c, val) in &[
            (zero.node_id, 0i64),
            (one.node_id, 1i64),
            (all_ones.node_id, -1i64),
        ] {
            dag.node_info.insert(*c, X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None, condition_code: None,
                addressing_mode: None, mem_operand: None,
                target_constant: Some(*val),
            });
        }

        let mut combiner = X86DAGCombine::new(X86Subtarget::new("x86-64", "generic"));

        let add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), x, zero);
        combiner.combine_add_identity(&mut dag, add.node_id);
        assert!(combiner.modified);

        let sub = dag.dag.get_binary_op(SDOpcode::Sub, Type::integer(32), x, zero);
        combiner.combine_sub_identity(&mut dag, sub.node_id);
        assert!(combiner.modified);

        let mul = dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), x, one);
        combiner.combine_mul_identity(&mut dag, mul.node_id);
        assert!(combiner.modified);

        let and = dag.dag.get_binary_op(SDOpcode::And, Type::integer(32), x, all_ones);
        combiner.combine_and_identity(&mut dag, and.node_id);
        assert!(combiner.modified);

        let or = dag.dag.get_binary_op(SDOpcode::Or, Type::integer(32), x, zero);
        combiner.combine_or_identity(&mut dag, or.node_id);
        assert!(combiner.modified);

        let xor = dag.dag.get_binary_op(SDOpcode::Xor, Type::integer(32), x, zero);
        combiner.combine_xor_zero(&mut dag, xor.node_id);
        assert!(combiner.modified);
    }

    #[test]
    fn test_combine_shift_all_amounts() {
        let mut dag = make_dag();
        let x = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(8));
        dag.node_info.insert(zero.node_id, X86DAGNode {
            node: SDNode::new(0, SDOpcode::Constant, vec![]),
            x86_opcode: None, condition_code: None,
            addressing_mode: None, mem_operand: None,
            target_constant: Some(0),
        });

        let mut combiner = X86DAGCombine::new(X86Subtarget::new("x86-64", "generic"));

        for &opcode in &[SDOpcode::Shl, SDOpcode::Sra, SDOpcode::Srl] {
            let shift = dag.dag.get_binary_op(opcode, x, zero);
            combiner.combine_shift_amount(&mut dag, shift.node_id);
        }
        assert!(combiner.modified);
    }

    // === Legalizer Extended Tests ===

    #[test]
    fn test_legalizer_vector_widths() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let legalizer = X86DAGLegalize::new(subtarget.clone());
        assert!(!legalizer.type_legalizer.legal_vector_widths.is_empty());
    }

    #[test]
    fn test_legalizer_32bit_config() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let legalizer = X86DAGLegalize::new_32bit(subtarget);
        assert_eq!(legalizer.type_legalizer.target_pointer_size, 32);
        assert_eq!(legalizer.type_legalizer.max_legal_int_size, 32);
    }

    #[test]
    fn test_legalize_empty_dag() {
        let mut dag = make_dag();
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mut legalizer = X86DAGLegalize::new(subtarget);
        legalizer.legalize(&mut dag);
        // Should not panic
    }

    // === ISel Extended Tests ===

    #[test]
    fn test_isel_all_binary_opcode_selections() {
        let mut isel = X86DAGToDAGISel::new(X86Subtarget::new("x86-64", "generic"));
        let mut dag = make_dag();
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let c = dag.get_vreg(Type::double_precision());
        let d = dag.get_vreg(Type::double_precision());

        isel.dag = Some(dag);

        // Verify all select methods return Some for valid inputs
        let add = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, b);
        assert!(isel.select_add(add.node_id).is_some());
        let sub = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::Sub, Type::integer(32), a, b);
        assert!(isel.select_sub(sub.node_id).is_some());
        let mul = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::Mul, Type::integer(32), a, b);
        assert!(isel.select_mul(mul.node_id).is_some());
        let and = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::And, Type::integer(32), a, b);
        assert!(isel.select_and(and.node_id).is_some());
        let or = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::Or, Type::integer(32), a, b);
        assert!(isel.select_or(or.node_id).is_some());
        let xor = isel.dag.as_ref().unwrap().dag.get_binary_op(SDOpcode::Xor, Type::integer(32), a, b);
        assert!(isel.select_xor(xor.node_id).is_some());
    }

    #[test]
    fn test_isel_all_condition_codes() {
        let isel = X86DAGToDAGISel::new(X86Subtarget::new("x86-64", "generic"));
        let all_ccs = [
            X86CondCode::O, X86CondCode::NO, X86CondCode::B, X86CondCode::AE,
            X86CondCode::E, X86CondCode::NE, X86CondCode::BE, X86CondCode::A,
            X86CondCode::S, X86CondCode::NS, X86CondCode::P, X86CondCode::NP,
            X86CondCode::L, X86CondCode::GE, X86CondCode::LE, X86CondCode::G,
        ];

        for &cc in &all_ccs {
            let jcc = isel.cond_code_to_jcc(cc);
            let setcc = isel.cond_code_to_setcc(cc);
            let cmov = isel.cond_code_to_cmov(cc);
            assert!(jcc.as_u32() > 0);
            assert!(setcc.as_u32() > 0);
            assert!(cmov.as_u32() > 0);
        }
    }

    #[test]
    fn test_isel_vreg_allocation() {
        let mut isel = X86DAGToDAGISel::new(X86Subtarget::new("x86-64", "generic"));
        let v1 = isel.new_vreg();
        let v2 = isel.new_vreg();
        let v3 = isel.new_vreg();
        assert!(v1 != v2);
        assert!(v2 != v3);
        assert!(v3 > v2);
        assert!(v2 > v1);
    }

    #[test]
    fn test_isel_get_label() {
        let isel = X86DAGToDAGISel::new(X86Subtarget::new("x86-64", "generic"));
        let label = isel.get_label(SDValue::new(42, 0));
        assert!(label.contains("42"));
    }

    // === Scheduler Extended Tests ===

    #[test]
    fn test_sched_model_all_kinds() {
        let kinds = [
            X86SchedModelKind::SkylakeClient,
            X86SchedModelKind::IceLake,
            X86SchedModelKind::AlderLakePcore,
            X86SchedModelKind::GraniteRapids,
            X86SchedModelKind::Zen3,
            X86SchedModelKind::Zen4,
            X86SchedModelKind::Zen5,
        ];

        for &kind in &kinds {
            let mut model = X86DAGSchedModel::new(kind);
            assert_eq!(model.model_kind, kind);
            let lat = model.get_latency(SDOpcode::Add);
            assert!(lat > 0, "Zero latency for {:?}", kind);
        }
    }

    #[test]
    fn test_sched_model_critical_path_empty() {
        let mut model = X86DAGSchedModel::default_x86();
        let dag = make_dag();
        let cp = model.compute_critical_path(&dag);
        assert!(cp >= 0);
    }

    // === Emitter Extended Tests ===

    #[test]
    fn test_emitter_all_instruction_types() {
        let emitter = X86InstrEmitter::new(X86Subtarget::new("x86-64", "generic"), "test");

        // MOV variants
        assert_eq!(emitter.emit_mov(1, 2).opcode, X86Opcode::MOV as u32);
        assert_eq!(emitter.emit_mov_imm(1, 42).opcode, X86Opcode::MOV as u32);

        // Binary
        assert_eq!(emitter.emit_binary(X86Opcode::ADD, 1, 2, 3).opcode, X86Opcode::ADD as u32);
        assert_eq!(emitter.emit_binary_imm(X86Opcode::SUB, 1, 2, 5).opcode, X86Opcode::SUB as u32);

        // Unary
        assert_eq!(emitter.emit_unary(X86Opcode::NOT, 1, 2).opcode, X86Opcode::NOT as u32);

        // Compare
        assert_eq!(emitter.emit_cmp(1, 2).opcode, X86Opcode::CMP as u32);

        // Flow
        assert_eq!(emitter.emit_ret().opcode, X86Opcode::RET as u32);
        assert_eq!(emitter.emit_call("target").opcode, X86Opcode::CALL as u32);
        assert_eq!(emitter.emit_jmp("target").opcode, X86Opcode::JMP as u32);

        // Conditional
        for &cc in &[X86CondCode::E, X86CondCode::NE, X86CondCode::L, X86CondCode::G,
                       X86CondCode::B, X86CondCode::A, X86CondCode::BE, X86CondCode::AE] {
            let jcc = emitter.emit_jcc(cc, "target");
            assert!(jcc.opcode > 0);
            let setcc = emitter.emit_setcc(cc, 1);
            assert!(setcc.opcode > 0);
        }

        // LEA
        let am = X86AddressMode::new_base_index_scale(5, 2, 4, 16);
        let lea = emitter.emit_lea(1, &am);
        assert_eq!(lea.opcode, X86Opcode::LEA as u32);
    }

    #[test]
    fn test_emitter_32bit_mode() {
        let emitter = X86InstrEmitter::new_32bit(X86Subtarget::new("x86-64", "generic"), "test32");
        assert!(!emitter.isel.is_64bit);
    }

    // === Pipeline Extended Tests ===

    #[test]
    fn test_pipeline_empty_function() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline(&subtarget, "empty", |builder| {
            builder.lower_ret(None);
        });
        assert_eq!(mf.name, "empty");
    }

    #[test]
    fn test_pipeline_full_arithmetic_chain() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline(&subtarget, "arith_chain", |builder| {
            let x = builder.x86_dag.get_vreg(Type::integer(32));
            let y = builder.x86_dag.get_vreg(Type::integer(32));
            let z = builder.x86_dag.get_vreg(Type::integer(32));

            let t1 = builder.lower_add(x, y);
            let t2 = builder.lower_sub(t1, z);
            let t3 = builder.lower_mul(t2, x);
            let t4 = builder.lower_and(t3, y);
            let t5 = builder.lower_or(t4, z);
            let t6 = builder.lower_xor(t5, x);

            builder.lower_ret(Some(t6));
        });
        assert_eq!(mf.name, "arith_chain");
        assert!(!mf.blocks.is_empty());
    }

    #[test]
    fn test_pipeline_with_comparisons() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline(&subtarget, "cmp_chain", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let b = builder.x86_dag.get_vreg(Type::integer(32));
            let eq = builder.lower_icmp(a, b, 0, false);
            let gt = builder.lower_icmp(a, b, 2, true);

            let fa = builder.x86_dag.get_vreg(Type::double_precision());
            let fb = builder.x86_dag.get_vreg(Type::double_precision());
            let oeq = builder.lower_fcmp(fa, fb, 0);

            builder.lower_ret(Some(eq));
        });
        assert_eq!(mf.name, "cmp_chain");
    }

    #[test]
    fn test_pipeline_32bit_full() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline_32bit(&subtarget, "full32", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let b = builder.x86_dag.get_vreg(Type::integer(32));
            let sum = builder.lower_add(a, b);
            let ext = builder.lower_zext(sum, Type::integer(64));
            builder.lower_ret(Some(ext));
        });
        assert_eq!(mf.name, "full32");
    }

    #[test]
    fn test_pipeline_with_calls_and_args() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline(&subtarget, "call_with_args", |builder| {
            let callee = builder.x86_dag.get_vreg(Type::pointer(0));
            let arg1 = builder.x86_dag.get_vreg(Type::integer(32));
            let arg2 = builder.x86_dag.get_vreg(Type::integer(32));
            let (result, _chain) = builder.lower_call(
                callee,
                &[arg1, arg2],
                Type::integer(32),
                false,
            );
            builder.lower_ret(Some(result));
        });
        assert_eq!(mf.name, "call_with_args");
    }

    #[test]
    fn test_pipeline_tail_call() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let mf = run_x86_dag_pipeline(&subtarget, "tail_call", |builder| {
            let callee = builder.x86_dag.get_vreg(Type::pointer(0));
            let arg = builder.x86_dag.get_vreg(Type::integer(32));
            let (_, _) = builder.lower_call(
                callee,
                &[arg],
                Type::integer(32),
                true,
            );
            builder.lower_ret(None);
        });
        assert_eq!(mf.name, "tail_call");
    }

    // === Complex Pattern Matcher Extended Tests ===

    #[test]
    fn test_complex_pattern_all_addressing_patterns() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        let mut dag = X86SelectionDAG::new(subtarget, cc);

        // Test with FrameIndex
        let fi = dag.get_frame_index(Type::pointer(0));
        let mut matcher = X86ComplexPatternMatcher::new();
        assert!(matcher.match_addressing_mode(&dag, fi.node_id));
        matcher.reset();

        // Test with Constant (absolute)
        let c = dag.dag.get_constant(0x1000, Type::integer(64));
        dag.node_info.insert(c.node_id, X86DAGNode {
            node: SDNode::new(0, SDOpcode::Constant, vec![]),
            x86_opcode: None, condition_code: None,
            addressing_mode: None, mem_operand: None,
            target_constant: Some(0x1000),
        });
        assert!(matcher.match_addressing_mode(&dag, c.node_id));
    }

    #[test]
    fn test_complex_pattern_shl_scale_all() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        let mut dag = X86SelectionDAG::new(subtarget, cc);
        let x = dag.get_vreg(Type::integer(32));

        for &shift in &[0i64, 1, 2, 3] {
            let amount = dag.dag.get_constant(shift, Type::integer(8));
            dag.node_info.insert(amount.node_id, X86DAGNode {
                node: SDNode::new(0, SDOpcode::Constant, vec![]),
                x86_opcode: None, condition_code: None,
                addressing_mode: None, mem_operand: None,
                target_constant: Some(shift),
            });
            let shl = dag.dag.get_binary_op(SDOpcode::Shl, Type::integer(32), x, amount);
            let mut matcher = X86ComplexPatternMatcher::new();
            let matched = matcher.match_addressing_mode(&dag, shl.node_id);
            assert!(matched || shift > 3); // scale > 8 not representable
        }
    }

    // === Immediate Folder Extended Tests ===

    #[test]
    fn test_immediate_folder_all_binary_ops() {
        let folder = X86ImmediateFolder::new(true);
        let test_cases = [
            (SDOpcode::Add, X86Opcode::ADD),
            (SDOpcode::Sub, X86Opcode::SUB),
            (SDOpcode::And, X86Opcode::AND),
            (SDOpcode::Or, X86Opcode::OR),
            (SDOpcode::Xor, X86Opcode::XOR),
            (SDOpcode::Mul, X86Opcode::IMUL),
        ];
        for &(sd_op, x86_op) in &test_cases {
            assert_eq!(folder.try_fold_imm_binary(sd_op, 42), Some(x86_op));
        }
    }

    #[test]
    fn test_immediate_folder_shift_masking() {
        let folder = X86ImmediateFolder::new(true);
        // Shift amounts are masked: 5 bits for 32-bit, 6 bits for 64-bit
        let result = folder.try_fold_imm_shift(SDOpcode::Shl, 100);
        assert_eq!(result, Some((X86Opcode::SHL, 100 & 0x3F)));
    }

    // === Pattern Table Extended Tests ===

    #[test]
    fn test_pattern_table_all_basic_ops_have_patterns() {
        let table = X86ISelPatternTable::new();
        let basic_ops = [
            SDOpcode::Add, SDOpcode::Sub, SDOpcode::Mul,
            SDOpcode::SDiv, SDOpcode::UDiv,
            SDOpcode::And, SDOpcode::Or, SDOpcode::Xor,
            SDOpcode::Shl, SDOpcode::Sra, SDOpcode::Srl,
            SDOpcode::Load, SDOpcode::Store,
            SDOpcode::Br, SDOpcode::BrCond, SDOpcode::Ret, SDOpcode::Call,
            SDOpcode::ZExt, SDOpcode::SExt,
            SDOpcode::SIToFP, SDOpcode::FPToSI,
            SDOpcode::Select,
        ];
        for &op in &basic_ops {
            let pats = table.lookup(op);
            assert!(!pats.is_empty(), "No patterns for {:?}", op);
        }
    }

    // === ABI Arg Layout Extended Tests ===

    #[test]
    fn test_abi_layout_sse_args() {
        let layout = X86ABIArgLayout::x86_64_sysv();
        for i in 0..8u32 {
            assert_eq!(layout.get_sse_arg_reg(i), Some(i));
        }
        assert_eq!(layout.get_sse_arg_reg(8), None);
    }

    #[test]
    fn test_abi_layout_ret_regs() {
        let layout = X86ABIArgLayout::x86_64_sysv();
        assert_eq!(layout.ret_regs.len(), 2);
        assert_eq!(layout.ret_regs[0], 0); // RAX
        assert_eq!(layout.ret_regs[1], 1); // RDX
    }

    // === DAG Utils Extended Tests ===

    #[test]
    fn test_dag_utils_all_integer_types() {
        for bits in &[1u32, 8, 16, 32, 64, 128] {
            let ty = Type::integer(*bits);
            let legal_64 = X86DAGUtils::is_type_legal(&ty, true);
            let legal_32 = X86DAGUtils::is_type_legal(&ty, false);
            match bits {
                8 | 16 | 32 => {
                    assert!(legal_64);
                    assert!(legal_32);
                }
                64 => {
                    assert!(legal_64);
                    assert!(!legal_32);
                }
                _ => {
                    assert!(!legal_64);
                    assert!(!legal_32);
                }
            }
        }
    }

    // === X86RegClass Extended Tests ===

    #[test]
    fn test_reg_class_all_sizes() {
        assert_eq!(X86RegClass::Gpr8.size_bits(), 8);
        assert_eq!(X86RegClass::Gpr16.size_bits(), 16);
        assert_eq!(X86RegClass::Gpr32.size_bits(), 32);
        assert_eq!(X86RegClass::Gpr64.size_bits(), 64);
        assert_eq!(X86RegClass::Xmm.size_bits(), 128);
        assert_eq!(X86RegClass::Ymm.size_bits(), 256);
        assert_eq!(X86RegClass::Zmm.size_bits(), 512);
        assert_eq!(X86RegClass::Mask.size_bits(), 64);
    }

    // === Cross-Component Integration Tests ===

    #[test]
    fn test_full_flow_builder_to_emitter() {
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        let mut builder = X86DAGBuilder::new(subtarget.clone(), cc);

        let a = builder.x86_dag.get_vreg(Type::integer(32));
        let b = builder.x86_dag.get_vreg(Type::integer(32));
        let sum = builder.lower_add(a, b);
        builder.lower_ret(Some(sum));

        let mut x86_dag = builder.finish();

        let mut combiner = X86DAGCombine::new(subtarget.clone());
        combiner.combine(&mut x86_dag);

        let mut legalizer = X86DAGLegalize::new(subtarget.clone());
        legalizer.legalize(&mut x86_dag);

        let mut emitter = X86InstrEmitter::new(subtarget, "full_flow");
        let mf = emitter.emit(x86_dag);
        assert_eq!(mf.name, "full_flow");
        assert!(!mf.blocks.is_empty());
    }

    #[test]
    fn test_all_combine_patterns_together() {
        let mut dag = make_dag();
        let x = dag.get_vreg(Type::integer(32));
        let zero = dag.dag.get_constant(0u64, Type::integer(32));
        let one = dag.dag.get_constant(1u64, Type::integer(32));

        dag.node_info.insert(zero.node_id, X86DAGNode {
            node: SDNode::new(0, SDOpcode::Constant, vec![]),
            x86_opcode: None, condition_code: None,
            addressing_mode: None, mem_operand: None,
            target_constant: Some(0),
        });
        dag.node_info.insert(one.node_id, X86DAGNode {
            node: SDNode::new(0, SDOpcode::Constant, vec![]),
            x86_opcode: None, condition_code: None,
            addressing_mode: None, mem_operand: None,
            target_constant: Some(1),
        });

        // Create a variety of nodes that should trigger combines
        let _add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), x, zero);
        let _sub = dag.dag.get_binary_op(SDOpcode::Sub, Type::integer(32), x, zero);
        let _mul = dag.dag.get_binary_op(SDOpcode::Mul, Type::integer(32), x, one);
        let _xor = dag.dag.get_binary_op(SDOpcode::Xor, Type::integer(32), x, zero);
        let _shl = dag.dag.get_binary_op(SDOpcode::Shl, Type::integer(32), x, zero);

        let mut combiner = X86DAGCombine::new(X86Subtarget::new("x86-64", "generic"));
        combiner.combine(&mut dag);
        assert!(combiner.x86_num_combined > 0);
    }
}

// ============================================================================
// 13. Additional X86-specific SelectionDAG Operations
// ============================================================================

/// X86 addressing mode resolver — converts an Abstract X86AddressMode
/// into concrete register/physical register assignments.
pub struct X86AddressResolver {
    /// Base register (if resolved)
    pub base_reg: Option<u32>,
    /// Index register (if resolved)
    pub index_reg: Option<u32>,
    /// Scale factor (1, 2, 4, 8)
    pub scale: u8,
    /// Displacement value
    pub displacement: i64,
    /// Whether the address is RIP-relative
    pub is_rip_relative: bool,
    /// Whether the segment is overridden
    pub segment_override: Option<u32>,
}

impl X86AddressResolver {
    /// Create a new resolver.
    pub fn new() -> Self {
        Self {
            base_reg: None,
            index_reg: None,
            scale: 1,
            displacement: 0,
            is_rip_relative: false,
            segment_override: None,
        }
    }

    /// Resolve from an X86AddressMode.
    pub fn resolve(&mut self, addr_mode: &X86AddressMode) {
        self.base_reg = addr_mode.base_reg;
        self.index_reg = addr_mode.index_reg;
        self.scale = addr_mode.scale;
        self.displacement = addr_mode.displacement;
        self.is_rip_relative = addr_mode.is_rip_relative;
        self.segment_override = addr_mode.segment;
    }

    /// Check if register allocation is needed.
    pub fn needs_regalloc(&self) -> bool {
        self.base_reg.is_some() || self.index_reg.is_some()
    }

    /// Get the encoding form needed for ModR/M byte.
    pub fn get_encoding_form(&self) -> X86EncodingForm {
        match (self.base_reg, self.index_reg) {
            (None, None) => X86EncodingForm::DirectAddress,
            (Some(_), None) => X86EncodingForm::BaseDisp8Or32,
            (None, Some(_)) => X86EncodingForm::IndexScale,
            (Some(_), Some(_)) => X86EncodingForm::BaseIndexScale,
        }
    }
}

impl Default for X86AddressResolver {
    fn default() -> Self {
        Self::new()
    }
}

/// X86 encoding forms for ModR/M and SIB bytes.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86EncodingForm {
    DirectAddress,
    BaseDisp8Or32,
    IndexScale,
    BaseIndexScale,
    RIPRelative,
}

impl X86EncodingForm {
    /// Get the human-readable name.
    pub fn name(&self) -> &'static str {
        match self {
            X86EncodingForm::DirectAddress => "DirectAddress",
            X86EncodingForm::BaseDisp8Or32 => "Base+Disp",
            X86EncodingForm::IndexScale => "Index*Scale+Disp",
            X86EncodingForm::BaseIndexScale => "Base+Index*Scale+Disp",
            X86EncodingForm::RIPRelative => "RIP+Disp32",
        }
    }
}

/// X86-specific constant data for lowering.
#[derive(Debug, Clone)]
pub struct X86ConstantData {
    /// The integer value
    pub int_val: Option<i64>,
    /// The floating-point value (as bits)
    pub fp_val: Option<u64>,
    /// The type of the constant
    pub ty: Type,
    /// Whether this is a pool constant (needs constant pool entry)
    pub is_pool_constant: bool,
    /// Section where the constant should be placed
    pub section: Option<String>,
}

impl X86ConstantData {
    /// Create an integer constant.
    pub fn new_int(val: i64, ty: Type) -> Self {
        Self {
            int_val: Some(val),
            fp_val: None,
            ty,
            is_pool_constant: false,
            section: None,
        }
    }

    /// Create a floating-point constant.
    pub fn new_fp(val: f64, ty: Type) -> Self {
        Self {
            int_val: None,
            fp_val: Some(val.to_bits()),
            ty,
            is_pool_constant: true,
            section: Some(".rodata".into()),
        }
    }

    /// Check if this is an integer constant that fits in a signed 32-bit immediate.
    pub fn fits_imm32(&self) -> bool {
        match self.int_val {
            Some(v) => v >= -2147483648 && v <= 2147483647,
            None => false,
        }
    }

    /// Check if this is an integer constant that equals zero.
    pub fn is_zero(&self) -> bool {
        self.int_val == Some(0)
    }

    /// Check if this is an integer constant that equals one.
    pub fn is_one(&self) -> bool {
        self.int_val == Some(1)
    }

    /// Get the size in bytes of this constant.
    pub fn size_bytes(&self) -> u32 {
        X86DAGUtils::type_size_bytes(&self.ty)
    }
}

/// X86 flag tracking for SelectionDAG.
///
/// Tracks which EFLAGS bits are set/used by DAG nodes,
/// enabling optimizations like CMP→SUB elimination.
#[derive(Debug, Clone, Default)]
pub struct X86FlagTracker {
    /// Whether the zero flag (ZF) is used
    pub uses_zf: bool,
    /// Whether the sign flag (SF) is used
    pub uses_sf: bool,
    /// Whether the overflow flag (OF) is used
    pub uses_of: bool,
    /// Whether the carry flag (CF) is used
    pub uses_cf: bool,
    /// Whether the parity flag (PF) is used
    pub uses_pf: bool,
    /// The last node that defined EFLAGS
    pub last_flag_definer: Option<usize>,
    /// The condition code last used
    pub last_cc: Option<X86CondCode>,
}

impl X86FlagTracker {
    /// Create a new flag tracker.
    pub fn new() -> Self {
        Self::default()
    }

    /// Record that a node defines EFLAGS.
    pub fn record_definer(&mut self, node_id: usize) {
        self.last_flag_definer = Some(node_id);
        self.uses_zf = true;
        self.uses_sf = true;
        self.uses_cf = true;
        self.uses_of = true;
    }

    /// Record that a specific condition code was used.
    pub fn record_use(&mut self, cc: X86CondCode) {
        self.last_cc = Some(cc);
        match cc {
            X86CondCode::E | X86CondCode::NE => {
                self.uses_zf = true;
            }
            X86CondCode::L | X86CondCode::G | X86CondCode::LE | X86CondCode::GE => {
                self.uses_sf = true;
                self.uses_of = true;
            }
            X86CondCode::B | X86CondCode::A | X86CondCode::BE | X86CondCode::AE => {
                self.uses_cf = true;
            }
            X86CondCode::S | X86CondCode::NS => {
                self.uses_sf = true;
            }
            X86CondCode::O | X86CondCode::NO => {
                self.uses_of = true;
            }
            X86CondCode::P | X86CondCode::NP => {
                self.uses_pf = true;
            }
        }
    }

    /// Check if a CMP can be replaced by a SUB (when result is used).
    pub fn can_eliminate_cmp(&self) -> bool {
        // If all flag uses are satisfied, the explicit CMP may be redundant
        self.last_flag_definer.is_some()
    }

    /// Reset tracking for a new basic block.
    pub fn reset(&mut self) {
        *self = Self::default();
    }
}

/// X86 extended DAG statistics for profiling the selection pipeline.
#[derive(Debug, Clone, Default)]
pub struct X86DAGStats {
    /// Total number of DAG nodes created
    pub total_nodes: u64,
    /// Number of nodes combined away
    pub nodes_combined: u64,
    /// Number of nodes legalized (replaced)
    pub nodes_legalized: u64,
    /// Number of machine instructions emitted
    pub instructions_emitted: u64,
    /// Number of virtual registers allocated
    pub virtual_registers: u64,
    /// Number of memory operations
    pub memory_ops: u64,
    /// Number of branches
    pub branches: u64,
    /// Number of calls
    pub calls: u64,
    /// Number of vector operations
    pub vector_ops: u64,
    /// Critical path length
    pub critical_path: u32,
    /// Estimated cycle count
    pub estimated_cycles: u64,
    /// Number of SSE instructions
    pub sse_instructions: u64,
    /// Number of AVX instructions
    pub avx_instructions: u64,
    /// Number of AVX-512 instructions
    pub avx512_instructions: u64,
}

impl X86DAGStats {
    /// Create new stats.
    pub fn new() -> Self {
        Self::default()
    }

    /// Accumulate stats from a completed DAG.
    pub fn accumulate(&mut self, dag: &X86SelectionDAG) {
        self.total_nodes += dag.dag.nodes.len() as u64;
        for node_id in 0..dag.dag.nodes.len() {
            if let Some(node) = dag.dag.get_node(node_id) {
                match node.opcode {
                    SDOpcode::Load | SDOpcode::Store => self.memory_ops += 1,
                    SDOpcode::Br | SDOpcode::BrCond => self.branches += 1,
                    SDOpcode::Call => self.calls += 1,
                    SDOpcode::BuildVector | SDOpcode::ExtractElement
                        | SDOpcode::InsertElement | SDOpcode::VectorShuffle => {
                        self.vector_ops += 1;
                    }
                    _ => {}
                }
            }
        }
    }

    /// Print a summary of the statistics.
    pub fn summary(&self) -> String {
        format!(
            "X86DAGStats: nodes={} combined={} legalized={} instrs={} vregs={} \
             memops={} branches={} calls={} vecops={} critpath={} cycles={} \
             sse={} avx={} avx512={}",
            self.total_nodes,
            self.nodes_combined,
            self.nodes_legalized,
            self.instructions_emitted,
            self.virtual_registers,
            self.memory_ops,
            self.branches,
            self.calls,
            self.vector_ops,
            self.critical_path,
            self.estimated_cycles,
            self.sse_instructions,
            self.avx_instructions,
            self.avx512_instructions,
        )
    }
}

// ============================================================================
// 14. Extended Tests — Address Resolver, Flag Tracker, Stats
// ============================================================================

#[cfg(test)]
mod extended2_tests {
    use super::*;

    #[test]
    fn test_address_resolver_new() {
        let resolver = X86AddressResolver::new();
        assert!(resolver.base_reg.is_none());
        assert!(resolver.index_reg.is_none());
        assert_eq!(resolver.scale, 1);
        assert_eq!(resolver.displacement, 0);
    }

    #[test]
    fn test_address_resolver_resolve() {
        let am = X86AddressMode::new_base_index_scale(5, 2, 4, 16);
        let mut resolver = X86AddressResolver::new();
        resolver.resolve(&am);
        assert_eq!(resolver.base_reg, Some(5));
        assert_eq!(resolver.index_reg, Some(2));
        assert_eq!(resolver.scale, 4);
        assert_eq!(resolver.displacement, 16);
    }

    #[test]
    fn test_address_resolver_needs_regalloc() {
        let mut resolver = X86AddressResolver::new();
        assert!(!resolver.needs_regalloc());
        resolver.base_reg = Some(5);
        assert!(resolver.needs_regalloc());
    }

    #[test]
    fn test_address_resolver_encoding_forms() {
        let mut resolver = X86AddressResolver::new();
        assert_eq!(resolver.get_encoding_form(), X86EncodingForm::DirectAddress);
        resolver.base_reg = Some(5);
        assert_eq!(resolver.get_encoding_form(), X86EncodingForm::BaseDisp8Or32);
        resolver.base_reg = None;
        resolver.index_reg = Some(2);
        assert_eq!(resolver.get_encoding_form(), X86EncodingForm::IndexScale);
        resolver.base_reg = Some(5);
        assert_eq!(resolver.get_encoding_form(), X86EncodingForm::BaseIndexScale);
    }

    #[test]
    fn test_address_resolver_default() {
        let resolver = X86AddressResolver::default();
        assert!(!resolver.needs_regalloc());
    }

    #[test]
    fn test_encoding_form_name() {
        assert_eq!(X86EncodingForm::DirectAddress.name(), "DirectAddress");
        assert_eq!(X86EncodingForm::BaseDisp8Or32.name(), "Base+Disp");
        assert_eq!(X86EncodingForm::IndexScale.name(), "Index*Scale+Disp");
        assert_eq!(X86EncodingForm::BaseIndexScale.name(), "Base+Index*Scale+Disp");
        assert_eq!(X86EncodingForm::RIPRelative.name(), "RIP+Disp32");
    }

    #[test]
    fn test_constant_data_int() {
        let cd = X86ConstantData::new_int(42, Type::integer(32));
        assert_eq!(cd.int_val, Some(42));
        assert!(!cd.is_pool_constant);
        assert!(cd.fits_imm32());
        assert!(!cd.is_zero());
        assert!(!cd.is_one());
    }

    #[test]
    fn test_constant_data_fp() {
        let cd = X86ConstantData::new_fp(3.14, Type::double_precision());
        assert!(cd.is_pool_constant);
        assert_eq!(cd.section, Some(".rodata".into()));
    }

    #[test]
    fn test_constant_data_zero_one() {
        let cd0 = X86ConstantData::new_int(0, Type::integer(32));
        assert!(cd0.is_zero());
        assert!(!cd0.is_one());

        let cd1 = X86ConstantData::new_int(1, Type::integer(32));
        assert!(!cd1.is_zero());
        assert!(cd1.is_one());
    }

    #[test]
    fn test_constant_data_fits_imm32() {
        assert!(X86ConstantData::new_int(0, Type::integer(32)).fits_imm32());
        assert!(X86ConstantData::new_int(2147483647, Type::integer(32)).fits_imm32());
        assert!(X86ConstantData::new_int(-2147483648, Type::integer(32)).fits_imm32());
        assert!(!X86ConstantData::new_int(2147483648, Type::integer(64)).fits_imm32());
        assert!(!X86ConstantData::new_int(-2147483649, Type::integer(64)).fits_imm32());
    }

    #[test]
    fn test_constant_data_size_bytes() {
        assert_eq!(X86ConstantData::new_int(0, Type::integer(8)).size_bytes(), 1);
        assert_eq!(X86ConstantData::new_int(0, Type::integer(32)).size_bytes(), 4);
        assert_eq!(X86ConstantData::new_int(0, Type::integer(64)).size_bytes(), 8);
    }

    #[test]
    fn test_flag_tracker_new() {
        let ft = X86FlagTracker::new();
        assert!(!ft.uses_zf);
        assert!(!ft.uses_sf);
        assert!(ft.last_flag_definer.is_none());
    }

    #[test]
    fn test_flag_tracker_record_definer() {
        let mut ft = X86FlagTracker::new();
        ft.record_definer(42);
        assert!(ft.uses_zf);
        assert!(ft.uses_sf);
        assert!(ft.uses_cf);
        assert!(ft.uses_of);
        assert_eq!(ft.last_flag_definer, Some(42));
    }

    #[test]
    fn test_flag_tracker_record_use_all_ccs() {
        let all_ccs = [
            X86CondCode::E, X86CondCode::NE,
            X86CondCode::L, X86CondCode::G, X86CondCode::LE, X86CondCode::GE,
            X86CondCode::B, X86CondCode::A, X86CondCode::BE, X86CondCode::AE,
            X86CondCode::S, X86CondCode::NS,
            X86CondCode::O, X86CondCode::NO,
            X86CondCode::P, X86CondCode::NP,
        ];

        for &cc in &all_ccs {
            let mut ft = X86FlagTracker::new();
            ft.record_use(cc);
            assert_eq!(ft.last_cc, Some(cc));
        }
    }

    #[test]
    fn test_flag_tracker_can_eliminate_cmp() {
        let mut ft = X86FlagTracker::new();
        assert!(!ft.can_eliminate_cmp());
        ft.record_definer(10);
        assert!(ft.can_eliminate_cmp());
    }

    #[test]
    fn test_flag_tracker_reset() {
        let mut ft = X86FlagTracker::new();
        ft.record_definer(10);
        ft.record_use(X86CondCode::E);
        ft.reset();
        assert!(!ft.uses_zf);
        assert!(ft.last_flag_definer.is_none());
        assert!(ft.last_cc.is_none());
    }

    #[test]
    fn test_flag_tracker_default() {
        let ft = X86FlagTracker::default();
        assert!(!ft.can_eliminate_cmp());
    }

    #[test]
    fn test_dag_stats_new() {
        let stats = X86DAGStats::new();
        assert_eq!(stats.total_nodes, 0);
        assert_eq!(stats.nodes_combined, 0);
        assert_eq!(stats.instructions_emitted, 0);
    }

    #[test]
    fn test_dag_stats_accumulate() {
        let mut stats = X86DAGStats::new();
        let subtarget = X86Subtarget::new("x86-64", "generic");
        let cc = X86CallingConvention::default();
        let mut dag = X86SelectionDAG::new(subtarget, cc);

        // Add various nodes to the DAG
        let a = dag.get_vreg(Type::integer(32));
        let b = dag.get_vreg(Type::integer(32));
        let _add = dag.dag.get_binary_op(SDOpcode::Add, Type::integer(32), a, b);
        let _load = dag.dag.get_binary_op(SDOpcode::Load, a, b);

        stats.accumulate(&dag);
        assert!(stats.total_nodes > 0);
    }

    #[test]
    fn test_dag_stats_summary() {
        let stats = X86DAGStats::new();
        let summary = stats.summary();
        assert!(summary.contains("X86DAGStats"));
        assert!(summary.contains("nodes="));
    }
}

// ============================================================================
// 15. X86 SelectionDAG Pipeline Orchestrator
// ============================================================================

/// The complete X86 SelectionDAG pipeline orchestrator.
///
/// Coordinates the full pipeline from DAG building through legalization
/// and instruction selection, collecting statistics and applying
/// target-specific optimizations at each stage.
pub struct X86DAGPipeline {
    /// The subtarget configuration
    pub subtarget: X86Subtarget,
    /// The calling convention
    pub calling_conv: X86CallingConvention,
    /// Whether to enable the DAG combiner
    pub enable_combiner: bool,
    /// Whether to enable DAG legalization
    pub enable_legalizer: bool,
    /// Maximum combine iterations
    pub max_combine_iterations: u32,
    /// Scheduling model kind
    pub sched_model_kind: X86SchedModelKind,
    /// Accumulated statistics
    pub stats: X86DAGStats,
}

impl X86DAGPipeline {
    /// Create a new pipeline for X86-64.
    pub fn new(subtarget: X86Subtarget) -> Self {
        Self {
            subtarget,
            calling_conv: X86CallingConvention::default(),
            enable_combiner: true,
            enable_legalizer: true,
            max_combine_iterations: 4,
            sched_model_kind: X86SchedModelKind::Zen3,
            stats: X86DAGStats::new(),
        }
    }

    /// Create a new pipeline for 32-bit X86.
    pub fn new_32bit(subtarget: X86Subtarget) -> Self {
        Self {
            subtarget,
            calling_conv: X86CallingConvention::default(),
            enable_combiner: true,
            enable_legalizer: true,
            max_combine_iterations: 4,
            sched_model_kind: X86SchedModelKind::Zen3,
            stats: X86DAGStats::new(),
        }
    }

    /// Disable the DAG combiner.
    pub fn without_combiner(mut self) -> Self {
        self.enable_combiner = false;
        self
    }

    /// Disable the DAG legalizer.
    pub fn without_legalizer(mut self) -> Self {
        self.enable_legalizer = false;
        self
    }

    /// Set the maximum combine iterations.
    pub fn with_max_combine_iterations(mut self, n: u32) -> Self {
        self.max_combine_iterations = n;
        self
    }

    /// Set the scheduling model.
    pub fn with_sched_model(mut self, kind: X86SchedModelKind) -> Self {
        self.sched_model_kind = kind;
        self
    }

    /// Run the full pipeline on an IR-to-DAG build function.
    pub fn run(
        &mut self,
        func_name: &str,
        build_fn: impl FnOnce(&mut X86DAGBuilder),
    ) -> MachineFunction {
        let mut builder = X86DAGBuilder::new(
            self.subtarget.clone(),
            self.calling_conv.clone(),
        );

        // Step 1: Build
        build_fn(&mut builder);
        let mut x86_dag = builder.finish();
        self.stats.accumulate(&x86_dag);
        self.stats.total_nodes = x86_dag.dag.nodes.len() as u64;

        // Step 2: Combine
        if self.enable_combiner {
            let mut combiner = X86DAGCombine::new(self.subtarget.clone());
            combiner.max_iterations = self.max_combine_iterations;
            combiner.combine(&mut x86_dag);
            self.stats.nodes_combined = combiner.x86_num_combined;
        }

        // Step 3: Legalize
        if self.enable_legalizer {
            let mut legalizer = X86DAGLegalize::new(self.subtarget.clone());
            legalizer.legalize(&mut x86_dag);
            self.stats.nodes_legalized =
                x86_dag.dag.nodes.len() as u64 - self.stats.total_nodes;
        }

        // Step 4: Compute scheduling info
        {
            let mut sched = X86DAGSchedModel::new(self.sched_model_kind);
            self.stats.critical_path = sched.compute_critical_path(&x86_dag);
        }

        // Step 5: ISel + Emit
        let mut emitter = X86InstrEmitter::new(self.subtarget.clone(), func_name);
        emitter.emit(x86_dag);
        let mf = emitter.finish();

        // Count instructions
        for block in &mf.blocks {
            self.stats.instructions_emitted += block.instructions.len() as u64;
            for instr in &block.instructions {
                // Categorize instruction types
                let opcode = instr.opcode;
                if opcode >= X86Opcode::ADDSS as u32 && opcode <= X86Opcode::HSUBPD as u32 {
                    self.stats.sse_instructions += 1;
                }
                if opcode >= X86Opcode::VADDPS as u32 && opcode <= X86Opcode::VZEROUPPER as u32 {
                    self.stats.avx_instructions += 1;
                }
                if opcode >= X86Opcode::VPADDD_Z as u32 {
                    self.stats.avx512_instructions += 1;
                }
            }
        }

        mf
    }

    /// Run on a 32-bit target.
    pub fn run_32bit(
        &mut self,
        func_name: &str,
        build_fn: impl FnOnce(&mut X86DAGBuilder),
    ) -> MachineFunction {
        let mut builder = X86DAGBuilder::new_32bit(
            self.subtarget.clone(),
            self.calling_conv.clone(),
        );

        build_fn(&mut builder);
        let mut x86_dag = builder.finish();
        self.stats.accumulate(&x86_dag);

        if self.enable_combiner {
            let mut combiner = X86DAGCombine::new(self.subtarget.clone());
            combiner.combine(&mut x86_dag);
            self.stats.nodes_combined = combiner.x86_num_combined;
        }

        if self.enable_legalizer {
            let mut legalizer = X86DAGLegalize::new_32bit(self.subtarget.clone());
            legalizer.legalize(&mut x86_dag);
        }

        let mut emitter = X86InstrEmitter::new_32bit(self.subtarget.clone(), func_name);
        emitter.emit(x86_dag);
        emitter.finish()
    }
}

// ============================================================================
// 16. Extended Pipeline Tests
// ============================================================================

#[cfg(test)]
mod pipeline_extended_tests {
    use super::*;

    fn make_pipeline() -> X86DAGPipeline {
        X86DAGPipeline::new(X86Subtarget::new("x86-64", "generic"))
    }

    #[test]
    fn test_pipeline_creation() {
        let pipeline = make_pipeline();
        assert!(pipeline.enable_combiner);
        assert!(pipeline.enable_legalizer);
        assert_eq!(pipeline.max_combine_iterations, 4);
    }

    #[test]
    fn test_pipeline_without_combiner() {
        let pipeline = make_pipeline().without_combiner();
        assert!(!pipeline.enable_combiner);
        assert!(pipeline.enable_legalizer);
    }

    #[test]
    fn test_pipeline_without_legalizer() {
        let pipeline = make_pipeline().without_legalizer();
        assert!(pipeline.enable_combiner);
        assert!(!pipeline.enable_legalizer);
    }

    #[test]
    fn test_pipeline_with_max_iterations() {
        let pipeline = make_pipeline().with_max_combine_iterations(10);
        assert_eq!(pipeline.max_combine_iterations, 10);
    }

    #[test]
    fn test_pipeline_with_sched_model() {
        let pipeline = make_pipeline().with_sched_model(X86SchedModelKind::IceLake);
        assert_eq!(pipeline.sched_model_kind, X86SchedModelKind::IceLake);
    }

    #[test]
    fn test_pipeline_run_simple() {
        let mut pipeline = make_pipeline();
        let mf = pipeline.run("simple", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            builder.lower_ret(Some(a));
        });
        assert_eq!(mf.name, "simple");
        assert!(pipeline.stats.instructions_emitted > 0);
    }

    #[test]
    fn test_pipeline_run_arithmetic() {
        let mut pipeline = make_pipeline();
        let mf = pipeline.run("arith", |builder| {
            let x = builder.x86_dag.get_vreg(Type::integer(32));
            let y = builder.x86_dag.get_vreg(Type::integer(32));
            let z = builder.x86_dag.get_vreg(Type::integer(32));
            let t1 = builder.lower_add(x, y);
            let t2 = builder.lower_mul(t1, z);
            builder.lower_ret(Some(t2));
        });
        assert_eq!(mf.name, "arith");
    }

    #[test]
    fn test_pipeline_run_32bit() {
        let mut pipeline = X86DAGPipeline::new_32bit(X86Subtarget::new("x86-64", "generic"));
        let mf = pipeline.run_32bit("simple32", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            builder.lower_ret(Some(a));
        });
        assert_eq!(mf.name, "simple32");
    }

    #[test]
    fn test_pipeline_stats_accumulation() {
        let mut pipeline = make_pipeline();
        pipeline.run("stats_test", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            let b = builder.x86_dag.get_vreg(Type::integer(32));
            let sum = builder.lower_add(a, b);
            let diff = builder.lower_sub(sum, a);
            builder.lower_ret(Some(diff));
        });
        assert!(pipeline.stats.instructions_emitted > 0);
        assert!(pipeline.stats.total_nodes > 0);
    }

    #[test]
    fn test_pipeline_run_without_combiner() {
        let mut pipeline = make_pipeline().without_combiner();
        let mf = pipeline.run("no_combine", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            builder.lower_ret(Some(a));
        });
        assert_eq!(mf.name, "no_combine");
    }

    #[test]
    fn test_pipeline_run_without_legalizer() {
        let mut pipeline = make_pipeline().without_legalizer();
        let mf = pipeline.run("no_legalize", |builder| {
            let a = builder.x86_dag.get_vreg(Type::integer(32));
            builder.lower_ret(Some(a));
        });
        assert_eq!(mf.name, "no_legalize");
    }

    #[test]
    fn test_pipeline_idempotent_runs() {
        let subtarget = X86Subtarget::new("x86-64", "generic");

        let mf1 = {
            let mut pipeline = X86DAGPipeline::new(subtarget.clone());
            pipeline.run("idem", |builder| {
                let a = builder.x86_dag.get_vreg(Type::integer(32));
                builder.lower_ret(Some(a));
            })
        };

        let mf2 = {
            let mut pipeline = X86DAGPipeline::new(subtarget.clone());
            pipeline.run("idem", |builder| {
                let a = builder.x86_dag.get_vreg(Type::integer(32));
                builder.lower_ret(Some(a));
            })
        };

        assert_eq!(mf1.name, mf2.name);
        assert_eq!(mf1.blocks.len(), mf2.blocks.len());
    }

    #[test]
    fn test_pipeline_multiple_sched_models() {
        let models = [
            X86SchedModelKind::SkylakeClient,
            X86SchedModelKind::IceLake,
            X86SchedModelKind::Zen3,
            X86SchedModelKind::Zen4,
            X86SchedModelKind::Zen5,
        ];

        for &model in &models {
            let mut pipeline = make_pipeline().with_sched_model(model);
            let mf = pipeline.run("sched_test", |builder| {
                let a = builder.x86_dag.get_vreg(Type::integer(32));
                builder.lower_ret(Some(a));
            });
            assert_eq!(mf.name, "sched_test");
        }
    }
}