llvm-native-core 0.1.6

//! Complete X86 instruction set — every instruction from Intel SDM Vol 2
//! plus extensions through AVX-512, AMX, CET, and more.
//!
//! This module provides:
//! - `X86FullOpcode`: 500+ instruction opcode enumeration
//! - `EncodingForm`: Instruction encoding format classification
//! - `InstrEncodingInfo`: Per-instruction encoding metadata
//! - `X86FullInstrInfo`: Complete instruction database with lookups
//!
//! Clean-room reconstruction from:
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual Vol 2
//! - AMD64 Architecture Programmer's Manual Vol 3
//! - Agner Fog's instruction tables

use std::collections::HashMap;

use super::x86_instr_info::OperandType;

// ============================================================================
// X86FullOpcode — complete x86 instruction opcode enumeration (500+ instructions)
// ============================================================================

/// Complete X86 instruction set covering every instruction from Intel SDM Vol 2
/// plus all major extensions (SSE through AVX-512, AMX, CET, etc.).
///
/// Values are chosen to extend the existing `X86Opcode` enum without collision:
/// all X86FullOpcode discriminants start at 400, leaving room for future
/// additions to the basic opcode set.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[repr(u32)]
#[allow(non_camel_case_types)]
pub enum X86FullOpcode {
    // === Data Transfer — MOV variants ===
    MOVrr = 400,
    MOVrm,
    MOVmr,
    MOVri,
    MOVmi,
    MOVSD,
    MOVSS,
    MOVAPS,
    MOVUPS,
    MOVDQA,
    MOVDQU,
    MOVZX,
    MOVSXD,
    MOVBE,
    MOVD,
    MOVQ,

    // === CMOVcc (16 variants) ===
    CMOVO,
    CMOVNO,
    CMOVB_FULL,
    CMOVAE_FULL,
    CMOVE_FULL,
    CMOVNE_FULL,
    CMOVBE_FULL,
    CMOVA_FULL,
    CMOVS_FULL,
    CMOVNS_FULL,
    CMOVP_FULL,
    CMOVNP_FULL,
    CMOVL_FULL,
    CMOVGE_FULL,
    CMOVLE_FULL,
    CMOVG_FULL,

    // === Data Transfer — miscellaneous ===
    XCHG,
    BSWAP,
    CMPXCHG,
    CMPXCHG8B,
    CMPXCHG16B,
    PUSHA,
    POPA,
    CWD,
    CDQ,
    CQO,
    CBW,
    CWDE,
    CDQE,

    // === Arithmetic ===
    ADD,
    ADC,
    SUB,
    SBB,
    MUL,
    IMUL,
    DIV,
    IDIV,
    INC,
    DEC,
    NEG,
    CMP,
    CMPXCHG_FULL,
    XADD,
    AAA,
    AAS,
    AAM,
    AAD,
    DAA,
    DAS,

    // === Logical ===
    AND,
    OR,
    XOR,
    NOT,
    TEST,

    // === Shifts/Rotates ===
    SHL,
    SHR,
    SAR,
    ROL,
    ROR,
    RCL,
    RCR,
    SHLD,
    SHRD,

    // === String Operations ===
    MOVS,
    CMPS,
    SCAS,
    LODS,
    STOS,
    REP,
    REPE,
    REPNE,
    REPZ,
    REPNZ,

    // === Control Transfer ===
    JMP,
    JO,
    JNO,
    JB_FULL,
    JAE_FULL,
    JE_FULL,
    JNE_FULL,
    JBE_FULL,
    JA_FULL,
    JS_FULL,
    JNS_FULL,
    JP_FULL,
    JNP_FULL,
    JL_FULL,
    JGE_FULL,
    JLE_FULL,
    JG_FULL,
    LOOP,
    LOOPE,
    LOOPNE,
    CALL,
    RET,
    IRET,
    INT,
    INTO,
    BOUND,
    ENTER,
    LEAVE,

    // === Flag Operations ===
    STC,
    CLC,
    CMC,
    STD,
    CLD,
    STI,
    CLI,
    LAHF,
    SAHF,
    PUSHF,
    POPF,

    // === Conditional Set ===
    SETO,
    SETNO,
    SETB,
    SETAE,
    SETE,
    SETNE,
    SETBE,
    SETA,
    SETS,
    SETNS,
    SETP,
    SETNP,
    SETL,
    SETGE,
    SETLE,
    SETG,

    // === System ===
    IN,
    OUT,
    INS,
    OUTS,
    HLT,
    WAIT,
    LOCK,
    LGDT,
    SGDT,
    LIDT,
    SIDT,
    LLDT,
    SLDT,
    LTR,
    STR,
    LMSW,
    SMSW,
    INVLPG,
    INVD,
    WBINVD,
    RDMSR,
    WRMSR,
    RDTSC,
    RDTSCP,
    RDPMC,
    CPUID,
    SYSCALL,
    SYSRET,
    SYSENTER,
    SYSEXIT,

    // === FPU (x87) ===
    FLD,
    FST,
    FSTP,
    FILD,
    FIST,
    FISTP,
    FBLD,
    FBSTP,
    FADD,
    FSUB,
    FMUL,
    FDIV,
    FABS,
    FCHS,
    FSQRT,
    FPREM,
    FPREM1,
    FCOM,
    FCOMP,
    FCOMPP,
    FUCOM,
    FUCOMP,
    FUCOMPP,
    FTST,
    FXAM,
    FSIN,
    FCOS,
    FSINCOS,
    FPTAN,
    FPATAN,
    F2XM1,
    FYL2X,
    FYL2XP1,
    FLDZ,
    FLD1,
    FLDPI,
    FLDL2T,
    FLDL2E,
    FLDLG2,
    FLDLN2,
    FNCLEX,
    FNDISI,
    FNENI,
    FNINIT,
    FNSTSW,
    FNSTCW,
    FLDCW,
    FSTCW,
    FSTSW,
    FFREE,
    FDECSTP,
    FINCSTP,
    FXCH,

    // === MMX ===
    MOVD_MMX,
    MOVQ_MMX,
    PACKSSWB,
    PACKSSDW,
    PACKUSWB,
    PADDB,
    PADDW,
    PADDD,
    PADDSB,
    PADDSW,
    PADDUSB,
    PADDUSW,
    PSUBB,
    PSUBW,
    PSUBD,
    PSUBSB,
    PSUBSW,
    PSUBUSB,
    PSUBUSW,
    PMULLW,
    PMULHW,
    PMADDWD,
    PCMPEQB,
    PCMPEQW,
    PCMPEQD,
    PCMPGTB,
    PCMPGTW,
    PCMPGTD,
    PAND,
    PANDN,
    POR,
    PXOR,
    PSLLW,
    PSLLD,
    PSLLQ,
    PSRLW,
    PSRLD,
    PSRLQ,
    PSRAW,
    PSRAD,
    PUNPCKHBW,
    PUNPCKHWD,
    PUNPCKHDQ,
    PUNPCKLBW,
    PUNPCKLWD,
    PUNPCKLDQ,

    // === SSE ===
    ADDPS,
    ADDSS,
    SUBPS,
    SUBSS,
    MULPS,
    MULSS,
    DIVPS,
    DIVSS,
    RCPPS,
    RCPSS,
    SQRTPS,
    SQRTSS,
    RSQRTPS,
    RSQRTSS,
    MAXPS,
    MAXSS,
    MINPS,
    MINSS,
    ANDPS,
    ANDNPS,
    ORPS,
    XORPS,
    CMPPS,
    CMPSS,
    SHUFPS,
    UNPCKHPS,
    UNPCKLPS,
    MOVMSKPS,
    MOVHLPS,
    MOVLHPS,
    MOVLPS,
    MOVHPS,

    // === SSE2 ===
    ADDPD,
    ADDSD,
    SUBPD,
    SUBSD,
    MULPD,
    MULSD,
    DIVPD,
    DIVSD,
    SQRTPD,
    SQRTSD,
    MAXPD,
    MAXSD,
    MINPD,
    MINSD,
    ANDPD,
    ANDNPD,
    ORPD,
    XORPD,
    CMPPD,
    CMPSD,
    SHUFPD,
    UNPCKHPD,
    UNPCKLPD,
    MOVMSKPD,
    MOVUPD,
    MOVAPD,
    MOVLPD,
    MOVHPD,
    CVTDQ2PD,
    CVTDQ2PS,
    CVTPD2DQ,
    CVTPD2PS,
    CVTPS2DQ,
    CVTPS2PD,
    CVTSD2SI,
    CVTSD2SS,
    CVTSI2SD,
    CVTSI2SS,
    CVTSS2SD,
    CVTSS2SI,
    CVTTPD2DQ,
    CVTTPS2DQ,
    CVTTSD2SI,
    CVTTSS2SI,
    PADDB_128,
    PADDW_128,
    PADDD_128,
    PADDQ_128,
    PSUBB_128,
    PSUBW_128,
    PSUBD_128,
    PSUBQ_128,
    PMULUDQ,
    PMULLW_128,
    PMULHW_128,
    PMULHUW,
    PSADBW,
    PAVGB,
    PAVGW,
    PMINUB,
    PMINSW,
    PMAXUB,
    PMAXSW,
    PSLLW_128,
    PSLLD_128,
    PSLLQ_128,
    PSRLW_128,
    PSRLD_128,
    PSRLQ_128,
    PSRAW_128,
    PSRAD_128,
    MASKMOVDQU,
    MOVQ2DQ,
    MOVDQ2Q,
    PUNPCKLBW_128,
    PUNPCKLWD_128,
    PUNPCKLDQ_128,
    PUNPCKLQDQ,
    PUNPCKHBW_128,
    PUNPCKHWD_128,
    PUNPCKHDQ_128,
    PUNPCKHQDQ,
    PACKSSWB_128,
    PACKSSDW_128,
    PACKUSWB_128,
    PAND_128,
    PANDN_128,
    POR_128,
    PXOR_128,
    PCMPEQB_128,
    PCMPEQW_128,
    PCMPEQD_128,

    // === SSE3 ===
    ADDSUBPS,
    ADDSUBPD,
    HADDPS,
    HADDPD,
    HSUBPS,
    HSUBPD,
    MOVSLDUP,
    MOVSHDUP,
    MOVDDUP,
    LDDQU,
    FISTTP,
    MONITOR,
    MWAIT,

    // === SSSE3 ===
    PHADDW,
    PHADDD,
    PHADDSW,
    PHSUBW,
    PHSUBD,
    PHSUBSW,
    PMADDUBSW,
    PMULHRSW,
    PSHUFB,
    PSIGNB,
    PSIGNW,
    PSIGND,
    PABSB,
    PABSW,
    PABSD,
    PALIGNR,
    PSHUFB_ALT,

    // === SSE4.1 ===
    PMULLD,
    PMULDQ,
    DPPS,
    DPPD,
    BLENDPS,
    BLENDPD,
    BLENDVPS,
    BLENDVPD,
    PMINSB,
    PMINSD,
    PMINUW,
    PMINUD,
    PMAXSB,
    PMAXSD,
    PMAXUW,
    PMAXUD,
    PACKUSDW,
    PCMPEQQ,
    PINSRB,
    PINSRD,
    PINSRQ,
    PEXTRB,
    PEXTRD,
    PEXTRQ,
    PTEST,
    ROUNDPS,
    ROUNDPD,
    ROUNDSS,
    ROUNDSD,
    CRC32,
    EXTRACTPS,
    INSERTPS,
    PMOVSXBW,
    PMOVSXBD,
    PMOVSXBQ,
    PMOVSXWD,
    PMOVSXWQ,
    PMOVSXDQ,
    PMOVZXBW,
    PMOVZXBD,
    PMOVZXBQ,
    PMOVZXWD,
    PMOVZXWQ,
    PMOVZXDQ,
    MPSADBW,
    PHMINPOSUW,

    // === SSE4.2 ===
    PCMPESTRI,
    PCMPESTRM,
    PCMPISTRI,
    PCMPISTRM,
    PCMPGTQ,

    // === AVX ===
    VADDPS,
    VADDPD,
    VADDSS,
    VADDSD,
    VSUBPS,
    VSUBPD,
    VSUBSS,
    VSUBSD,
    VMULPS,
    VMULPD,
    VMULSS,
    VMULSD,
    VDIVPS,
    VDIVPD,
    VDIVSS,
    VDIVSD,
    VANDPS,
    VANDNPS,
    VORPS,
    VXORPS,
    VZEROALL,
    VZEROUPPER,
    VMOVAPS,
    VMOVUPS,
    VMOVAPD,
    VMOVUPD,
    VBROADCASTSS,
    VBROADCASTSD,
    VBROADCASTF128,
    VPERMILPS,
    VPERMILPD,
    VPERM2F128,
    VEXTRACTF128,
    VINSERTF128,
    VCVTPH2PS,
    VCVTPS2PH,

    // === AVX2 ===
    VPBROADCASTB,
    VPBROADCASTW,
    VPBROADCASTD,
    VPBROADCASTQ,
    VPERMQ,
    VPERMPD,
    VPERM2I128,
    VPGATHERDD,
    VPGATHERDQ,
    VPGATHERQD,
    VPGATHERQQ,
    VPMASKMOVD,
    VPMASKMOVQ,
    VPSLLVD,
    VPSLLVQ,
    VPSRLVD,
    VPSRLVQ,
    VPSRAVD,

    // === FMA ===
    VFMADD132PS,
    VFMADD132PD,
    VFMADD132SS,
    VFMADD132SD,
    VFMADD213PS,
    VFMADD213PD,
    VFMADD213SS,
    VFMADD213SD,
    VFMADD231PS,
    VFMADD231PD,
    VFMADD231SS,
    VFMADD231SD,
    VFMSUB132PS,
    VFMSUB132PD,
    VFMSUB132SS,
    VFMSUB132SD,
    VFMSUB213PS,
    VFMSUB213PD,
    VFMSUB213SS,
    VFMSUB213SD,
    VFMSUB231PS,
    VFMSUB231PD,
    VFMSUB231SS,
    VFMSUB231SD,
    VFNMADD132PS,
    VFNMADD132PD,
    VFNMADD132SS,
    VFNMADD132SD,
    VFNMADD213PS,
    VFNMADD213PD,
    VFNMADD213SS,
    VFNMADD213SD,
    VFNMADD231PS,
    VFNMADD231PD,
    VFNMADD231SS,
    VFNMADD231SD,
    VFNMSUB132PS,
    VFNMSUB132PD,
    VFNMSUB132SS,
    VFNMSUB132SD,
    VFNMSUB213PS,
    VFNMSUB213PD,
    VFNMSUB213SS,
    VFNMSUB213SD,
    VFNMSUB231PS,
    VFNMSUB231PD,
    VFNMSUB231SS,
    VFNMSUB231SD,

    // === BMI/BMI2 ===
    ANDN,
    BEXTR,
    BLSI,
    BLSMSK,
    BLSR,
    BZHI,
    MULX,
    PDEP,
    PEXT,
    RORX,
    SARX,
    SHLX,
    SHRX,
    TZCNT,
    LZCNT,

    // === ADX ===
    ADCX,
    ADOX,

    // === SHA ===
    SHA1RNDS4,
    SHA1NEXTE,
    SHA1MSG1,
    SHA1MSG2,
    SHA256RNDS2,
    SHA256MSG1,
    SHA256MSG2,

    // === AES ===
    AESENC,
    AESENCLAST,
    AESDEC,
    AESDECLAST,
    AESKEYGENASSIST,
    AESIMC,

    // === RDRAND/RDSEED ===
    RDRAND,
    RDSEED,

    // === AVX-512 Foundation ===
    VPADDD_Z,
    VPADDQ_Z,
    VPSUBD_Z,
    VPSUBQ_Z,
    VPMULLD_Z,
    VPMULLQ_Z,
    VPANDD_Z,
    VPANDQ_Z,
    VPORD_Z,
    VPORQ_Z,
    VPXORD_Z,
    VPXORQ_Z,
    VPSLLVD_Z,
    VPSRLVD_Z,
    VPSRAVD_Z,
    VPERMD_Z,
    VPERMQ_Z,
    VPERMPS_Z,
    VPERMPD_Z,
    VCOMPRESSPS_Z,
    VCOMPRESSPD_Z,
    VEXPANDPS_Z,
    VEXPANDPD_Z,
    VPBROADCASTD_Z,
    VPBROADCASTQ_Z,
    VPBROADCASTSS_Z,
    VPBROADCASTSD_Z,
    VMOVDQU8_Z,
    VMOVDQU16_Z,
    VMOVDQU32_Z,
    VMOVDQU64_Z,
    VPCMPEQD_Z,
    VPCMPEQQ_Z,
    VPCMPGTD_Z,
    VPCMPGTQ_Z,
    KAND,
    KANDN,
    KNOT,
    KOR,
    KXNOR,
    KXOR,
    KADD,
    KSHIFTL,
    KSHIFTR,
    KTEST,
    KMOV,
    KUNPCK,
    VADDPD_Z,
    VADDPS_Z,
    VMULPD_Z,
    VMULPS_Z,
    VADDSD_Z,
    VADDSS_Z,
    VMULSD_Z,
    VMULSS_Z,
    VFMADD132PD_Z,
    VFMADD213PD_Z,
    VFMADD231PD_Z,
    VFMADD132PS_Z,
    VFMADD213PS_Z,
    VFMADD231PS_Z,
    VALIGND_Z,
    VALIGNQ_Z,
    VDBPSADBW_Z,
    VPABSQ_Z,
    VPABSQ,
    VPMADD52LUQ_Z,
    VPMADD52HUQ_Z,

    // === AMX (Advanced Matrix Extensions) ===
    TILELOADD,
    TILESTORED,
    TILERELEASE,
    TILEZERO,
    TDPBSSD,
    TDPBSUD,
    TDPBUSD,
    TDPBUUD,
    TDPBF16PS,
    TDPFP16PS,
    TCMMIMFP16PS,
    TCMMRLFP16PS,

    // === CET (Control-flow Enforcement) ===
    ENDBR32,
    ENDBR64,
    INCSSP,
    RDSSP,
    SETSSBSY,
    CLRSSBSY,
    WRSS,
    WRUSS,

    // === Cache and Prefetch ===
    CLDEMOTE,
    CLFLUSH,
    CLFLUSHOPT,
    CLWB,
    PREFETCH,
    PREFETCHW,
    PREFETCHWT1,

    // === RDPID, FS/GS Base ===
    RDPID,
    RDFSBASE,
    RDGSBASE,
    WRFSBASE,
    WRGSBASE,

    // === PTWRITE ===
    PTWRITE,

    // === WAITPKG ===
    UMONITOR,
    UMWAIT,
    TPAUSE,

    // === SERIALIZE ===
    SERIALIZE,

    // ========================================================================
    // Extended AVX-512 — remaining forms
    // ========================================================================
    VPERMB_Z,
    VPERMI2B_Z,
    VPERMT2B_Z,
    VPCOMPRESSB_Z,
    VPCOMPRESSW_Z,
    VPEXPANDB_Z,
    VPEXPANDW_Z,
    VPCONFLICTD_Z,
    VPCONFLICTQ_Z,
    VPLZCNTD_Z,
    VPLZCNTQ_Z,
    VPOPCNTB_Z,
    VPOPCNTW_Z,
    VPOPCNTD_Z,
    VPOPCNTQ_Z,
    VGETMANTPS_Z,
    VGETMANTPD_Z,
    VGETMANTSS_Z,
    VGETMANTSD_Z,
    VGETEXPPS_Z,
    VGETEXPPD_Z,
    VGETEXPSS_Z,
    VGETEXPSD_Z,
    VRNDSCALEPS_Z,
    VRNDSCALEPD_Z,
    VRNDSCALESS_Z,
    VRNDSCALESD_Z,
    VREDUCEPS_Z,
    VREDUCEPD_Z,
    VREDUCESS_Z,
    VREDUCESD_Z,
    VRANGEPS_Z,
    VRANGEPD_Z,
    VRANGESS_Z,
    VRANGESD_Z,
    VFIXUPIMMPS_Z,
    VFIXUPIMMPD_Z,
    VFIXUPIMMSS_Z,
    VFIXUPIMMSD_Z,
    VSCALEFPS_Z,
    VSCALEFPD_Z,
    VSCALEFSS_Z,
    VSCALEFSD_Z,
    VFPCLASSPS_Z,
    VFPCLASSPD_Z,
    VFPCLASSSS_Z,
    VFPCLASSSD_Z,
    VDBPSADBW_Z_512,
    KADDW_Z,
    KANDB_Z,
    KANDW_Z,
    KANDNB_Z,
    KANDNW_Z,
    KNOTB_Z,
    KNOTW_Z,
    KORB_Z,
    KORW_Z,
    KXNORB_Z,
    KXNORW_Z,
    KXORB_Z,
    KXORW_Z,
    KORTESTB_Z,
    KORTESTW_Z,
    KTESTB_Z,
    KTESTW_Z,
    KUNPCKBW_Z,
    KUNPCKWD_Z,
    VCVTNE2PS2BF16_Z,
    VCVTNEPS2BF16_Z,
    VDPBF16PS_Z,
    VADDPH_Z,
    VADDSH_Z,
    VSUBPH_Z,
    VSUBSH_Z,
    VMULPH_Z,
    VMULSH_Z,
    VDIVPH_Z,
    VDIVSH_Z,
    VFMADD132PH_Z,
    VFMADD213PH_Z,
    VFMADD231PH_Z,
    VFMSUB132PH_Z,
    VFMSUB213PH_Z,
    VFMSUB231PH_Z,
    VFNMADD132PH_Z,
    VFNMADD213PH_Z,
    VFNMADD231PH_Z,
    VFNMSUB132PH_Z,
    VFNMSUB213PH_Z,
    VFNMSUB231PH_Z,
    VMAXPH_Z,
    VMAXSH_Z,
    VMINPH_Z,
    VMINSH_Z,
    VSQRTPH_Z,
    VSQRTSH_Z,
    VCVTPH2W_Z,
    VCVTPH2UW_Z,
    VCVTPH2DQ_Z,
    VCVTPH2UDQ_Z,
    VCVTPH2QQ_Z,
    VCVTPH2UQQ_Z,
    VCVTW2PH_Z,
    VCVTUW2PH_Z,
    VCVTDQ2PH_Z,
    VCVTUDQ2PH_Z,
    VCVTQQ2PH_Z,
    VCVTUQQ2PH_Z,
    VCVTPH2PSX_Z,
    VCVTPS2PHX_Z,
    VCVTPH2PD_Z,
    VCVTPD2PH_Z,
    VFPCLASSPH_Z,
    VGETMANTPH_Z,
    VGETEXPPH_Z,
    VRNDSCALEPH_Z,
    VREDUCEPH_Z,
    VRANGEPH_Z,
    VSCALEFPH_Z,
    VPCOMPRESSB_256,
    VPCOMPRESSW_256,
    VPEXPANDB_256,
    VPEXPANDW_256,
    VPSHLDVW,
    VPSHLDVD,
    VPSHLDVQ,
    VPSHRDVW,
    VPSHRDVD,
    VPSHRDVQ,
    VGF2P8AFFINEINVQB_Z,
    VGF2P8AFFINEQB_Z,
    VGF2P8MULB_Z,
    VAESDEC_Z,
    VAESDECLAST_Z,
    VAESENC_Z,
    VAESENCLAST_Z,
    VPCLMULQDQ_Z,
    ENQCMD,
    ENQCMDS,
    MOVDIRI,
    MOVDIR64B,
    PCONFIG,
    CLUI,
    STUI,
    TESTUI,
    SENDUIP,
    UIRET,
    XBEGIN,
    XEND,
    XABORT,
    XTEST,
    LOADIWKEY,
    AESENC128KL,
    AESDEC128KL,
    AESENC256KL,
    AESDEC256KL,
    AESENCWIDE128KL,
    AESDECWIDE128KL,
    AESENCWIDE256KL,
    AESDECWIDE256KL,
    ENCODEKEY128,
    ENCODEKEY256,
    HRESET,
    URDMSR,
    UWRMSR,

    // === Additional CET (Control-flow Enforcement Technology) ===
    RDSSPD,
    RDSSPQ,
    INCSSPD,
    INCSSPQ,
    RSTORSSP,
    SAVEPREVSSP,
    WRSSD,
    WRSSQ,
    WRUSSD,
    WRUSSQ,

    // === AVX-VNNI-INT8 (extended) ===
    VPDPBSUD,
    VPDPBSUDS,
    VPDPBUUD,
    VPDPBUUDS,

    // === AVX-512 VP2INTERSECT ===
    VP2INTERSECTD,
    VP2INTERSECTQ,

    // === AVX-512 FP16 ===
    VADDPH,
    VMULPH,
    VDIVPH,
    VSUBPH,
    VMINPH,
    VMAXPH,
    VSQRTPH,

    // === AVX-512 BF16 ===
    VCVTNE2PS2BF16,
    VDPBF16PS,
    VCVTNEEBF162PS,
    VCVTNEEPH2PS,

    // === AMX Config (extra) ===
    LDTILECFG,
    STTILECFG,
    TILECONFIG,

    // === FRED (Flexible Return) ===
    ERETS,
    ERETU,
    LKGS,

    // === CMPCCXADD ===
    CMPCCXADD,

    // === RAO-INT (Remote Atomic) ===
    AADD,
    AAND,
    AOR,
    AXOR,

    // === MSR Non-Serializing ===
    WRMSRNS,
    RDMSRLIST,
    WRMSRLIST,
}

impl X86FullOpcode {
    /// Convert to a raw numeric discriminant.
    pub fn as_u32(self) -> u32 {
        self as u32
    }

    /// Return the AT&T mnemonic for this opcode.
    pub fn mnemonic(self) -> &'static str {
        FULL_OPCODE_MNEMONICS[self.as_u32() as usize - 400]
    }

    /// Return the Intel mnemonic for this opcode.
    pub fn intel_mnemonic(self) -> &'static str {
        FULL_OPCODE_INTEL_MNEMONICS[self.as_u32() as usize - 400]
    }

    /// Return the number of explicit operands for this opcode.
    pub fn num_operands(self) -> u8 {
        FULL_OPCODE_NUM_OPERANDS[self.as_u32() as usize - 400]
    }

    /// Return this instruction's encoding form.
    pub fn encoding_form(self) -> EncodingForm {
        FULL_OPCODE_ENCODING_FORMS[self.as_u32() as usize - 400]
    }

    /// Return true if this is a CMOVcc variant.
    pub fn is_cmov(self) -> bool {
        matches!(
            self,
            X86FullOpcode::CMOVO
                | X86FullOpcode::CMOVNO
                | X86FullOpcode::CMOVB_FULL
                | X86FullOpcode::CMOVAE_FULL
                | X86FullOpcode::CMOVE_FULL
                | X86FullOpcode::CMOVNE_FULL
                | X86FullOpcode::CMOVBE_FULL
                | X86FullOpcode::CMOVA_FULL
                | X86FullOpcode::CMOVS_FULL
                | X86FullOpcode::CMOVNS_FULL
                | X86FullOpcode::CMOVP_FULL
                | X86FullOpcode::CMOVNP_FULL
                | X86FullOpcode::CMOVL_FULL
                | X86FullOpcode::CMOVGE_FULL
                | X86FullOpcode::CMOVLE_FULL
                | X86FullOpcode::CMOVG_FULL
        )
    }

    /// Return true if this is a Jcc variant.
    pub fn is_jcc(self) -> bool {
        matches!(
            self,
            X86FullOpcode::JO
                | X86FullOpcode::JNO
                | X86FullOpcode::JB_FULL
                | X86FullOpcode::JAE_FULL
                | X86FullOpcode::JE_FULL
                | X86FullOpcode::JNE_FULL
                | X86FullOpcode::JBE_FULL
                | X86FullOpcode::JA_FULL
                | X86FullOpcode::JS_FULL
                | X86FullOpcode::JNS_FULL
                | X86FullOpcode::JP_FULL
                | X86FullOpcode::JNP_FULL
                | X86FullOpcode::JL_FULL
                | X86FullOpcode::JGE_FULL
                | X86FullOpcode::JLE_FULL
                | X86FullOpcode::JG_FULL
        )
    }

    /// Return true if this is a SETcc variant.
    pub fn is_setcc(self) -> bool {
        matches!(
            self,
            X86FullOpcode::SETO
                | X86FullOpcode::SETNO
                | X86FullOpcode::SETB
                | X86FullOpcode::SETAE
                | X86FullOpcode::SETE
                | X86FullOpcode::SETNE
                | X86FullOpcode::SETBE
                | X86FullOpcode::SETA
                | X86FullOpcode::SETS
                | X86FullOpcode::SETNS
                | X86FullOpcode::SETP
                | X86FullOpcode::SETNP
                | X86FullOpcode::SETL
                | X86FullOpcode::SETGE
                | X86FullOpcode::SETLE
                | X86FullOpcode::SETG
        )
    }

    /// Return true if this instruction uses VEX encoding.
    pub fn is_vex(self) -> bool {
        matches!(
            self.encoding_form(),
            EncodingForm::VEX | EncodingForm::VEX3Byte
        )
    }

    /// Return true if this instruction uses EVEX encoding.
    pub fn is_evex(self) -> bool {
        matches!(self.encoding_form(), EncodingForm::EVEX)
    }

    /// Return true if this instruction uses legacy encoding (no prefix or REX only).
    pub fn is_legacy(self) -> bool {
        matches!(
            self.encoding_form(),
            EncodingForm::Legacy | EncodingForm::LegacyREX
        )
    }

    /// Return the base opcode byte (primary opcode, not including ModR/M reg field).
    pub fn base_opcode(self) -> u8 {
        FULL_OPCODE_BASE_BYTES[self.as_u32() as usize - 400]
    }

    /// Return the opcode map (0=1-byte, 1=0F, 2=0F38, 3=0F3A).
    pub fn opcode_map(self) -> u8 {
        FULL_OPCODE_MAPS[self.as_u32() as usize - 400]
    }

    /// Return the mandatory prefix for SSE/AVX instructions (0=none, 1=66, 2=F3, 3=F2).
    pub fn mandatory_prefix(self) -> u8 {
        FULL_OPCODE_MANDATORY_PREFIX[self.as_u32() as usize - 400]
    }

    /// Return true if ModR/M byte is required.
    pub fn requires_modrm(self) -> bool {
        FULL_OPCODE_REQUIRES_MODRM[self.as_u32() as usize - 400]
    }

    /// Return the ModR/M reg/opcode extension value for group operations.
    pub fn modrm_extension(self) -> u8 {
        FULL_OPCODE_MODRM_EXT[self.as_u32() as usize - 400]
    }
}

// ============================================================================
// EncodingForm — instruction encoding format classification
// ============================================================================

/// What encoding form an instruction uses.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum EncodingForm {
    /// Legacy 1/2-byte opcode, possibly with REX prefix in 64-bit mode.
    Legacy,
    /// Legacy encoding that always requires a REX prefix in 64-bit mode
    /// (e.g., instructions accessing R8-R15 or requiring REX.W).
    LegacyREX,
    /// 2-byte VEX prefix encoding (AVX, 128/256-bit).
    VEX,
    /// 3-byte VEX prefix encoding (AVX, 3-operand instructions).
    VEX3Byte,
    /// 3-byte XOP prefix encoding (AMD XOP instructions).
    XOP,
    /// 4-byte EVEX prefix encoding (AVX-512).
    EVEX,
    /// No encoding — pseudo or prefix-only instruction.
    None,
}

// ============================================================================
// InstrEncodingInfo — per-instruction encoding metadata
// ============================================================================

/// Complete encoding information for a single X86 instruction.
#[derive(Debug, Clone)]
pub struct InstrEncodingInfo {
    /// The full opcode.
    pub opcode: X86FullOpcode,
    /// AT&T syntax mnemonic.
    pub mnemonic: &'static str,
    /// Intel syntax mnemonic.
    pub intel_mnemonic: &'static str,
    /// Number of explicit operands.
    pub num_operands: u8,
    /// Encoding form used by this instruction.
    pub encoding_form: EncodingForm,
    /// Base opcode byte (not including ModR/M reg field for group ops).
    pub base_opcode: u8,
    /// Opcode map: 0=1-byte, 1=0F prefix, 2=0F38, 3=0F3A.
    pub opcode_map: u8,
    /// Mandatory prefix: 0=none, 1=66, 2=F3, 3=F2.
    pub mandatory_prefix: u8,
    /// Whether ModR/M byte is emitted.
    pub requires_modrm: bool,
    /// For group operations: the ModR/M reg/opcode extension value (0-7, 255=none).
    pub modrm_extension: u8,
    /// Operand type signature.
    pub operand_types: &'static [OperandType],
    /// True if instruction is a terminator (branch, return, etc.).
    pub is_terminator: bool,
    /// True if instruction is a conditional or unconditional branch.
    pub is_branch: bool,
    /// True if instruction is a call.
    pub is_call: bool,
    /// True if instruction is a return.
    pub is_return: bool,
    /// True if instruction compares values (sets flags).
    pub is_compare: bool,
    /// True if instruction moves immediate to register.
    pub is_move_immediate: bool,
    /// True if instruction converts between types.
    pub is_convert: bool,
    /// True if instruction may have side effects beyond operands.
    pub has_side_effects: bool,
    /// True if instruction may read from memory.
    pub may_load: bool,
    /// True if instruction may write to memory.
    pub may_store: bool,
    /// True if instruction is commutative.
    pub is_commutative: bool,
    /// True if instruction uses 3-address form.
    pub is_three_address: bool,
}

// ============================================================================
// Static lookup tables — ~722 entries (one per X86FullOpcode variant)
// ============================================================================

// Import variant names for use in constant array initializers below.
// Note: EncodingForm::None shadows Option::None, so we import specific variants.
use EncodingForm::{Legacy, LegacyREX, VEX3Byte, EVEX, VEX};

// AT&T mnemonics
pub(crate) const FULL_OPCODE_MNEMONICS: &[&str] = &[
    // MOV variants (400-415)
    "mov",
    "mov",
    "mov",
    "mov",
    "mov",
    "movsd",
    "movss",
    "movaps",
    "movups",
    "movdqa",
    "movdqu",
    "movzx",
    "movsxd",
    "movbe",
    "movd",
    "movq",
    "cmovno",
    "cmovb",
    "cmovae",
    "cmove",
    "cmovne",
    "cmovbe",
    "cmova",
    "cmovs",
    "cmovns",
    "cmovp",
    "cmovnp",
    "cmovl",
    "cmovge",
    "cmovle",
    "cmovg",
    "bswap",
    "cmpxchg",
    "cmpxchg8b",
    "cmpxchg16b",
    "pusha",
    "popa",
    "cwd",
    "cdq",
    "cqo",
    "cbw",
    "cwde",
    "cdqe",
    "adc",
    "sub",
    "sbb",
    "mul",
    "imul",
    "div",
    "idiv",
    "inc",
    "dec",
    "neg",
    "cmp",
    "cmpxchg",
    "xadd",
    "aaa",
    "aas",
    "aam",
    "aad",
    "daa",
    "das",
    "or",
    "xor",
    "not",
    "test",
    "shr",
    "sar",
    "rol",
    "ror",
    "rcl",
    "rcr",
    "shld",
    "shrd",
    "cmps",
    "scas",
    "lods",
    "stos",
    "rep",
    "repe",
    "repne",
    "repz",
    "repnz",
    "jo",
    "jno",
    "jb",
    "jae",
    "je",
    "jne",
    "jbe",
    "ja",
    "js",
    "jns",
    "jp",
    "jnp",
    "jl",
    "jge",
    "jle",
    "jg",
    "loop",
    "loope",
    "loopne",
    "call",
    "ret",
    "iret",
    "int",
    "into",
    "bound",
    "enter",
    "leave",
    "clc",
    "cmc",
    "std",
    "cld",
    "sti",
    "cli",
    "lahf",
    "sahf",
    "pushf",
    "popf",
    "setno",
    "setb",
    "setae",
    "sete",
    "setne",
    "setbe",
    "seta",
    "sets",
    "setns",
    "setp",
    "setnp",
    "setl",
    "setge",
    "setle",
    "setg",
    "out",
    "ins",
    "outs",
    "hlt",
    "wait",
    "lock",
    "lgdt",
    "sgdt",
    "lidt",
    "sidt",
    "lldt",
    "sldt",
    "ltr",
    "str",
    "lmsw",
    "smsw",
    "invlpg",
    "invd",
    "wbinvd",
    "rdmsr",
    "wrmsr",
    "rdtsc",
    "rdtscp",
    "rdpmc",
    "cpuid",
    "syscall",
    "sysret",
    "sysenter",
    "sysexit",
    "fst",
    "fstp",
    "fild",
    "fist",
    "fistp",
    "fbld",
    "fbstp",
    "fadd",
    "fsub",
    "fmul",
    "fdiv",
    "fabs",
    "fchs",
    "fsqrt",
    "fprem",
    "fprem1",
    "fcom",
    "fcomp",
    "fcompp",
    "fucom",
    "fucomp",
    "fucompp",
    "ftst",
    "fxam",
    "fsin",
    "fcos",
    "fsincos",
    "fptan",
    "fpatan",
    "f2xm1",
    "fyl2x",
    "fyl2xp1",
    "fldz",
    "fld1",
    "fldpi",
    "fldl2t",
    "fldl2e",
    "fldlg2",
    "fldln2",
    "fnclex",
    "fndisi",
    "fneni",
    "fninit",
    "fnstsw",
    "fnstcw",
    "fldcw",
    "fstcw",
    "fstsw",
    "ffree",
    "fdecstp",
    "fincstp",
    "fxch",
    "movq",
    "packsswb",
    "packssdw",
    "packuswb",
    "paddb",
    "paddw",
    "paddd",
    "paddsb",
    "paddsw",
    "paddusb",
    "paddusw",
    "psubb",
    "psubw",
    "psubd",
    "psubsb",
    "psubsw",
    "psubusb",
    "psubusw",
    "pmullw",
    "pmulhw",
    "pmaddwd",
    "pcmpeqb",
    "pcmpeqw",
    "pcmpeqd",
    "pcmpgtb",
    "pcmpgtw",
    "pcmpgtd",
    "pand",
    "pandn",
    "por",
    "pxor",
    "psllw",
    "pslld",
    "psllq",
    "psrlw",
    "psrld",
    "psrlq",
    "psraw",
    "psrad",
    "punpckhbw",
    "punpckhwd",
    "punpckhdq",
    "punpcklbw",
    "punpcklwd",
    "punpckldq",
    "addss",
    "subps",
    "subss",
    "mulps",
    "mulss",
    "divps",
    "divss",
    "rcpps",
    "rcpss",
    "sqrtps",
    "sqrtss",
    "rsqrtps",
    "rsqrtss",
    "maxps",
    "maxss",
    "minps",
    "minss",
    "andps",
    "andnps",
    "orps",
    "xorps",
    "cmpps",
    "cmpss",
    "shufps",
    "unpckhps",
    "unpcklps",
    "movmskps",
    "movhlps",
    "movlhps",
    "movlps",
    "movhps",
    "addsd",
    "subpd",
    "subsd",
    "mulpd",
    "mulsd",
    "divpd",
    "divsd",
    "sqrtpd",
    "sqrtsd",
    "maxpd",
    "maxsd",
    "minpd",
    "minsd",
    "andpd",
    "andnpd",
    "orpd",
    "xorpd",
    "cmppd",
    "cmpsd",
    "shufpd",
    "unpckhpd",
    "unpcklpd",
    "movmskpd",
    "movupd",
    "movapd",
    "movlpd",
    "movhpd",
    "cvtdq2pd",
    "cvtdq2ps",
    "cvtpd2dq",
    "cvtpd2ps",
    "cvtps2dq",
    "cvtps2pd",
    "cvtsd2si",
    "cvtsd2ss",
    "cvtsi2sd",
    "cvtsi2ss",
    "cvtss2sd",
    "cvtss2si",
    "cvttpd2dq",
    "cvttps2dq",
    "cvttsd2si",
    "cvttss2si",
    "paddb",
    "paddw",
    "paddd",
    "paddq",
    "psubb",
    "psubw",
    "psubd",
    "psubq",
    "pmuludq",
    "pmullw",
    "pmulhw",
    "pmulhuw",
    "psadbw",
    "pavgb",
    "pavgw",
    "pminub",
    "pminsw",
    "pmaxub",
    "pmaxsw",
    "psllw",
    "pslld",
    "psllq",
    "psrlw",
    "psrld",
    "psrlq",
    "psraw",
    "psrad",
    "maskmovdqu",
    "movq2dq",
    "movdq2q",
    "punpcklbw",
    "punpcklwd",
    "punpckldq",
    "punpcklqdq",
    "punpckhbw",
    "punpckhwd",
    "punpckhdq",
    "punpckhqdq",
    "packsswb",
    "packssdw",
    "packuswb",
    "pand",
    "pandn",
    "por",
    "pxor",
    "pcmpeqb",
    "pcmpeqw",
    "pcmpeqd",
    "addsubpd",
    "haddps",
    "haddpd",
    "hsubps",
    "hsubpd",
    "movsldup",
    "movshdup",
    "movddup",
    "lddqu",
    "fisttp",
    "monitor",
    "mwait",
    "phaddd",
    "phaddsw",
    "phsubw",
    "phsubd",
    "phsubsw",
    "pmaddubsw",
    "pmulhrsw",
    "pshufb",
    "psignb",
    "psignw",
    "psignd",
    "pabsb",
    "pabsw",
    "pabsd",
    "palignr",
    "pshufb",
    "pmuldq",
    "dpps",
    "dppd",
    "blendps",
    "blendpd",
    "blendvps",
    "blendvpd",
    "pminsb",
    "pminsd",
    "pminuw",
    "pminud",
    "pmaxsb",
    "pmaxsd",
    "pmaxuw",
    "pmaxud",
    "packusdw",
    "pcmpeqq",
    "pinsrb",
    "pinsrd",
    "pinsrq",
    "pextrb",
    "pextrd",
    "pextrq",
    "ptest",
    "roundps",
    "roundpd",
    "roundss",
    "roundsd",
    "crc32",
    "extractps",
    "insertps",
    "pmovsxbw",
    "pmovsxbd",
    "pmovsxbq",
    "pmovsxwd",
    "pmovsxwq",
    "pmovsxdq",
    "pmovzxbw",
    "pmovzxbd",
    "pmovzxbq",
    "pmovzxwd",
    "pmovzxwq",
    "pmovzxdq",
    "mpsadbw",
    "phminposuw",
    "pcmpestrm",
    "pcmpistri",
    "pcmpistrm",
    "pcmpgtq",
    "vaddpd",
    "vaddss",
    "vaddsd",
    "vsubps",
    "vsubpd",
    "vsubss",
    "vsubsd",
    "vmulps",
    "vmulpd",
    "vmulss",
    "vmulsd",
    "vdivps",
    "vdivpd",
    "vdivss",
    "vdivsd",
    "vandps",
    "vandnps",
    "vorps",
    "vxorps",
    "vzeroall",
    "vzeroupper",
    "vmovaps",
    "vmovups",
    "vmovapd",
    "vmovupd",
    "vbroadcastss",
    "vbroadcastsd",
    "vbroadcastf128",
    "vpermilps",
    "vpermilpd",
    "vperm2f128",
    "vextractf128",
    "vinsertf128",
    "vcvtph2ps",
    "vcvtps2ph",
    "vpbroadcastw",
    "vpbroadcastd",
    "vpbroadcastq",
    "vpermq",
    "vpermpd",
    "vperm2i128",
    "vpgatherdd",
    "vpgatherdq",
    "vpgatherqd",
    "vpgatherqq",
    "vpmaskmovd",
    "vpmaskmovq",
    "vpsllvd",
    "vpsllvq",
    "vpsrlvd",
    "vpsrlvq",
    "vpsravd",
    "vfmadd132pd",
    "vfmadd132ss",
    "vfmadd132sd",
    "vfmadd213ps",
    "vfmadd213pd",
    "vfmadd213ss",
    "vfmadd213sd",
    "vfmadd231ps",
    "vfmadd231pd",
    "vfmadd231ss",
    "vfmadd231sd",
    "vfmsub132ps",
    "vfmsub132pd",
    "vfmsub132ss",
    "vfmsub132sd",
    "vfmsub213ps",
    "vfmsub213pd",
    "vfmsub213ss",
    "vfmsub213sd",
    "vfmsub231ps",
    "vfmsub231pd",
    "vfmsub231ss",
    "vfmsub231sd",
    "vfnmadd132ps",
    "vfnmadd132pd",
    "vfnmadd132ss",
    "vfnmadd132sd",
    "vfnmadd213ps",
    "vfnmadd213pd",
    "vfnmadd213ss",
    "vfnmadd213sd",
    "vfnmadd231ps",
    "vfnmadd231pd",
    "vfnmadd231ss",
    "vfnmadd231sd",
    "vfnmsub132ps",
    "vfnmsub132pd",
    "vfnmsub132ss",
    "vfnmsub132sd",
    "vfnmsub213ps",
    "vfnmsub213pd",
    "vfnmsub213ss",
    "vfnmsub213sd",
    "vfnmsub231ps",
    "vfnmsub231pd",
    "vfnmsub231ss",
    "vfnmsub231sd",
    "bextr",
    "blsi",
    "blsmsk",
    "blsr",
    "bzhi",
    "mulx",
    "pdep",
    "pext",
    "rorx",
    "sarx",
    "shlx",
    "shrx",
    "tzcnt",
    "lzcnt",
    "adox",
    "sha1nexte",
    "sha1msg1",
    "sha1msg2",
    "sha256rnds2",
    "sha256msg1",
    "sha256msg2",
    "aesenclast",
    "aesdec",
    "aesdeclast",
    "aeskeygenassist",
    "aesimc",
    "rdseed",
    "vpaddq",
    "vpsubd",
    "vpsubq",
    "vpmulld",
    "vpmullq",
    "vpandd",
    "vpandq",
    "vpord",
    "vporq",
    "vpxord",
    "vpxorq",
    "vpsllvd",
    "vpsrlvd",
    "vpsravd",
    "vpermd",
    "vpermq",
    "vpermps",
    "vpermpd",
    "vcompressps",
    "vcompresspd",
    "vexpandps",
    "vexpandpd",
    "vpbroadcastd",
    "vpbroadcastq",
    "vpbroadcastss",
    "vpbroadcastsd",
    "vmovdqu8",
    "vmovdqu16",
    "vmovdqu32",
    "vmovdqu64",
    "vpcmpeqd",
    "vpcmpeqq",
    "vpcmpgtd",
    "vpcmpgtq",
    "kand",
    "kandn",
    "knot",
    "kor",
    "kxnor",
    "kxor",
    "kadd",
    "kshiftl",
    "kshiftr",
    "ktest",
    "kmov",
    "kunpck",
    "vaddpd",
    "vaddps",
    "vmulpd",
    "vmulps",
    "vaddsd",
    "vaddss",
    "vmulsd",
    "vmulss",
    "vfmadd132pd",
    "vfmadd213pd",
    "vfmadd231pd",
    "vfmadd132ps",
    "vfmadd213ps",
    "vfmadd231ps",
    "valignd",
    "valignq",
    "vdbpsadbw",
    "vpabsq",
    "vpabsq",
    "vpmadd52luq",
    "vpmadd52huq",
    "tilestored",
    "tilerelease",
    "tilezero",
    "tdpbssd",
    "tdpbsud",
    "tdpbusd",
    "tdpbuud",
    "tdpbf16ps",
    "tdpfp16ps",
    "tcmmimfp16ps",
    "tcmmrlfp16ps",
    "endbr64",
    "incssp",
    "rdssp",
    "setssbsy",
    "clrssbsy",
    "wrss",
    "wruss",
    "clflush",
    "clflushopt",
    "clwb",
    "prefetch",
    "prefetchw",
    "prefetchwt1",
    "rdfsbase",
    "rdgsbase",
    "wrfsbase",
    "wrgsbase",
    "umwait",
    "tpause",
    "vpermi2b",
    "vpermt2b",
    "vpcompressb",
    "vpcompressw",
    "vpexpandb",
    "vpexpandw",
    "vpconflictd",
    "vpconflictq",
    "vplzcntd",
    "vplzcntq",
    "vpopcntb",
    "vpopcntw",
    "vpopcntd",
    "vpopcntq",
    "vgetmantps",
    "vgetmantpd",
    "vgetmantss",
    "vgetmantsd",
    "vgetexpps",
    "vgetexppd",
    "vgetexpss",
    "vgetexpsd",
    "vrndscaleps",
    "vrndscalepd",
    "vrndscaless",
    "vrndscalesd",
    "vreduceps",
    "vreducepd",
    "vreducess",
    "vreducesd",
    "vrangeps",
    "vrangepd",
    "vrangess",
    "vrangesd",
    "vfixupimmps",
    "vfixupimmpd",
    "vfixupimmss",
    "vfixupimmsd",
    "vscalefps",
    "vscalefpd",
    "vscalefss",
    "vscalefsd",
    "vfclassps",
    "vfclasspd",
    "vfclassss",
    "vfclasssd",
    "vdbpsadbw",
    "kaddw",
    "kandb",
    "kandw",
    "kandnb",
    "kandnw",
    "knotb",
    "knotw",
    "korb",
    "korw",
    "kxnorb",
    "kxnorw",
    "kxorb",
    "kxorw",
    "kortestb",
    "kortestw",
    "ktestb",
    "ktestw",
    "kunpckbw",
    "kunpckwd",
    "vcvtne2ps2bf16",
    "vcvtneps2bf16",
    "vdpbf16ps",
    "vaddph",
    "vaddsh",
    "vsubph",
    "vsubsh",
    "vmulph",
    "vmulsh",
    "vdivph",
    "vdivsh",
    "vfmadd132ph",
    "vfmadd213ph",
    "vfmadd231ph",
    "vfmsub132ph",
    "vfmsub213ph",
    "vfmsub231ph",
    "vfnmadd132ph",
    "vfnmadd213ph",
    "vfnmadd231ph",
    "vfnmsub132ph",
    "vfnmsub213ph",
    "vfnmsub231ph",
    "vmaxph",
    "vmaxsh",
    "vminph",
    "vminsh",
    "vsqrtph",
    "vsqrtsh",
    "vcvtph2w",
    "vcvtph2uw",
    "vcvtph2dq",
    "vcvtph2udq",
    "vcvtph2qq",
    "vcvtph2uqq",
    "vcvtw2ph",
    "vcvtuw2ph",
    "vcvtdq2ph",
    "vcvtudq2ph",
    "vcvtqq2ph",
    "vcvtuqq2ph",
    "vcvtph2psx",
    "vcvtps2phx",
    "vcvtph2pd",
    "vcvtpd2ph",
    "vfclassph",
    "vgetmantph",
    "vgetexpph",
    "vrndscaleph",
    "vreduceph",
    "vrangeph",
    "vscalefph",
    "vpcompressb",
    "vpcompressw",
    "vpexpandb",
    "vpexpandw",
    "vpshldvw",
    "vpshldvd",
    "vpshldvq",
    "vpshrdvw",
    "vpshrdvd",
    "vpshrdvq",
    "vgf2p8affineinvqb",
    "vgf2p8affineqb",
    "vgf2p8mulb",
    "vaesdec",
    "vaesdeclast",
    "vaesenc",
    "vaesenclast",
    "vpclmulqdq",
    "enqcmds",
    "movdiri",
    "movdir64b",
    "stui",
    "testui",
    "senduip",
    "uiret",
    "xend",
    "xabort",
    "xtest",
    "aesenc128kl",
    "aesdec128kl",
    "aesenc256kl",
    "aesdec256kl",
    "aesencwide128kl",
    "aesdecwide128kl",
    "aesencwide256kl",
    "aesdecwide256kl",
    "encodekey128",
    "encodekey256",
    "urdmsr",
    "uwrmsr",
    "vpshufbitqmb",
    "vpcompressd",
    "vpcompressq",
    "vpexpandd",
    "vpexpandq",
    "vpdpbusd",
    "vpdpbusds",
    "vpdpwssd",
    "vpdpwssds",
    "vpdpbssd",
    "vpdpbssds",
    "vpdpbsdd",
    "vpdpbsds",
    "vbcstnebf162ps",
    "vbcstnesh2ps",
    "vcvtneebf162ps",
    "vcvtneeph2ps",
    "vcvtneobf162ps",
    "vcvtneoph2ps",
    "vcvtneps2bf16",
    "cmpbexadd",
    "cmpbxadd",
    "cmplexadd",
    "cmplxadd",
    "cmpnexadd",
    "cmpnpxadd",
    "cmpnoxadd",
    "cmpoxadd",
    "cmppxadd",
    "cmpsxadd",
    "cmpzxadd",
    "cmpnaexadd",
    "prefetchit0",
    "prefetchit1",
    "aadd",
    "aand",
    "aor",
    "axor",
    "wrmsrns",
    "rdmsrlist",
    "wrmsrlist",
    // === CET (Control-flow Enforcement Technology) ===
    "endbr32",
    "endbr64",
    "rdsspd",
    "rdsspq",
    "incsspd",
    "incsspq",
    "rstorssp",
    "saveprevssp",
    "setssbsy",
    "clrssbsy",
    "wrssd",
    "wrssq",
    "wrussd",
    "wrussq",
    // === Key Locker (KL) ===
    "loadiwkey",
    "aesenc128kl",
    "aesdec128kl",
    "aesenc256kl",
    "aesdec256kl",
    "aesencwide128kl",
    "aesdecwide128kl",
    "aesencwide256kl",
    "aesdecwide256kl",
    "encodekey128",
    "encodekey256",
    // === HRESET ===
    "hreset",
];

// Intel mnemonics (same as AT&T for most, different for some)
pub(crate) const FULL_OPCODE_INTEL_MNEMONICS: &[&str] = &[
    // MOV variants (400-415)
    "mov",
    "mov",
    "mov",
    "mov",
    "mov",
    "movsd",
    "movss",
    "movaps",
    "movups",
    "movdqa",
    "movdqu",
    "movzx",
    "movsxd",
    "movbe",
    "movd",
    "movq",
    "cmovno",
    "cmovb",
    "cmovae",
    "cmove",
    "cmovne",
    "cmovbe",
    "cmova",
    "cmovs",
    "cmovns",
    "cmovp",
    "cmovnp",
    "cmovl",
    "cmovge",
    "cmovle",
    "cmovg",
    "bswap",
    "cmpxchg",
    "cmpxchg8b",
    "cmpxchg16b",
    "pusha",
    "popa",
    "cwd",
    "cdq",
    "cqo",
    "cbw",
    "cwde",
    "cdqe",
    "adc",
    "sub",
    "sbb",
    "mul",
    "imul",
    "div",
    "idiv",
    "inc",
    "dec",
    "neg",
    "cmp",
    "cmpxchg",
    "xadd",
    "aaa",
    "aas",
    "aam",
    "aad",
    "daa",
    "das",
    "or",
    "xor",
    "not",
    "test",
    "shr",
    "sar",
    "rol",
    "ror",
    "rcl",
    "rcr",
    "shld",
    "shrd",
    "cmps",
    "scas",
    "lods",
    "stos",
    "rep",
    "repe",
    "repne",
    "repz",
    "repnz",
    "jo",
    "jno",
    "jb",
    "jae",
    "je",
    "jne",
    "jbe",
    "ja",
    "js",
    "jns",
    "jp",
    "jnp",
    "jl",
    "jge",
    "jle",
    "jg",
    "loop",
    "loope",
    "loopne",
    "call",
    "ret",
    "iret",
    "int",
    "into",
    "bound",
    "enter",
    "leave",
    "clc",
    "cmc",
    "std",
    "cld",
    "sti",
    "cli",
    "lahf",
    "sahf",
    "pushf",
    "popf",
    "setno",
    "setb",
    "setae",
    "sete",
    "setne",
    "setbe",
    "seta",
    "sets",
    "setns",
    "setp",
    "setnp",
    "setl",
    "setge",
    "setle",
    "setg",
    "out",
    "ins",
    "outs",
    "hlt",
    "wait",
    "lock",
    "lgdt",
    "sgdt",
    "lidt",
    "sidt",
    "lldt",
    "sldt",
    "ltr",
    "str",
    "lmsw",
    "smsw",
    "invlpg",
    "invd",
    "wbinvd",
    "rdmsr",
    "wrmsr",
    "rdtsc",
    "rdtscp",
    "rdpmc",
    "cpuid",
    "syscall",
    "sysret",
    "sysenter",
    "sysexit",
    "fst",
    "fstp",
    "fild",
    "fist",
    "fistp",
    "fbld",
    "fbstp",
    "fadd",
    "fsub",
    "fmul",
    "fdiv",
    "fabs",
    "fchs",
    "fsqrt",
    "fprem",
    "fprem1",
    "fcom",
    "fcomp",
    "fcompp",
    "fucom",
    "fucomp",
    "fucompp",
    "ftst",
    "fxam",
    "fsin",
    "fcos",
    "fsincos",
    "fptan",
    "fpatan",
    "f2xm1",
    "fyl2x",
    "fyl2xp1",
    "fldz",
    "fld1",
    "fldpi",
    "fldl2t",
    "fldl2e",
    "fldlg2",
    "fldln2",
    "fnclex",
    "fndisi",
    "fneni",
    "fninit",
    "fnstsw",
    "fnstcw",
    "fldcw",
    "fstcw",
    "fstsw",
    "ffree",
    "fdecstp",
    "fincstp",
    "fxch",
    "movq",
    "packsswb",
    "packssdw",
    "packuswb",
    "paddb",
    "paddw",
    "paddd",
    "paddsb",
    "paddsw",
    "paddusb",
    "paddusw",
    "psubb",
    "psubw",
    "psubd",
    "psubsb",
    "psubsw",
    "psubusb",
    "psubusw",
    "pmullw",
    "pmulhw",
    "pmaddwd",
    "pcmpeqb",
    "pcmpeqw",
    "pcmpeqd",
    "pcmpgtb",
    "pcmpgtw",
    "pcmpgtd",
    "pand",
    "pandn",
    "por",
    "pxor",
    "psllw",
    "pslld",
    "psllq",
    "psrlw",
    "psrld",
    "psrlq",
    "psraw",
    "psrad",
    "punpckhbw",
    "punpckhwd",
    "punpckhdq",
    "punpcklbw",
    "punpcklwd",
    "punpckldq",
    "addss",
    "subps",
    "subss",
    "mulps",
    "mulss",
    "divps",
    "divss",
    "rcpps",
    "rcpss",
    "sqrtps",
    "sqrtss",
    "rsqrtps",
    "rsqrtss",
    "maxps",
    "maxss",
    "minps",
    "minss",
    "andps",
    "andnps",
    "orps",
    "xorps",
    "cmpps",
    "cmpss",
    "shufps",
    "unpckhps",
    "unpcklps",
    "movmskps",
    "movhlps",
    "movlhps",
    "movlps",
    "movhps",
    "addsd",
    "subpd",
    "subsd",
    "mulpd",
    "mulsd",
    "divpd",
    "divsd",
    "sqrtpd",
    "sqrtsd",
    "maxpd",
    "maxsd",
    "minpd",
    "minsd",
    "andpd",
    "andnpd",
    "orpd",
    "xorpd",
    "cmppd",
    "cmpsd",
    "shufpd",
    "unpckhpd",
    "unpcklpd",
    "movmskpd",
    "movupd",
    "movapd",
    "movlpd",
    "movhpd",
    "cvtdq2pd",
    "cvtdq2ps",
    "cvtpd2dq",
    "cvtpd2ps",
    "cvtps2dq",
    "cvtps2pd",
    "cvtsd2si",
    "cvtsd2ss",
    "cvtsi2sd",
    "cvtsi2ss",
    "cvtss2sd",
    "cvtss2si",
    "cvttpd2dq",
    "cvttps2dq",
    "cvttsd2si",
    "cvttss2si",
    "paddb",
    "paddw",
    "paddd",
    "paddq",
    "psubb",
    "psubw",
    "psubd",
    "psubq",
    "pmuludq",
    "pmullw",
    "pmulhw",
    "pmulhuw",
    "psadbw",
    "pavgb",
    "pavgw",
    "pminub",
    "pminsw",
    "pmaxub",
    "pmaxsw",
    "psllw",
    "pslld",
    "psllq",
    "psrlw",
    "psrld",
    "psrlq",
    "psraw",
    "psrad",
    "maskmovdqu",
    "movq2dq",
    "movdq2q",
    "punpcklbw",
    "punpcklwd",
    "punpckldq",
    "punpcklqdq",
    "punpckhbw",
    "punpckhwd",
    "punpckhdq",
    "punpckhqdq",
    "packsswb",
    "packssdw",
    "packuswb",
    "pand",
    "pandn",
    "por",
    "pxor",
    "pcmpeqb",
    "pcmpeqw",
    "pcmpeqd",
    "addsubpd",
    "haddps",
    "haddpd",
    "hsubps",
    "hsubpd",
    "movsldup",
    "movshdup",
    "movddup",
    "lddqu",
    "fisttp",
    "monitor",
    "mwait",
    "phaddd",
    "phaddsw",
    "phsubw",
    "phsubd",
    "phsubsw",
    "pmaddubsw",
    "pmulhrsw",
    "pshufb",
    "psignb",
    "psignw",
    "psignd",
    "pabsb",
    "pabsw",
    "pabsd",
    "palignr",
    "pshufb",
    "pmuldq",
    "dpps",
    "dppd",
    "blendps",
    "blendpd",
    "blendvps",
    "blendvpd",
    "pminsb",
    "pminsd",
    "pminuw",
    "pminud",
    "pmaxsb",
    "pmaxsd",
    "pmaxuw",
    "pmaxud",
    "packusdw",
    "pcmpeqq",
    "pinsrb",
    "pinsrd",
    "pinsrq",
    "pextrb",
    "pextrd",
    "pextrq",
    "ptest",
    "roundps",
    "roundpd",
    "roundss",
    "roundsd",
    "crc32",
    "extractps",
    "insertps",
    "pmovsxbw",
    "pmovsxbd",
    "pmovsxbq",
    "pmovsxwd",
    "pmovsxwq",
    "pmovsxdq",
    "pmovzxbw",
    "pmovzxbd",
    "pmovzxbq",
    "pmovzxwd",
    "pmovzxwq",
    "pmovzxdq",
    "mpsadbw",
    "phminposuw",
    "pcmpestrm",
    "pcmpistri",
    "pcmpistrm",
    "pcmpgtq",
    "vaddpd",
    "vaddss",
    "vaddsd",
    "vsubps",
    "vsubpd",
    "vsubss",
    "vsubsd",
    "vmulps",
    "vmulpd",
    "vmulss",
    "vmulsd",
    "vdivps",
    "vdivpd",
    "vdivss",
    "vdivsd",
    "vandps",
    "vandnps",
    "vorps",
    "vxorps",
    "vzeroall",
    "vzeroupper",
    "vmovaps",
    "vmovups",
    "vmovapd",
    "vmovupd",
    "vbroadcastss",
    "vbroadcastsd",
    "vbroadcastf128",
    "vpermilps",
    "vpermilpd",
    "vperm2f128",
    "vextractf128",
    "vinsertf128",
    "vcvtph2ps",
    "vcvtps2ph",
    "vpbroadcastw",
    "vpbroadcastd",
    "vpbroadcastq",
    "vpermq",
    "vpermpd",
    "vperm2i128",
    "vpgatherdd",
    "vpgatherdq",
    "vpgatherqd",
    "vpgatherqq",
    "vpmaskmovd",
    "vpmaskmovq",
    "vpsllvd",
    "vpsllvq",
    "vpsrlvd",
    "vpsrlvq",
    "vpsravd",
    "vfmadd132pd",
    "vfmadd132ss",
    "vfmadd132sd",
    "vfmadd213ps",
    "vfmadd213pd",
    "vfmadd213ss",
    "vfmadd213sd",
    "vfmadd231ps",
    "vfmadd231pd",
    "vfmadd231ss",
    "vfmadd231sd",
    "vfmsub132ps",
    "vfmsub132pd",
    "vfmsub132ss",
    "vfmsub132sd",
    "vfmsub213ps",
    "vfmsub213pd",
    "vfmsub213ss",
    "vfmsub213sd",
    "vfmsub231ps",
    "vfmsub231pd",
    "vfmsub231ss",
    "vfmsub231sd",
    "vfnmadd132ps",
    "vfnmadd132pd",
    "vfnmadd132ss",
    "vfnmadd132sd",
    "vfnmadd213ps",
    "vfnmadd213pd",
    "vfnmadd213ss",
    "vfnmadd213sd",
    "vfnmadd231ps",
    "vfnmadd231pd",
    "vfnmadd231ss",
    "vfnmadd231sd",
    "vfnmsub132ps",
    "vfnmsub132pd",
    "vfnmsub132ss",
    "vfnmsub132sd",
    "vfnmsub213ps",
    "vfnmsub213pd",
    "vfnmsub213ss",
    "vfnmsub213sd",
    "vfnmsub231ps",
    "vfnmsub231pd",
    "vfnmsub231ss",
    "vfnmsub231sd",
    "bextr",
    "blsi",
    "blsmsk",
    "blsr",
    "bzhi",
    "mulx",
    "pdep",
    "pext",
    "rorx",
    "sarx",
    "shlx",
    "shrx",
    "tzcnt",
    "lzcnt",
    "adox",
    "sha1nexte",
    "sha1msg1",
    "sha1msg2",
    "sha256rnds2",
    "sha256msg1",
    "sha256msg2",
    "aesenclast",
    "aesdec",
    "aesdeclast",
    "aeskeygenassist",
    "aesimc",
    "rdseed",
    "vpaddq",
    "vpsubd",
    "vpsubq",
    "vpmulld",
    "vpmullq",
    "vpandd",
    "vpandq",
    "vpord",
    "vporq",
    "vpxord",
    "vpxorq",
    "vpsllvd",
    "vpsrlvd",
    "vpsravd",
    "vpermd",
    "vpermq",
    "vpermps",
    "vpermpd",
    "vcompressps",
    "vcompresspd",
    "vexpandps",
    "vexpandpd",
    "vpbroadcastd",
    "vpbroadcastq",
    "vpbroadcastss",
    "vpbroadcastsd",
    "vmovdqu8",
    "vmovdqu16",
    "vmovdqu32",
    "vmovdqu64",
    "vpcmpeqd",
    "vpcmpeqq",
    "vpcmpgtd",
    "vpcmpgtq",
    "kand",
    "kandn",
    "knot",
    "kor",
    "kxnor",
    "kxor",
    "kadd",
    "kshiftl",
    "kshiftr",
    "ktest",
    "kmov",
    "kunpck",
    "vaddpd",
    "vaddps",
    "vmulpd",
    "vmulps",
    "vaddsd",
    "vaddss",
    "vmulsd",
    "vmulss",
    "vfmadd132pd",
    "vfmadd213pd",
    "vfmadd231pd",
    "vfmadd132ps",
    "vfmadd213ps",
    "vfmadd231ps",
    "valignd",
    "valignq",
    "vdbpsadbw",
    "vpabsq",
    "vpabsq",
    "vpmadd52luq",
    "vpmadd52huq",
    "tilestored",
    "tilerelease",
    "tilezero",
    "tdpbssd",
    "tdpbsud",
    "tdpbusd",
    "tdpbuud",
    "tdpbf16ps",
    "tdpfp16ps",
    "tcmmimfp16ps",
    "tcmmrlfp16ps",
    "endbr64",
    "incssp",
    "rdssp",
    "setssbsy",
    "clrssbsy",
    "wrss",
    "wruss",
    "clflush",
    "clflushopt",
    "clwb",
    "prefetch",
    "prefetchw",
    "prefetchwt1",
    "rdfsbase",
    "rdgsbase",
    "wrfsbase",
    "wrgsbase",
    "umwait",
    "tpause",
    "vpermi2b",
    "vpermt2b",
    "vpcompressb",
    "vpcompressw",
    "vpexpandb",
    "vpexpandw",
    "vpconflictd",
    "vpconflictq",
    "vplzcntd",
    "vplzcntq",
    "vpopcntb",
    "vpopcntw",
    "vpopcntd",
    "vpopcntq",
    "vgetmantps",
    "vgetmantpd",
    "vgetmantss",
    "vgetmantsd",
    "vgetexpps",
    "vgetexppd",
    "vgetexpss",
    "vgetexpsd",
    "vrndscaleps",
    "vrndscalepd",
    "vrndscaless",
    "vrndscalesd",
    "vreduceps",
    "vreducepd",
    "vreducess",
    "vreducesd",
    "vrangeps",
    "vrangepd",
    "vrangess",
    "vrangesd",
    "vfixupimmps",
    "vfixupimmpd",
    "vfixupimmss",
    "vfixupimmsd",
    "vscalefps",
    "vscalefpd",
    "vscalefss",
    "vscalefsd",
    "vfclassps",
    "vfclasspd",
    "vfclassss",
    "vfclasssd",
    "vdbpsadbw",
    "kaddw",
    "kandb",
    "kandw",
    "kandnb",
    "kandnw",
    "knotb",
    "knotw",
    "korb",
    "korw",
    "kxnorb",
    "kxnorw",
    "kxorb",
    "kxorw",
    "kortestb",
    "kortestw",
    "ktestb",
    "ktestw",
    "kunpckbw",
    "kunpckwd",
    "vcvtne2ps2bf16",
    "vcvtneps2bf16",
    "vdpbf16ps",
    "vaddph",
    "vaddsh",
    "vsubph",
    "vsubsh",
    "vmulph",
    "vmulsh",
    "vdivph",
    "vdivsh",
    "vfmadd132ph",
    "vfmadd213ph",
    "vfmadd231ph",
    "vfmsub132ph",
    "vfmsub213ph",
    "vfmsub231ph",
    "vfnmadd132ph",
    "vfnmadd213ph",
    "vfnmadd231ph",
    "vfnmsub132ph",
    "vfnmsub213ph",
    "vfnmsub231ph",
    "vmaxph",
    "vmaxsh",
    "vminph",
    "vminsh",
    "vsqrtph",
    "vsqrtsh",
    "vcvtph2w",
    "vcvtph2uw",
    "vcvtph2dq",
    "vcvtph2udq",
    "vcvtph2qq",
    "vcvtph2uqq",
    "vcvtw2ph",
    "vcvtuw2ph",
    "vcvtdq2ph",
    "vcvtudq2ph",
    "vcvtqq2ph",
    "vcvtuqq2ph",
    "vcvtph2psx",
    "vcvtps2phx",
    "vcvtph2pd",
    "vcvtpd2ph",
    "vfclassph",
    "vgetmantph",
    "vgetexpph",
    "vrndscaleph",
    "vreduceph",
    "vrangeph",
    "vscalefph",
    "vpcompressb",
    "vpcompressw",
    "vpexpandb",
    "vpexpandw",
    "vpshldvw",
    "vpshldvd",
    "vpshldvq",
    "vpshrdvw",
    "vpshrdvd",
    "vpshrdvq",
    "vgf2p8affineinvqb",
    "vgf2p8affineqb",
    "vgf2p8mulb",
    "vaesdec",
    "vaesdeclast",
    "vaesenc",
    "vaesenclast",
    "vpclmulqdq",
    "enqcmds",
    "movdiri",
    "movdir64b",
    "stui",
    "testui",
    "senduip",
    "uiret",
    "xend",
    "xabort",
    "xtest",
    "aesenc128kl",
    "aesdec128kl",
    "aesenc256kl",
    "aesdec256kl",
    "aesencwide128kl",
    "aesdecwide128kl",
    "aesencwide256kl",
    "aesdecwide256kl",
    "encodekey128",
    "encodekey256",
    "urdmsr",
    "uwrmsr",
    "VPSHUFBITQMB",
    "VPCOMPRESSD",
    "VPCOMPRESSQ",
    "VPEXPANDD",
    "VPEXPANDQ",
    "VPDPBUSD",
    "VPDPBUSDS",
    "VPDPWSSD",
    "VPDPWSSDS",
    "VPDPBSSD",
    "VPDPBSSDS",
    "VPDPBSDD",
    "VPDPBSDS",
    "VBCSTNEBF162PS",
    "VBCSTNESH2PS",
    "VCVTNEEBF162PS",
    "VCVTNEEPH2PS",
    "VCVTNEOBF162PS",
    "VCVTNEOPH2PS",
    "VCVTNEPS2BF16",
    "CMPBEXADD",
    "CMPBXADD",
    "CMPLEXADD",
    "CMPLXADD",
    "CMPNEXADD",
    "CMPNPXADD",
    "CMPNOXADD",
    "CMPOXADD",
    "CMPPXADD",
    "CMPSXADD",
    "CMPZXADD",
    "CMPNAEXADD",
    "PREFETCHIT0",
    "PREFETCHIT1",
    "AADD",
    "AAND",
    "AOR",
    "AXOR",
    "WRMSRNS",
    "RDMSRLIST",
    "WRMSRLIST",
];

// Number of explicit operands
const FULL_OPCODE_NUM_OPERANDS: &[u8] = &[
    // MOV variants (400-415)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    // CMOVcc (420-435) — all have 2 operands (dst, src)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // Data Transfer misc (436-448)
    2, 1, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, // Arithmetic (450-469)
    2, 2, 2, 2, 1, 2, 1, 1, 1, 1, 1, 2, 2, 2, 0, 0, 0, 0, 0, 0, // Logical (470-474)
    2, 2, 2, 1, 2, // Shifts/Rotates (475-483)
    2, 2, 2, 2, 2, 2, 2, 3, 3, // String Ops (484-493)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // Control Transfer (494-521)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 2, 1,
    // Flag Ops (522-532)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SETcc (533-548)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // System (549-578)
    2, 2, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // FPU x87 (579-631)
    1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // MMX (632-677)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // SSE (678-709)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2,
    // SSE2 (710-801)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, // SSE3 (802-814)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, // SSSE3 (815-831)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 2, // SSE4.1 (832-877)
    2, 2, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // SSE4.2 (878-882)
    3, 3, 3, 3, 2, // AVX (883-918)
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, // AVX2 (919-936)
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // FMA (937-984)
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // BMI/BMI2 (985-999)
    2, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // ADX (1000-1001)
    2, 2, // SHA (1002-1008)
    3, 2, 2, 2, 3, 2, 2, // AES (1009-1014)
    2, 2, 2, 2, 2, 2, // RDRAND/RDSEED (1015-1016)
    1, 1, // AVX-512 Foundation (1017-1084)
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, // AMX (1085-1096)
    1, 1, 0, 1, 3, 3, 3, 3, 3, 3, 3, 3, // CET (1097-1104)
    0, 0, 0, 1, 0, 0, 2, 2, // Cache/Prefetch (1105-1111)
    1, 1, 1, 1, 1, 1, 1, // RDPID/FSGS (1112-1116)
    1, 1, 1, 1, 1, // PTWRITE (1117)
    1, // WAITPKG (1118-1120)
    2, 2, 2, // SERIALIZE (1121)
    0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
];

// Encoding forms
const FULL_OPCODE_ENCODING_FORMS: &[EncodingForm] = &[
    // MOV variants (400-415) — legacy
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    Legacy,
    Legacy,
    Legacy,
    LegacyREX,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    EncodingForm::None,
    EncodingForm::None,
    EncodingForm::None,
    EncodingForm::None,
    EncodingForm::None,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    EncodingForm::None,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX,
    VEX,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    VEX3Byte,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    Legacy,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    EVEX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    LegacyREX,
    Legacy,
    Legacy,
    LegacyREX,
    LegacyREX,
    LegacyREX,
];

// Base opcode bytes
const FULL_OPCODE_BASE_BYTES: &[u8] = &[
    // MOV variants (400-415)
    0x89, 0x8B, 0x89, 0xB8, 0xC7, 0x10, 0xF3, 0x0F, 0x28, 0x0F, 0x10, 0x6F, 0x7F, 0x0F, 0xB6, 0x0F,
    0xBE, 0x63, 0x0F, 0x38, 0xF0, 0x6E, 0x7E, 0x6E, 0x7E, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
    0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x0F, 0xC8, 0x0F, 0xB0, 0xC7, 0x0F, 0xC7, 0x60,
    0x61, 0x99, 0x99, 0x99, 0x98, 0x98, 0x98, 0x11, 0x29, 0x19, 0xF7, 0xF7, 0xF7, 0xF7, 0xFF, 0xFF,
    0xF7, 0x39, 0x0F, 0xB0, 0x0F, 0xC0, 0x37, 0x3F, 0xD4, 0xD5, 0x27, 0x2F, 0x09, 0x31, 0xF7, 0x85,
    0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0x0F, 0xA4, 0x0F, 0xAC, 0xA6, 0xAE, 0xAC, 0xAA, 0xF3, 0xF3,
    0xF2, 0xF3, 0xF2, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C,
    0x7D, 0x7E, 0x7F, 0xE2, 0xE1, 0xE0, 0xE8, 0xC3, 0xCF, 0xCD, 0xCE, 0x62, 0xC8, 0xC9, 0xF8, 0xF5,
    0xFD, 0xFC, 0xFB, 0xFA, 0x9F, 0x9E, 0x9C, 0x9D, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
    0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, 0xE6, 0x6C, 0x6E, 0xF4, 0x9B, 0xF0, 0x0F, 0x01, 0x0F,
    0x01, 0x0F, 0x01, 0x0F, 0x01, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x01, 0x0F,
    0x01, 0x0F, 0x01, 0x0F, 0x08, 0x0F, 0x09, 0x0F, 0x32, 0x0F, 0x30, 0x0F, 0x31, 0x01, 0xF9, 0x0F,
    0x01, 0x33, 0x0F, 0xA2, 0x0F, 0x05, 0x0F, 0x07, 0x0F, 0x34, 0x0F, 0x35, 0xD9, 0xD9, 0xDB, 0xDB,
    0xDB, 0xDF, 0xDF, 0xD8, 0xD8, 0xD8, 0xD8, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD8, 0xD8, 0xDE, 0xDD,
    0xDD, 0xDE, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
    0xD9, 0xD9, 0xD9, 0xDB, 0xDB, 0xDB, 0xDB, 0xDD, 0xD9, 0xD9, 0xD9, 0xDD, 0xDD, 0xD9, 0xD9, 0x6F,
    0x63, 0x6B, 0x67, 0xFC, 0xFD, 0xFE, 0xEC, 0xED, 0xDC, 0xDD, 0xF8, 0xF9, 0xFA, 0xE8, 0xE9, 0xD8,
    0xD9, 0xD5, 0xE5, 0xF5, 0x74, 0x75, 0x76, 0x64, 0x65, 0x66, 0xDB, 0xDF, 0xEB, 0xEF, 0xF1, 0xF2,
    0xF3, 0xD1, 0xD2, 0xD3, 0xE1, 0xE2, 0x68, 0x69, 0x6A, 0x60, 0x61, 0x62, 0xF3, 0x0F, 0x58, 0x5C,
    0xF3, 0x0F, 0x5C, 0x59, 0xF3, 0x0F, 0x59, 0x5E, 0xF3, 0x0F, 0x5E, 0x53, 0xF3, 0x0F, 0x53, 0x51,
    0xF3, 0x0F, 0x51, 0x52, 0xF3, 0x0F, 0x52, 0x5F, 0xF3, 0x0F, 0x5F, 0x5D, 0xF3, 0x0F, 0x5D, 0x54,
    0x55, 0x56, 0x57, 0xC2, 0xF3, 0x0F, 0xC2, 0xC6, 0x15, 0x14, 0x50, 0x12, 0x16, 0x12, 0x16, 0xF2,
    0x0F, 0x58, 0x5C, 0xF2, 0x0F, 0x5C, 0x59, 0xF2, 0x0F, 0x59, 0x5E, 0xF2, 0x0F, 0x5E, 0x51, 0xF2,
    0x0F, 0x51, 0x5F, 0xF2, 0x0F, 0x5F, 0x5D, 0xF2, 0x0F, 0x5D, 0x54, 0x55, 0x56, 0x57, 0xC2, 0xF2,
    0x0F, 0xC2, 0xC6, 0x15, 0x14, 0x50, 0x10, 0x28, 0x12, 0x16, 0xE6, 0x5B, 0xE6, 0x5A, 0x5B, 0x5A,
    0xF2, 0x0F, 0x2D, 0xF2, 0x0F, 0x5A, 0xF2, 0x0F, 0x2A, 0xF3, 0x0F, 0x2A, 0xF3, 0x0F, 0x5A, 0xF2,
    0x0F, 0x2C, 0xE6, 0xE6, 0xF2, 0x0F, 0x2C, 0xF3, 0x0F, 0x2C, 0xFC, 0xFD, 0xFE, 0xD4, 0xF8, 0xF9,
    0xFA, 0xFB, 0xF4, 0xD5, 0xE5, 0xE4, 0xF6, 0xE0, 0xE3, 0xDA, 0xEA, 0xDE, 0xEE, 0xF1, 0xF2, 0xF3,
    0xD1, 0xD2, 0xD3, 0xE1, 0xE2, 0xF7, 0xD6, 0xD6, 0x60, 0x61, 0x62, 0x6C, 0x68, 0x69, 0x6A, 0x6D,
    0x63, 0x6B, 0x67, 0xDB, 0xDF, 0xEB, 0x74, 0x75, 0x76, 0xD0, 0x7C, 0x7C, 0x7D, 0x7D, 0x12, 0x16,
    0x12, 0xF0, 0xDB, 0x0F, 0x01, 0xC8, 0x0F, 0x01, 0xC9, 0x02, 0x03, 0x05, 0x06, 0x07, 0x04, 0x0B,
    0x00, 0x08, 0x09, 0x0A, 0x1C, 0x1D, 0x1E, 0x0F, 0x00, 0x28, 0x40, 0x41, 0x0C, 0x0D, 0x14, 0x15,
    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x2E, 0x2F, 0x2B, 0x29, 0x20, 0x22, 0x22, 0x14, 0x16, 0x16,
    0x17, 0x08, 0x09, 0x0A, 0x0B, 0x38, 0xF0, 0x10, 0x17, 0x21, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25,
    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x42, 0x41, 0x60, 0x62, 0x62, 0x37, 0x58, 0x58, 0x58, 0x5C,
    0x5C, 0x5C, 0x5C, 0x59, 0x59, 0x59, 0x59, 0x5E, 0x5E, 0x5E, 0x5E, 0x54, 0x55, 0x56, 0x57, 0x77,
    0x77, 0x28, 0x10, 0x28, 0x10, 0x18, 0x19, 0x1A, 0x0C, 0x0D, 0x16, 0x19, 0x18, 0x13, 0x1D, 0x79,
    0x58, 0x59, 0x36, 0x16, 0x46, 0x90, 0x90, 0x90, 0x90, 0x8C, 0x8E, 0x47, 0x47, 0x45, 0x45, 0x46,
    0x98, 0x99, 0x99, 0xA8, 0xA8, 0xA9, 0xA9, 0xB8, 0xB8, 0xB9, 0xB9, 0x9A, 0x9A, 0x9B, 0x9B, 0xAA,
    0xAA, 0xAB, 0xAB, 0xBA, 0xBA, 0xBB, 0xBB, 0x9C, 0x9C, 0x9D, 0x9D, 0xAC, 0xAC, 0xAD, 0xAD, 0xBC,
    0xBC, 0xBD, 0xBD, 0x9E, 0x9E, 0x9F, 0x9F, 0xAE, 0xAE, 0xAF, 0xAF, 0xBE, 0xBE, 0xBF, 0xBF, 0xF7,
    0xF3, 0xF3, 0xF3, 0xF5, 0xF6, 0xF5, 0xF5, 0xF2, 0xF7, 0xF7, 0xF7, 0xF3, 0xF3, 0xF6, 0xC8, 0xC9,
    0xCA, 0xCB, 0xCD, 0xCE, 0xDD, 0xDE, 0xDF, 0xDF, 0xDB, 0xC7, 0xD4, 0xFA, 0xFB, 0x40, 0x40, 0xDB,
    0xDB, 0xEB, 0xEB, 0xEF, 0xEF, 0x47, 0x45, 0x47, 0x45, 0x36, 0x36, 0x1D, 0x1D, 0x8A, 0x8A, 0x88,
    0x88, 0x8A, 0x8A, 0x88, 0x88, 0x58, 0x58, 0x7C, 0x58, 0x18, 0x18, 0x6F, 0x6F, 0x7F, 0x7F, 0x7E,
    0x7E, 0x6E, 0x6E, 0x76, 0x29, 0x75, 0x37, 0x41, 0x42, 0x44, 0x45, 0x46, 0x47, 0x4A, 0x4A, 0x33,
    0x4A, 0x4B, 0x4B, 0x58, 0x58, 0x59, 0x59, 0x58, 0x58, 0x59, 0x59, 0x98, 0xA8, 0xB8, 0x98, 0xA8,
    0xB8, 0x03, 0x03, 0x42, 0x42, 0x1E, 0x1F, 0xB4, 0xB5, 0xB4, 0xB5, 0x4B, 0x49, 0x49, 0x5E, 0x5F,
    0x5E, 0x5F, 0x5C, 0x5C, 0x6C, 0x6C, 0x1E, 0x01, 0x1E, 0x01, 0x01, 0x01, 0x01, 0xAE, 0xAE, 0xAE,
    0x0D, 0x0D, 0x0D, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0xAE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
];

// Opcode maps
const FULL_OPCODE_MAPS: &[u8] = &[
    // MOV variants (400-415) — mix of 1-byte and 2-byte
    0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    // CMOVcc (420-435) — all use 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // Data Transfer misc (436-448)
    0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, // Arithmetic (450-469)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, // Logical (470-474)
    0, 0, 0, 0, 0, // Shifts/Rotates (475-483) — some have 0F prefix group
    0, 0, 0, 0, 0, 0, 0, 1, 1, // String Ops (484-493)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // Control Transfer (494-521)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // Flag Ops (522-532)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SETcc (533-548) — 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // System (549-578)
    0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1,
    // FPU x87 (579-631) — mostly 1-byte
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // MMX (632-677) — 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // SSE (678-709) — 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    // SSE2 (710-801) — 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, // SSE3 (802-814) — 0F prefix
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // SSSE3 (815-831) — 0F38/0F3A prefix
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 2, // SSE4.1 (832-877) — 0F38 prefix
    2, 2, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // SSE4.2 (878-882) — 0F38 prefix
    2, 2, 2, 2, 2, // AVX (883-918) — VEX (map 1)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3,
    3, 3, 2, 3, // AVX2 (919-936) — VEX (map 2/3)
    2, 2, 2, 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // FMA (937-984) — VEX (map 2)
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // BMI/BMI2 (985-999)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, // ADX (1000-1001)
    1, 1, // SHA (1002-1008) — 0F38
    2, 2, 2, 2, 2, 2, 2, // AES (1009-1014) — 0F38
    2, 2, 2, 2, 2, 2, // RDRAND/RDSEED (1015-1016)
    1, 1, // AVX-512 Foundation (1017-1084) — EVEX
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // AMX (1085-1096)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, // CET (1097-1104)
    0, 0, 0, 0, 0, 0, 0, 0, // Cache/Prefetch (1105-1111)
    1, 1, 1, 0, 0, 0, 0, // RDPID/FSGS (1112-1116)
    1, 1, 1, 1, 1, // PTWRITE (1117)
    1, // WAITPKG (1118-1120)
    1, 1, 1, // SERIALIZE (1121)
    1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
];

// Mandatory prefix (0=none, 1=66, 2=F3, 3=F2)
const FULL_OPCODE_MANDATORY_PREFIX: &[u8] = &[
    // MOV variants (400-415)
    0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CMOVcc (420-435)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // Data Transfer misc (436-448)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // Arithmetic (450-469)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // Logical (470-474)
    0, 0, 0, 0, 0, // Shifts/Rotates (475-483)
    0, 0, 0, 0, 0, 0, 0, 0, 0, // String Ops (484-493)
    0, 0, 0, 0, 0, 1, 1, 2, 1, 2, // Control Transfer (494-521)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // Flag Ops (522-532)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SETcc (533-548)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // System (549-578)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // FPU x87 (579-631)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // MMX (632-677)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SSE (678-709)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    // SSE2 (710-801)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, // SSE3 (802-814)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SSSE3 (815-831)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SSE4.1 (832-877)
    0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // SSE4.2 (878-882)
    0, 0, 0, 0, 0, // AVX (883-918) — VEX pp field (0=none, 1=66, 2=F3, 3=F2)
    0, 1, 2, 3, 0, 1, 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 1, 1, 1, 1, 1, 1,
    1, 1, 2, 2, // AVX2 (919-936) — VEX
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // FMA (937-984) — VEX pp=1(66)
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // BMI/BMI2 (985-999)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // ADX (1000-1001)
    0, 0, // SHA (1002-1008)
    0, 0, 0, 0, 0, 0, 0, // AES (1009-1014)
    0, 0, 0, 0, 0, 0, // RDRAND/RDSEED (1015-1016)
    0, 0, // AVX-512 Foundation (1017-1084) — EVEX
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // AMX (1085-1096)
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // CET (1097-1104)
    0, 0, 0, 0, 0, 0, 0, 0, // Cache/Prefetch (1105-1111)
    0, 0, 0, 0, 0, 0, 0, // RDPID/FSGS (1112-1116)
    0, 0, 0, 0, 0, // PTWRITE (1117)
    0, // WAITPKG (1118-1120)
    0, 0, 0, // SERIALIZE (1121)
    0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
    1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
];

// Whether ModR/M is required
const FULL_OPCODE_REQUIRES_MODRM: &[bool] = &[
    // MOV variants (400-415) — most need ModR/M, MOVri depending on form
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // CMOVcc (420-435) — true
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // Data Transfer misc (436-448)
    true, true, true, true, true, false, false, false, false, false, false, false, false,
    // Arithmetic (450-469)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, false,
    false, false, false, false, false, // Logical (470-474)
    true, true, true, true, true, // Shifts/Rotates (475-483)
    true, true, true, true, true, true, true, true, true, // String Ops (484-493)
    false, false, false, false, false, false, false, false, false, false,
    // Control Transfer (494-521)
    false, false, false, false, false, false, false, false, false, false, false, false, false,
    false, false, false, false, false, false, false, false, false, false, false, false, false,
    false, false, // Flag Ops (522-532)
    false, false, false, false, false, false, false, false, false, false, false,
    // SETcc (533-548) — true
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // System (549-578)
    true, true, false, false, false, false, false, true, true, true, true, true, true, true, true,
    true, true, true, true, false, false, true, true, true, true, true, true, true, true, true,
    true, // FPU x87 (579-631) — varies
    true, true, true, true, true, true, true, true, true, true, true, true, false, false, false,
    false, false, true, true, true, true, true, true, false, false, false, false, false, false,
    false, false, false, false, false, false, false, false, false, false, false, true, true, true,
    true, false, false, false, false, false, true, true, true, true, // MMX (632-677)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, // SSE (678-709)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // SSE2 (710-801) — all true
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, // SSE3 (802-814)
    true, true, true, true, true, true, true, true, true, true, true, true, true,
    // SSSE3 (815-831) — all true
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, // SSE4.1 (832-877) — all true
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // SSE4.2 (878-882)
    true, true, true, true, true, // AVX (883-918)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, false, false, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, // AVX2 (919-936)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, // FMA (937-984)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // BMI/BMI2 (985-999)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // ADX (1000-1001)
    true, true, // SHA (1002-1008)
    true, true, true, true, true, true, true, // AES (1009-1014)
    true, true, true, true, true, true, // RDRAND/RDSEED (1015-1016)
    true, true, // AVX-512 Foundation (1017-1084)
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    // AMX (1085-1096)
    true, true, true, true, true, true, true, true, true, true, true, true,
    // CET (1097-1104)
    false, false, false, true, false, false, true, true, // Cache/Prefetch (1105-1111)
    true, true, true, true, true, true, true, // RDPID/FSGS (1112-1116)
    true, true, true, true, true, // PTWRITE (1117)
    true, // WAITPKG (1118-1120)
    true, true, true, // SERIALIZE (1121)
    false, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true,
    true, true, true, true, true, true, true, true, true, true, true,
];

// ModR/M reg/opcode extension for group operations (255 = none)
const FULL_OPCODE_MODRM_EXT: &[u8] = &[
    // MOV variants (400-415)
    255, 255, 255, 255, 0, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // CMOVcc (420-435)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // Data Transfer misc (436-448)
    255, 5, 255, 1, 1, 255, 255, 255, 255, 255, 255, 255, 255, // Arithmetic (450-469)
    255, 255, 255, 255, 4, 5, 6, 7, 0, 1, 3, 7, 255, 255, 255, 255, 255, 255, 255, 255,
    // Logical (470-474)
    255, 255, 255, 2, 255, // Shifts/Rotates (475-483)
    4, 5, 7, 0, 1, 2, 3, 255, 255, // String Ops (484-493)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // Control Transfer (494-521)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, // Flag Ops (522-532)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // SETcc (533-548)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // System (549-578)
    255, 255, 255, 255, 255, 255, 255, 2, 2, 3, 3, 2, 2, 3, 3, 6, 6, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, // FPU x87 (579-631)
    0, 2, 3, 0, 2, 3, 4, 6, 0, 4, 1, 6, 255, 255, 255, 255, 255, 2, 3, 3, 4, 5, 5, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, // MMX (632-677)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, // SSE (678-709)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // SSE2 (710-801)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, // SSE3 (802-814)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // SSSE3 (815-831)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // SSE4.1 (832-877)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, // SSE4.2 (878-882)
    255, 255, 255, 255, 255, // AVX (883-918)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // AVX2 (919-936)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // FMA (937-984)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // BMI/BMI2 (985-999)
    255, 255, 3, 2, 1, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    // ADX (1000-1001)
    255, 255, // SHA (1002-1008)
    255, 255, 255, 255, 255, 255, 255, // AES (1009-1014)
    255, 255, 255, 255, 255, 255, // RDRAND/RDSEED (1015-1016)
    6, 7, // AVX-512 Foundation (1017-1084)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, // AMX (1085-1096)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, // CET (1097-1104)
    255, 255, 255, 255, 255, 255, 255, 255, // Cache/Prefetch (1105-1111)
    255, 255, 255, 255, 255, 255, 255, // RDPID/FSGS (1112-1116)
    255, 255, 255, 255, 255, // PTWRITE (1117)
    255, // WAITPKG (1118-1120)
    255, 255, 255, // SERIALIZE (1121)
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
    255, 255, 255, 255, 255,
];

// ============================================================================
// Assert that all arrays are the same length at compile time
// ============================================================================

/// Verify all arrays have consistent length at init time, not compile time.
/// (Discriminants have gaps, so arrays are shorter than the full range.)
#[allow(dead_code)]
fn verify_array_lengths() {
    let len = FULL_OPCODE_MNEMONICS.len();
    assert_eq!(len, FULL_OPCODE_INTEL_MNEMONICS.len());
    assert_eq!(len, FULL_OPCODE_NUM_OPERANDS.len());
    assert_eq!(len, FULL_OPCODE_ENCODING_FORMS.len());
    assert_eq!(len, FULL_OPCODE_BASE_BYTES.len());
    assert_eq!(len, FULL_OPCODE_MAPS.len());
    assert_eq!(len, FULL_OPCODE_MANDATORY_PREFIX.len());
    assert_eq!(len, FULL_OPCODE_REQUIRES_MODRM.len());
    assert_eq!(len, FULL_OPCODE_MODRM_EXT.len());
}

// ============================================================================
// X86FullInstrInfo — complete instruction database for full opcodes
// ============================================================================

/// Master instruction information database for all `X86FullOpcode` variants.
///
/// Provides lookup methods for all instruction properties and supports
/// both forward (opcode → info) and reverse (mnemonic → opcode) queries.
pub struct X86FullInstrInfo {
    /// HashMap from full opcode to encoding info.
    infos: HashMap<X86FullOpcode, InstrEncodingInfo>,
    /// Reverse lookup: AT&T mnemonic → full opcode.
    by_mnemonic: HashMap<String, X86FullOpcode>,
}

impl X86FullInstrInfo {
    /// Construct a new X86FullInstrInfo with all encoding info pre-populated.
    /// This walks all 722 opcode variants from the static lookup tables.
    pub fn new() -> Self {
        let mut info = X86FullInstrInfo {
            infos: HashMap::new(),
            by_mnemonic: HashMap::new(),
        };
        info.init();
        info
    }

    /// Populate from the static tables.
    fn init(&mut self) {
        // Discriminants are now contiguous starting at 400.
        // Each array entry at index i corresponds to discriminant 400 + i.
        let count = FULL_OPCODE_MNEMONICS.len();
        for idx in 0..count {
            let disc = (400 + idx) as u32;
            let opcode: X86FullOpcode = unsafe { std::mem::transmute(disc) };
            let mnemonic = FULL_OPCODE_MNEMONICS[idx];
            let encoding_info = InstrEncodingInfo {
                opcode,
                mnemonic: FULL_OPCODE_MNEMONICS[idx],
                intel_mnemonic: FULL_OPCODE_INTEL_MNEMONICS[idx],
                num_operands: FULL_OPCODE_NUM_OPERANDS[idx],
                encoding_form: FULL_OPCODE_ENCODING_FORMS[idx],
                base_opcode: FULL_OPCODE_BASE_BYTES[idx],
                opcode_map: FULL_OPCODE_MAPS[idx],
                mandatory_prefix: FULL_OPCODE_MANDATORY_PREFIX[idx],
                requires_modrm: FULL_OPCODE_REQUIRES_MODRM[idx],
                modrm_extension: FULL_OPCODE_MODRM_EXT[idx],
                operand_types: &[],
                is_terminator: opcode.is_jcc()
                    || opcode.is_setcc()
                    || matches!(
                        opcode,
                        X86FullOpcode::JMP
                            | X86FullOpcode::RET
                            | X86FullOpcode::IRET
                            | X86FullOpcode::HLT
                    ),
                is_branch: opcode.is_jcc()
                    || matches!(
                        opcode,
                        X86FullOpcode::JMP | X86FullOpcode::CALL | X86FullOpcode::RET
                    ),
                is_call: matches!(opcode, X86FullOpcode::CALL),
                is_return: matches!(opcode, X86FullOpcode::RET | X86FullOpcode::IRET),
                is_compare: matches!(
                    opcode,
                    X86FullOpcode::CMP
                        | X86FullOpcode::TEST
                        | X86FullOpcode::CMPPS
                        | X86FullOpcode::CMPSS
                        | X86FullOpcode::CMPPD
                        | X86FullOpcode::CMPSD
                        | X86FullOpcode::FTST
                        | X86FullOpcode::FCOM
                        | X86FullOpcode::FCOMP
                        | X86FullOpcode::FCOMPP
                        | X86FullOpcode::FUCOM
                        | X86FullOpcode::FUCOMP
                        | X86FullOpcode::FUCOMPP
                        | X86FullOpcode::FXAM
                        | X86FullOpcode::PTEST
                        | X86FullOpcode::PCMPEQB
                        | X86FullOpcode::PCMPEQW
                        | X86FullOpcode::PCMPEQD
                        | X86FullOpcode::PCMPEQQ
                        | X86FullOpcode::PCMPGTB
                        | X86FullOpcode::PCMPGTW
                        | X86FullOpcode::PCMPGTD
                        | X86FullOpcode::PCMPGTQ
                        | X86FullOpcode::KTEST
                ),
                is_move_immediate: matches!(opcode, X86FullOpcode::MOVri | X86FullOpcode::MOVmi),
                is_convert: matches!(
                    opcode,
                    X86FullOpcode::CVTSD2SI
                        | X86FullOpcode::CVTSD2SS
                        | X86FullOpcode::CVTSI2SD
                        | X86FullOpcode::CVTSI2SS
                        | X86FullOpcode::CVTSS2SD
                        | X86FullOpcode::CVTSS2SI
                        | X86FullOpcode::CVTTSD2SI
                        | X86FullOpcode::CVTTSS2SI
                        | X86FullOpcode::CVTDQ2PD
                        | X86FullOpcode::CVTDQ2PS
                        | X86FullOpcode::CVTPD2DQ
                        | X86FullOpcode::CVTPD2PS
                        | X86FullOpcode::CVTPS2DQ
                        | X86FullOpcode::CVTPS2PD
                        | X86FullOpcode::CVTTPD2DQ
                        | X86FullOpcode::CVTTPS2DQ
                        | X86FullOpcode::CWD
                        | X86FullOpcode::CDQ
                        | X86FullOpcode::CQO
                        | X86FullOpcode::CBW
                        | X86FullOpcode::CWDE
                        | X86FullOpcode::CDQE
                        | X86FullOpcode::MOVSXD
                        | X86FullOpcode::MOVZX
                        | X86FullOpcode::VCVTPH2PS
                        | X86FullOpcode::VCVTPS2PH
                ),
                has_side_effects: matches!(
                    opcode,
                    X86FullOpcode::SYSCALL
                        | X86FullOpcode::SYSENTER
                        | X86FullOpcode::INT
                        | X86FullOpcode::HLT
                        | X86FullOpcode::RDTSC
                        | X86FullOpcode::RDTSCP
                        | X86FullOpcode::RDPMC
                        | X86FullOpcode::CPUID
                        | X86FullOpcode::IN
                        | X86FullOpcode::OUT
                        | X86FullOpcode::WRMSR
                        | X86FullOpcode::INVLPG
                        | X86FullOpcode::STI
                        | X86FullOpcode::CLI
                        | X86FullOpcode::MWAIT
                        | X86FullOpcode::MONITOR
                ),
                may_load: matches!(
                    opcode,
                    X86FullOpcode::MOVrm
                        | X86FullOpcode::MOVZX
                        | X86FullOpcode::MOVSXD
                        | X86FullOpcode::POPA
                        | X86FullOpcode::POPA
                        | X86FullOpcode::POPF
                        | X86FullOpcode::LODS
                        | X86FullOpcode::SCAS
                        | X86FullOpcode::CMPS
                        | X86FullOpcode::IN
                        | X86FullOpcode::FLDCW
                        | X86FullOpcode::FLD
                        | X86FullOpcode::FILD
                        | X86FullOpcode::FBLD
                        | X86FullOpcode::LDDQU
                ) || opcode.mnemonic().starts_with("mov") && (idx >= 1 && idx <= 2),
                may_store: matches!(
                    opcode,
                    X86FullOpcode::MOVmr
                        | X86FullOpcode::MOVmi
                        | X86FullOpcode::PUSHA
                        | X86FullOpcode::PUSHF
                        | X86FullOpcode::STOS
                        | X86FullOpcode::OUT
                        | X86FullOpcode::FST
                        | X86FullOpcode::FSTP
                        | X86FullOpcode::FIST
                        | X86FullOpcode::FISTP
                        | X86FullOpcode::FBSTP
                        | X86FullOpcode::FSTCW
                        | X86FullOpcode::FSTSW
                ),
                is_commutative: matches!(
                    opcode,
                    X86FullOpcode::ADD
                        | X86FullOpcode::ADC
                        | X86FullOpcode::MUL
                        | X86FullOpcode::IMUL
                        | X86FullOpcode::AND
                        | X86FullOpcode::OR
                        | X86FullOpcode::XOR
                        | X86FullOpcode::ADCX
                        | X86FullOpcode::ADOX
                        | X86FullOpcode::FADD
                        | X86FullOpcode::FMUL
                        | X86FullOpcode::ADDPS
                        | X86FullOpcode::ADDSS
                        | X86FullOpcode::MULPS
                        | X86FullOpcode::MULSS
                        | X86FullOpcode::ADDPD
                        | X86FullOpcode::ADDSD
                        | X86FullOpcode::MULPD
                        | X86FullOpcode::MULSD
                        | X86FullOpcode::VADDPS
                        | X86FullOpcode::VADDPD
                        | X86FullOpcode::VMULPS
                        | X86FullOpcode::VMULPD
                        | X86FullOpcode::VFMADD132PS
                        | X86FullOpcode::VFMADD132PD
                ),
                is_three_address: opcode.is_vex()
                    || opcode.is_evex()
                    || matches!(
                        opcode,
                        X86FullOpcode::IMUL | X86FullOpcode::SHLD | X86FullOpcode::SHRD
                    ),
            };
            self.by_mnemonic
                .insert(encoding_info.mnemonic.to_string(), opcode);
            self.infos.insert(opcode, encoding_info);
        }
    }

    /// Look up encoding info by full opcode.
    pub fn get(&self, opcode: X86FullOpcode) -> Option<&InstrEncodingInfo> {
        self.infos.get(&opcode)
    }

    /// Look up a full opcode by AT&T mnemonic.
    pub fn find_by_mnemonic(&self, mnemonic: &str) -> Option<X86FullOpcode> {
        self.by_mnemonic.get(mnemonic).copied()
    }

    /// Return the base opcode byte for the given full opcode.
    pub fn get_base_opcode(&self, opcode: X86FullOpcode) -> u8 {
        self.infos.get(&opcode).map(|i| i.base_opcode).unwrap_or(0)
    }

    /// Return the opcode map for the given full opcode.
    pub fn get_opcode_map(&self, opcode: X86FullOpcode) -> u8 {
        self.infos.get(&opcode).map(|i| i.opcode_map).unwrap_or(0)
    }

    /// Return the mandatory prefix for the given full opcode.
    pub fn get_mandatory_prefix(&self, opcode: X86FullOpcode) -> u8 {
        self.infos
            .get(&opcode)
            .map(|i| i.mandatory_prefix)
            .unwrap_or(0)
    }

    /// Return whether ModR/M is required for the given full opcode.
    pub fn requires_modrm(&self, opcode: X86FullOpcode) -> bool {
        self.infos
            .get(&opcode)
            .map(|i| i.requires_modrm)
            .unwrap_or(false)
    }

    /// Return the ModR/M extension byte for group ops.
    pub fn get_modrm_extension(&self, opcode: X86FullOpcode) -> u8 {
        self.infos
            .get(&opcode)
            .map(|i| i.modrm_extension)
            .unwrap_or(255)
    }

    /// Return the encoding form for the opcode.
    pub fn encoding_form(&self, opcode: X86FullOpcode) -> EncodingForm {
        self.infos
            .get(&opcode)
            .map(|i| i.encoding_form)
            .unwrap_or(EncodingForm::Legacy)
    }

    /// Look up a full opcode by (base_opcode, opcode_map, mandatory_prefix).
    /// This is used by the decoder to map raw bytes to an opcode variant.
    pub fn lookup_by_bytes(
        &self,
        base_opcode: u8,
        opcode_map: u8,
        mandatory_prefix: u8,
    ) -> Option<X86FullOpcode> {
        let count = FULL_OPCODE_MNEMONICS.len();
        for idx in 0..count {
            let disc = (400 + idx) as u32;
            let opcode: X86FullOpcode = unsafe { std::mem::transmute(disc) };
            if let Some(enc) = self.infos.get(&opcode) {
                if enc.opcode_map == opcode_map
                    && enc.base_opcode == base_opcode
                    && enc.mandatory_prefix == mandatory_prefix
                {
                    return Some(opcode);
                }
            }
        }
        Option::None
    }
}

// ============================================================================
// Extension instruction info — ISA additions beyond the base enum
// ============================================================================

/// Descriptor for an extension instruction not yet in the main opcode enum.
/// These cover recent ISA additions: AVX-512 subsets, AMX, AVX-VNNI,
/// AVX-IFMA, AVX-NE-CONVERT, CMPCCXADD, PREFETCHITI, RAO-INT, MSRLIST,
/// SHA512, SM3, SM4, TSXLDTRK, AVX-512 BF16.
pub struct ExtInstrDesc {
    pub mnemonic: &'static str,
    pub intel_mnemonic: &'static str,
    pub num_operands: u8,
    pub encoding_form: EncodingForm,
    pub base_opcode: u8,
    pub opcode_map: u8,
    pub mandatory_prefix: u8,
    pub requires_modrm: bool,
    pub modrm_extension: u8,
    pub is_terminator: bool,
    pub has_side_effects: bool,
    pub may_load: bool,
    pub may_store: bool,
}

impl X86FullInstrInfo {
    /// Return a static table of all extension instructions.
    /// These are recent ISA additions tracked separately from the main opcode enum.
    pub fn get_extension_instructions() -> Vec<ExtInstrDesc> {
        vec![
            // AVX-512 BITALG
            ExtInstrDesc {
                mnemonic: "vpshufbitqmb",
                intel_mnemonic: "VPSHUFBITQMB",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x8F,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AVX-512 VBMI2 — VPCOMPRESS D/Q, VPEXPAND D/Q
            ExtInstrDesc {
                mnemonic: "vpcompressd",
                intel_mnemonic: "VPCOMPRESSD",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x8B,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "vpcompressq",
                intel_mnemonic: "VPCOMPRESSQ",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x8B,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "vpexpandd",
                intel_mnemonic: "VPEXPANDD",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x89,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpexpandq",
                intel_mnemonic: "VPEXPANDQ",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x89,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: false,
            },
            // AVX-VNNI
            ExtInstrDesc {
                mnemonic: "vpdpbusd",
                intel_mnemonic: "VPDPBUSD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x50,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpbusds",
                intel_mnemonic: "VPDPBUSDS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x51,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpwssd",
                intel_mnemonic: "VPDPWSSD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x52,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpwssds",
                intel_mnemonic: "VPDPWSSDS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x53,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpbssd",
                intel_mnemonic: "VPDPBSSD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x50,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpbssds",
                intel_mnemonic: "VPDPBSSDS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x51,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpbsdd",
                intel_mnemonic: "VPDPBSDD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x52,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpdpbsds",
                intel_mnemonic: "VPDPBSDS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x53,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AVX-IFMA
            ExtInstrDesc {
                mnemonic: "vpmadd52luq",
                intel_mnemonic: "VPMADD52LUQ",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB4,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vpmadd52huq",
                intel_mnemonic: "VPMADD52HUQ",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB5,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AVX-NE-CONVERT
            ExtInstrDesc {
                mnemonic: "vbcstnebf162ps",
                intel_mnemonic: "VBCSTNEBF162PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB1,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vbcstnesh2ps",
                intel_mnemonic: "VBCSTNESH2PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB1,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneebf162ps",
                intel_mnemonic: "VCVTNEEBF162PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB2,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneeph2ps",
                intel_mnemonic: "VCVTNEEPH2PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB2,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneobf162ps",
                intel_mnemonic: "VCVTNEOBF162PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB3,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneoph2ps",
                intel_mnemonic: "VCVTNEOPH2PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB3,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneps2bf16",
                intel_mnemonic: "VCVTNEPS2BF16",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x72,
                opcode_map: 3,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // CMPCCXADD (12 condition codes)
            ExtInstrDesc {
                mnemonic: "cmpbexadd",
                intel_mnemonic: "CMPBEXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE0,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpbxadd",
                intel_mnemonic: "CMPBXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE2,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmplexadd",
                intel_mnemonic: "CMPLEXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE4,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmplxadd",
                intel_mnemonic: "CMPLXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE6,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpnexadd",
                intel_mnemonic: "CMPNEXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE8,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpnpxadd",
                intel_mnemonic: "CMPNPXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xEA,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpnoxadd",
                intel_mnemonic: "CMPNOXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xEC,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpoxadd",
                intel_mnemonic: "CMPOXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xEE,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmppxadd",
                intel_mnemonic: "CMPPXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE1,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpsxadd",
                intel_mnemonic: "CMPSXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE3,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpzxadd",
                intel_mnemonic: "CMPZXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE5,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "cmpnaexadd",
                intel_mnemonic: "CMPNAEXADD",
                num_operands: 3,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xE7,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            // PREFETCHITI
            ExtInstrDesc {
                mnemonic: "prefetchit0",
                intel_mnemonic: "PREFETCHIT0",
                num_operands: 1,
                encoding_form: EncodingForm::Legacy,
                base_opcode: 0x18,
                opcode_map: 0,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 7,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "prefetchit1",
                intel_mnemonic: "PREFETCHIT1",
                num_operands: 1,
                encoding_form: EncodingForm::Legacy,
                base_opcode: 0x18,
                opcode_map: 0,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 6,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // RAO-INT
            ExtInstrDesc {
                mnemonic: "aadd",
                intel_mnemonic: "AADD",
                num_operands: 2,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xFC,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "aand",
                intel_mnemonic: "AAND",
                num_operands: 2,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xFC,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "aor",
                intel_mnemonic: "AOR",
                num_operands: 2,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xFC,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "axor",
                intel_mnemonic: "AXOR",
                num_operands: 2,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xFC,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: true,
            },
            // WRMSRNS
            ExtInstrDesc {
                mnemonic: "wrmsrns",
                intel_mnemonic: "WRMSRNS",
                num_operands: 0,
                encoding_form: EncodingForm::Legacy,
                base_opcode: 0x01,
                opcode_map: 0,
                mandatory_prefix: 0,
                requires_modrm: false,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            // MSRLIST
            ExtInstrDesc {
                mnemonic: "rdmsrlist",
                intel_mnemonic: "RDMSRLIST",
                num_operands: 1,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xC6,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "wrmsrlist",
                intel_mnemonic: "WRMSRLIST",
                num_operands: 1,
                encoding_form: EncodingForm::LegacyREX,
                base_opcode: 0xC6,
                opcode_map: 1,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            // SHA512
            ExtInstrDesc {
                mnemonic: "sha512msg1",
                intel_mnemonic: "SHA512MSG1",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xCC,
                opcode_map: 2,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "sha512msg2",
                intel_mnemonic: "SHA512MSG2",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xCD,
                opcode_map: 2,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "sha512rnds2",
                intel_mnemonic: "SHA512RNDS2",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xCB,
                opcode_map: 2,
                mandatory_prefix: 0,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // SM3
            ExtInstrDesc {
                mnemonic: "vsm3msg1",
                intel_mnemonic: "VSM3MSG1",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xDE,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vsm3msg2",
                intel_mnemonic: "VSM3MSG2",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xDF,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vsm3rnds2",
                intel_mnemonic: "VSM3RNDS2",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xDE,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // SM4
            ExtInstrDesc {
                mnemonic: "vsm4key4",
                intel_mnemonic: "VSM4KEY4",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xDA,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vsm4rnds4",
                intel_mnemonic: "VSM4RNDS4",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xDB,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // TSXLDTRK
            ExtInstrDesc {
                mnemonic: "xsusldtrk",
                intel_mnemonic: "XSUSLDTRK",
                num_operands: 0,
                encoding_form: EncodingForm::Legacy,
                base_opcode: 0x5B,
                opcode_map: 0,
                mandatory_prefix: 0,
                requires_modrm: false,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "xresldtrk",
                intel_mnemonic: "XRESLDTRK",
                num_operands: 0,
                encoding_form: EncodingForm::Legacy,
                base_opcode: 0x5C,
                opcode_map: 0,
                mandatory_prefix: 0,
                requires_modrm: false,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            // ================================================================
            // AVX-512 VP2INTERSECT — pair intersection
            // ================================================================
            ExtInstrDesc {
                mnemonic: "vp2intersectd",
                intel_mnemonic: "VP2INTERSECTD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x68,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vp2intersectq",
                intel_mnemonic: "VP2INTERSECTQ",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x68,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // ================================================================
            // AVX-512 FP16 — half-precision floating-point
            // ================================================================
            ExtInstrDesc {
                mnemonic: "vaddph",
                intel_mnemonic: "VADDPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x58,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vmulph",
                intel_mnemonic: "VMULPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x59,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vdivph",
                intel_mnemonic: "VDIVPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5E,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vsubph",
                intel_mnemonic: "VSUBPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5C,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vminph",
                intel_mnemonic: "VMINPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5D,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vmaxph",
                intel_mnemonic: "VMAXPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5F,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vsqrtph",
                intel_mnemonic: "VSQRTPH",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x51,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vrndscaleph",
                intel_mnemonic: "VRNDSCALEPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x08,
                opcode_map: 3,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtph2w",
                intel_mnemonic: "VCVTPH2W",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x7D,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtw2ph",
                intel_mnemonic: "VCVTW2PH",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x7D,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtph2uw",
                intel_mnemonic: "VCVTPH2UW",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x7D,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtuw2ph",
                intel_mnemonic: "VCVTUW2PH",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x7D,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AVX-512 FP16 FMA
            ExtInstrDesc {
                mnemonic: "vfmadd132ph",
                intel_mnemonic: "VFMADD132PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x98,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfmadd213ph",
                intel_mnemonic: "VFMADD213PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xA8,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfmadd231ph",
                intel_mnemonic: "VFMADD231PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB8,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfmsub132ph",
                intel_mnemonic: "VFMSUB132PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x9A,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfmsub213ph",
                intel_mnemonic: "VFMSUB213PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xAA,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfmsub231ph",
                intel_mnemonic: "VFMSUB231PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xBA,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmadd132ph",
                intel_mnemonic: "VFNMADD132PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x9C,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmadd213ph",
                intel_mnemonic: "VFNMADD213PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xAC,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmadd231ph",
                intel_mnemonic: "VFNMADD231PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xBC,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmsub132ph",
                intel_mnemonic: "VFNMSUB132PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x9E,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmsub213ph",
                intel_mnemonic: "VFNMSUB213PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xAE,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vfnmsub231ph",
                intel_mnemonic: "VFNMSUB231PH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xBE,
                opcode_map: 2,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AVX-512 FP16 comparison
            ExtInstrDesc {
                mnemonic: "vcmpph",
                intel_mnemonic: "VCMPPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xC2,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vgetmantph",
                intel_mnemonic: "VGETMANTPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x26,
                opcode_map: 3,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vgetexpph",
                intel_mnemonic: "VGETEXPPH",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x42,
                opcode_map: 0,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vscalefph",
                intel_mnemonic: "VSCALEFPH",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x2C,
                opcode_map: 3,
                mandatory_prefix: 3,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // ================================================================
            // AVX-512 BF16 — brain floating-point
            // ================================================================
            ExtInstrDesc {
                mnemonic: "vcvtne2ps2bf16",
                intel_mnemonic: "VCVTNE2PS2BF16",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x72,
                opcode_map: 3,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneebf162ps",
                intel_mnemonic: "VCVTNEEBF162PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB2,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vcvtneobf162ps",
                intel_mnemonic: "VCVTNEOBF162PS",
                num_operands: 2,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0xB3,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "vdpbf16ps",
                intel_mnemonic: "VDPBF16PS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x52,
                opcode_map: 2,
                mandatory_prefix: 2,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // ================================================================
            // AVX-512 AMX — Advanced Matrix Extensions tile ops
            // ================================================================
            ExtInstrDesc {
                mnemonic: "tdpbssd",
                intel_mnemonic: "TDPBSSD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5E,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tdpbsud",
                intel_mnemonic: "TDPBSUD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5E,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tdpbusd",
                intel_mnemonic: "TDPBUSD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5E,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tdpbuud",
                intel_mnemonic: "TDPBUUD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5E,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tdpbf16ps",
                intel_mnemonic: "TDPBF16PS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5C,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AMX-FP16
            ExtInstrDesc {
                mnemonic: "tdpfp16ps",
                intel_mnemonic: "TDPFP16PS",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x5C,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: false,
            },
            // AMX TILE operations
            ExtInstrDesc {
                mnemonic: "tileloadd",
                intel_mnemonic: "TILELOADD",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x4B,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: true,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tilestored",
                intel_mnemonic: "TILESTORED",
                num_operands: 3,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x4B,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: true,
            },
            ExtInstrDesc {
                mnemonic: "tileconfig",
                intel_mnemonic: "TILECONFIG",
                num_operands: 1,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x49,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: true,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tilerelease",
                intel_mnemonic: "TILERELEASE",
                num_operands: 0,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x49,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: false,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: true,
                may_load: false,
                may_store: false,
            },
            ExtInstrDesc {
                mnemonic: "tilezero",
                intel_mnemonic: "TILEZERO",
                num_operands: 1,
                encoding_form: EncodingForm::EVEX,
                base_opcode: 0x49,
                opcode_map: 2,
                mandatory_prefix: 1,
                requires_modrm: true,
                modrm_extension: 255,
                is_terminator: false,
                has_side_effects: false,
                may_load: false,
                may_store: true,
            },
        ]
    }

    /// Find an extension instruction by mnemonic.
    pub fn find_ext_by_mnemonic(mnemonic: &str) -> Option<ExtInstrDesc> {
        Self::get_extension_instructions()
            .into_iter()
            .find(|e| e.mnemonic == mnemonic || e.intel_mnemonic == mnemonic)
    }

    /// Get the total count of extension instructions.
    pub fn extension_instruction_count() -> usize {
        Self::get_extension_instructions().len()
    }
}

impl Default for X86FullInstrInfo {
    fn default() -> Self {
        X86FullInstrInfo::new()
    }
}

// ============================================================================
// Intel APX (Advanced Performance Extensions) — REX2, EGPR, NDD, CCMP, PUSH2/POP2
// ============================================================================

/// APX extensions added to x86-64 in the Granite Rapids / Sierra Forest era.
/// Key features:
/// - REX2 prefix: extends register encoding to 32 GPRs (r0-r31) and 32 XMM/YMM/ZMM registers
/// - Extended GPRs: EGPRs r16-r31 accessible via REX2 prefix
/// - Three-operand (NDD) forms: non-destructive destination for all ALU ops
/// - Conditional compare: CCMP, CTEST with flags
/// - PUSH2/POP2: push/pop two registers at once
/// - Zero-upper: implicit zeroing of upper bits on GPR writes

/// REX2 prefix byte constants.
/// REX2 is an 8-bit prefix (0xD5) that allows encoding up to 32 registers.
pub mod rex2_prefix {
    /// REX2 prefix byte.
    pub const REX2: u8 = 0xD5;

    /// Build a REX2 prefix byte.
    ///
    /// REX2 layout: [M0 | R4 | X4 | B4 | W | R3 | X3 | B3]
    ///   M0: must be 0 for REX2 (set to 1 for future expansion)
    ///   R4: extension of REX.R (bit 4 of ModR/M reg field)
    ///   X4: extension of REX.X (bit 4 of SIB index field)
    ///   B4: extension of REX.B (bit 4 of ModR/M r/m or SIB base)
    ///   W: 64-bit operand size (same as REX.W)
    ///   R3: REX.R (bit 3 of ModR/M reg field)
    ///   X3: REX.X (bit 3 of SIB index field)
    ///   B3: REX.B (bit 3 of ModR/M r/m or SIB base)
    pub fn build(
        m0: bool,
        r4: bool,
        x4: bool,
        b4: bool,
        w: bool,
        r3: bool,
        x3: bool,
        b3: bool,
    ) -> u8 {
        ((m0 as u8) << 7)
            | ((r4 as u8) << 6)
            | ((x4 as u8) << 5)
            | ((b4 as u8) << 4)
            | ((w as u8) << 3)
            | ((r3 as u8) << 2)
            | ((x3 as u8) << 1)
            | (b3 as u8)
    }

    /// Build a REX2 for a simple 64-bit operation with no extended registers.
    pub fn w() -> u8 {
        build(false, false, false, false, true, false, false, false)
    }

    /// Extract R4 from REX2 (bit 6).
    pub fn r4(rex2: u8) -> bool {
        (rex2 >> 6) & 1 != 0
    }

    /// Extract X4 from REX2 (bit 5).
    pub fn x4(rex2: u8) -> bool {
        (rex2 >> 5) & 1 != 0
    }

    /// Extract B4 from REX2 (bit 4).
    pub fn b4(rex2: u8) -> bool {
        (rex2 >> 4) & 1 != 0
    }

    /// Extract W from REX2 (bit 3).
    pub fn w_bit(rex2: u8) -> bool {
        (rex2 >> 3) & 1 != 0
    }

    /// Extract R3 from REX2 (bit 2).
    pub fn r3(rex2: u8) -> bool {
        (rex2 >> 2) & 1 != 0
    }

    /// Extract X3 from REX2 (bit 1).
    pub fn x3(rex2: u8) -> bool {
        (rex2 >> 1) & 1 != 0
    }

    /// Extract B3 from REX2 (bit 0).
    pub fn b3(rex2: u8) -> bool {
        rex2 & 1 != 0
    }

    /// Check if an REX2 prefix is needed for the given register numbers.
    /// REX2 is needed when any register is r16-r31 (or xmm16-xmm31).
    pub fn needed(reg1: u8, reg2: Option<u8>, rm: Option<u8>) -> bool {
        reg1 >= 16 || reg2.map_or(false, |r| r >= 16) || rm.map_or(false, |r| r >= 16)
    }

    /// Check if an REX2 prefix is needed when three registers are involved.
    pub fn needed_3op(dst: u8, src1: u8, src2: u8) -> bool {
        dst >= 16 || src1 >= 16 || src2 >= 16
    }

    /// Build REX2 for a register-to-register operation.
    /// Returns (rex2_byte, m0, r4, x4, b4, w, r3, x3, b3)
    pub fn build_for_regs(reg: u8, rm: u8, w: bool) -> [u8; 2] {
        let needs_rex2 = reg >= 16 || rm >= 16;
        if !needs_rex2 {
            // Use legacy REX prefix
            let rex = 0x40 | ((w as u8) << 3) | (((reg >> 3) & 1) << 2) | (((rm >> 3) & 1) << 0);
            return [rex, 0];
        }

        let r4 = (reg >> 4) & 1 != 0;
        let r3 = (reg >> 3) & 1 != 0;
        let b4 = (rm >> 4) & 1 != 0;
        let b3 = (rm >> 3) & 1 != 0;

        let rex2 = build(false, r4, false, b4, w, r3, false, b3);
        [REX2, rex2]
    }

    /// Build REX2 for a three-operand (NDD) operation.
    pub fn build_for_ndd(dst: u8, src1: u8, src2: u8, w: bool) -> [u8; 2] {
        let needs_rex2 = dst >= 16 || src1 >= 16 || src2 >= 16;
        if !needs_rex2 {
            let rex = 0x40 | ((w as u8) << 3) | (((src1 >> 3) & 1) << 2) | (((src2 >> 3) & 1) << 0);
            return [rex, 0];
        }

        let r4 = (src1 >> 4) & 1 != 0;
        let r3 = (src1 >> 3) & 1 != 0;
        let b4 = (src2 >> 4) & 1 != 0;
        let b3 = (src2 >> 3) & 1 != 0;
        let x4 = (dst >> 4) & 1 != 0;

        let rex2 = build(false, r4, x4, b4, w, r3, false, b3);
        [REX2, rex2]
    }
}

// ============================================================================
// APX Extended GPR (EGPR) — registers r16-r31
// ============================================================================

/// Extended General Purpose Register identifiers for APX.
/// These go beyond the traditional r8-r15 and xmm16-xmm31.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[repr(u8)]
pub enum EgprId {
    R16 = 16,
    R17 = 17,
    R18 = 18,
    R19 = 19,
    R20 = 20,
    R21 = 21,
    R22 = 22,
    R23 = 23,
    R24 = 24,
    R25 = 25,
    R26 = 26,
    R27 = 27,
    R28 = 28,
    R29 = 29,
    R30 = 30,
    R31 = 31,
}

impl EgprId {
    /// Get the register number (16-31).
    pub fn number(&self) -> u8 {
        *self as u8
    }

    /// Get the 64-bit register name.
    pub fn name64(&self) -> &'static str {
        match self {
            Self::R16 => "r16",
            Self::R17 => "r17",
            Self::R18 => "r18",
            Self::R19 => "r19",
            Self::R20 => "r20",
            Self::R21 => "r21",
            Self::R22 => "r22",
            Self::R23 => "r23",
            Self::R24 => "r24",
            Self::R25 => "r25",
            Self::R26 => "r26",
            Self::R27 => "r27",
            Self::R28 => "r28",
            Self::R29 => "r29",
            Self::R30 => "r30",
            Self::R31 => "r31",
        }
    }

    /// Get the 32-bit register name.
    pub fn name32(&self) -> &'static str {
        match self {
            Self::R16 => "r16d",
            Self::R17 => "r17d",
            Self::R18 => "r18d",
            Self::R19 => "r19d",
            Self::R20 => "r20d",
            Self::R21 => "r21d",
            Self::R22 => "r22d",
            Self::R23 => "r23d",
            Self::R24 => "r24d",
            Self::R25 => "r25d",
            Self::R26 => "r26d",
            Self::R27 => "r27d",
            Self::R28 => "r28d",
            Self::R29 => "r29d",
            Self::R30 => "r30d",
            Self::R31 => "r31d",
        }
    }

    /// Get the 16-bit register name.
    pub fn name16(&self) -> &'static str {
        match self {
            Self::R16 => "r16w",
            Self::R17 => "r17w",
            Self::R18 => "r18w",
            Self::R19 => "r19w",
            Self::R20 => "r20w",
            Self::R21 => "r21w",
            Self::R22 => "r22w",
            Self::R23 => "r23w",
            Self::R24 => "r24w",
            Self::R25 => "r25w",
            Self::R26 => "r26w",
            Self::R27 => "r27w",
            Self::R28 => "r28w",
            Self::R29 => "r29w",
            Self::R30 => "r30w",
            Self::R31 => "r31w",
        }
    }

    /// Get the 8-bit register name.
    pub fn name8(&self) -> &'static str {
        match self {
            Self::R16 => "r16b",
            Self::R17 => "r17b",
            Self::R18 => "r18b",
            Self::R19 => "r19b",
            Self::R20 => "r20b",
            Self::R21 => "r21b",
            Self::R22 => "r22b",
            Self::R23 => "r23b",
            Self::R24 => "r24b",
            Self::R25 => "r25b",
            Self::R26 => "r26b",
            Self::R27 => "r27b",
            Self::R28 => "r28b",
            Self::R29 => "r29b",
            Self::R30 => "r30b",
            Self::R31 => "r31b",
        }
    }

    /// Return true if this EGPR requires REX2 prefix.
    pub fn needs_rex2(&self) -> bool {
        true // All EGPRs (r16-r31) require REX2
    }
}

/// Helper to check if a register number is an EGPR (16-31).
pub fn is_egpr(reg_num: u8) -> bool {
    reg_num >= 16 && reg_num <= 31
}

/// Helper to check if a register number requires REX2 prefix.
pub fn needs_rex2_prefix(reg_num: u8) -> bool {
    reg_num >= 16
}

// ============================================================================
// APX Three-Operand (NDD) Instruction Forms
// ============================================================================

/// APX Non-Destructive Destination (NDD) forms add an explicit destination
/// operand to instructions that traditionally had two operands where one
/// is both source and destination.
///
/// Example: ADD r1, r2, r3  → r1 = r2 + r3 (instead of ADD r1, r2 → r1 += r2)
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[allow(non_camel_case_types)]
pub enum ApkNddForm {
    /// NDD version of ADD: add_ndd dst, src1, src2 → dst = src1 + src2
    ADD_NDD,
    /// NDD version of SUB: sub_ndd dst, src1, src2 → dst = src1 - src2
    SUB_NDD,
    /// NDD version of AND: and_ndd dst, src1, src2 → dst = src1 & src2
    AND_NDD,
    /// NDD version of OR: or_ndd dst, src1, src2 → dst = src1 | src2
    OR_NDD,
    /// NDD version of XOR: xor_ndd dst, src1, src2 → dst = src1 ^ src2
    XOR_NDD,
    /// NDD version of ADC: adc_ndd dst, src1, src2 → dst = src1 + src2 + CF
    ADC_NDD,
    /// NDD version of SBB: sbb_ndd dst, src1, src2 → dst = src1 - src2 - CF
    SBB_NDD,
    /// NDD version of IMUL: imul_ndd dst, src1, src2 → dst = src1 * src2
    IMUL_NDD,
    /// NDD version of CMP: cmp_ndd src1, src2, flags → flags = src1 - src2
    CMP_NDD,
    /// NDD version of SHL: shl_ndd dst, src, count → dst = src << count
    SHL_NDD,
    /// NDD version of SHR: shr_ndd dst, src, count → dst = src >> count
    SHR_NDD,
    /// NDD version of SAR: sar_ndd dst, src, count → dst = src >> count (arithmetic)
    SAR_NDD,
    /// NDD version of ROL: rol_ndd dst, src, count → dst = src <<< count
    ROL_NDD,
    /// NDD version of ROR: ror_ndd dst, src, count → dst = src >>> count
    ROR_NDD,
    /// NDD version of NEG: neg_ndd dst, src → dst = -src
    NEG_NDD,
    /// NDD version of NOT: not_ndd dst, src → dst = ~src
    NOT_NDD,
    /// NDD version of INC: inc_ndd dst, src → dst = src + 1
    INC_NDD,
    /// NDD version of DEC: dec_ndd dst, src → dst = src - 1
    DEC_NDD,
}

impl ApkNddForm {
    /// Get the mnemonic for this NDD form.
    pub fn mnemonic(&self) -> &'static str {
        match self {
            Self::ADD_NDD => "add",
            Self::SUB_NDD => "sub",
            Self::AND_NDD => "and",
            Self::OR_NDD => "or",
            Self::XOR_NDD => "xor",
            Self::ADC_NDD => "adc",
            Self::SBB_NDD => "sbb",
            Self::IMUL_NDD => "imul",
            Self::CMP_NDD => "cmp",
            Self::SHL_NDD => "shl",
            Self::SHR_NDD => "shr",
            Self::SAR_NDD => "sar",
            Self::ROL_NDD => "rol",
            Self::ROR_NDD => "ror",
            Self::NEG_NDD => "neg",
            Self::NOT_NDD => "not",
            Self::INC_NDD => "inc",
            Self::DEC_NDD => "dec",
        }
    }

    /// Get the base opcode for the legacy (non-NDD) form.
    pub fn legacy_opcode(&self) -> u8 {
        match self {
            Self::ADD_NDD => 0x01,  // ADD r/m, r via /r (ModR/M reg=ext)
            Self::SUB_NDD => 0x29,  // SUB r/m, r
            Self::AND_NDD => 0x21,  // AND r/m, r
            Self::OR_NDD => 0x09,   // OR r/m, r
            Self::XOR_NDD => 0x31,  // XOR r/m, r
            Self::ADC_NDD => 0x11,  // ADC r/m, r
            Self::SBB_NDD => 0x19,  // SBB r/m, r
            Self::IMUL_NDD => 0xAF, // IMUL r, r/m (0F AF /r)
            Self::CMP_NDD => 0x39,  // CMP r/m, r
            Self::SHL_NDD => 0x20,  // SHL r/m, CL (D2 /4)
            Self::SHR_NDD => 0x28,  // SHR r/m, CL (D3 /5)
            Self::SAR_NDD => 0x38,  // SAR r/m, CL (D3 /7)
            Self::ROL_NDD => 0x00,  // ROL r/m, CL (D2 /0)
            Self::ROR_NDD => 0x08,  // ROR r/m, CL (D3 /1)
            Self::NEG_NDD => 0xD8,  // NEG r/m (F7 /3)
            Self::NOT_NDD => 0xD0,  // NOT r/m (F7 /2)
            Self::INC_NDD => 0xC0,  // INC r/m (FF /0)
            Self::DEC_NDD => 0xC8,  // DEC r/m (FF /1)
        }
    }

    /// Return the number of operands for this NDD form.
    pub fn num_operands(&self) -> u8 {
        match self {
            Self::NEG_NDD | Self::NOT_NDD | Self::INC_NDD | Self::DEC_NDD => 2,
            Self::CMP_NDD => 3, // dst is flags, src1, src2
            _ => 3,
        }
    }

    /// Whether this NDD form is commutative (src1 and src2 can be swapped).
    pub fn is_commutative(&self) -> bool {
        matches!(
            self,
            Self::ADD_NDD
                | Self::AND_NDD
                | Self::OR_NDD
                | Self::XOR_NDD
                | Self::ADC_NDD
                | Self::IMUL_NDD
        )
    }

    /// Get the OperandType for the destination.
    pub fn dst_type(&self) -> OperandType {
        match self {
            Self::CMP_NDD => OperandType::Reg64, // flags implicitly
            _ => OperandType::Reg64,
        }
    }

    /// Get the OperandType for source 1.
    pub fn src1_type(&self) -> OperandType {
        OperandType::Reg64
    }

    /// Get the OperandType for source 2.
    pub fn src2_type(&self) -> OperandType {
        match self {
            Self::SHL_NDD | Self::SHR_NDD | Self::SAR_NDD | Self::ROL_NDD | Self::ROR_NDD => {
                OperandType::Imm8
            }
            _ => OperandType::Reg64,
        }
    }
}

// ============================================================================
// APX Conditional Compare (CCMP, CTEST)
// ============================================================================

/// APX conditional compare operations: compare two operands
/// and conditionally update flags based on a condition code.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct ApkConditionalCompare {
    /// The condition code controlling whether the compare executes.
    pub condition: X86ConditionCode,
    /// Whether it's a CCMP (compare) or CTEST (test) operation.
    pub is_test: bool,
    /// The source flags register to test.
    pub src_flags: ApkFlagsReg,
    /// The destination flags register to write.
    pub dst_flags: ApkFlagsReg,
}

/// APX flags register designators.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ApkFlagsReg {
    /// Default flags register (OF, SF, ZF, AF, PF, CF).
    Flags,
    /// EFLAGS (32-bit flags).
    EFlags,
    /// RFLAGS (64-bit flags).
    RFlags,
    /// Condition flags only (OF, SF, ZF, CF).
    CondFlags,
}

impl ApkFlagsReg {
    pub fn name(&self) -> &'static str {
        match self {
            Self::Flags => "flags",
            Self::EFlags => "eflags",
            Self::RFlags => "rflags",
            Self::CondFlags => "condflags",
        }
    }
}

/// X86 condition codes used in CCMP.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[repr(u8)]
pub enum X86ConditionCode {
    O = 0,   // overflow
    NO = 1,  // no overflow
    B = 2,   // below (CF=1)
    NB = 3,  // not below (CF=0)
    Z = 4,   // zero (ZF=1)
    NZ = 5,  // not zero (ZF=0)
    BE = 6,  // below or equal (CF=1 or ZF=1)
    A = 7,   // above (CF=0 and ZF=0)
    S = 8,   // sign (SF=1)
    NS = 9,  // not sign (SF=0)
    P = 10,  // parity (PF=1)
    NP = 11, // not parity (PF=0)
    L = 12,  // less (SF != OF)
    GE = 13, // greater or equal (SF == OF)
    LE = 14, // less or equal (ZF=1 or SF != OF)
    G = 15,  // greater (ZF=0 and SF == OF)
    // APX-specific conditions
    T = 16, // always true
    F = 17, // always false
}

impl X86ConditionCode {
    pub fn mnemonic(&self) -> &'static str {
        match self {
            Self::O => "o",
            Self::NO => "no",
            Self::B => "b",
            Self::NB => "nb",
            Self::Z => "z",
            Self::NZ => "nz",
            Self::BE => "be",
            Self::A => "a",
            Self::S => "s",
            Self::NS => "ns",
            Self::P => "p",
            Self::NP => "np",
            Self::L => "l",
            Self::GE => "ge",
            Self::LE => "le",
            Self::G => "g",
            Self::T => "t",
            Self::F => "f",
        }
    }

    /// Whether this condition negates the original flag update.
    pub fn is_negating(&self) -> bool {
        matches!(self, Self::F)
    }
}

impl ApkConditionalCompare {
    /// Create a CCMP instruction description.
    pub fn ccmp(
        condition: X86ConditionCode,
        src_flags: ApkFlagsReg,
        dst_flags: ApkFlagsReg,
    ) -> Self {
        Self {
            condition,
            is_test: false,
            src_flags,
            dst_flags,
        }
    }

    /// Create a CTEST instruction description.
    pub fn ctest(
        condition: X86ConditionCode,
        src_flags: ApkFlagsReg,
        dst_flags: ApkFlagsReg,
    ) -> Self {
        Self {
            condition,
            is_test: true,
            src_flags,
            dst_flags,
        }
    }

    /// Get the mnemonic for this conditional compare.
    pub fn mnemonic(&self) -> String {
        if self.is_test {
            format!("ctest{}", self.condition.mnemonic())
        } else {
            format!("ccmp{}", self.condition.mnemonic())
        }
    }
}

// ============================================================================
// APX PUSH2 / POP2 — push/pop two registers at once
// ============================================================================

/// PUSH2 encoding: pushes two GPRs onto the stack in one instruction.
/// This is an APX extension that atomically pushes two registers.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct Push2Pop2 {
    /// First register.
    pub reg1: u8,
    /// Second register.
    pub reg2: u8,
    /// Whether this is POP2 (true) or PUSH2 (false).
    pub is_pop: bool,
}

impl Push2Pop2 {
    /// Create a PUSH2 encoding.
    pub fn push2(reg1: u8, reg2: u8) -> Self {
        Self {
            reg1,
            reg2,
            is_pop: false,
        }
    }

    /// Create a POP2 encoding.
    pub fn pop2(reg1: u8, reg2: u8) -> Self {
        Self {
            reg1,
            reg2,
            is_pop: true,
        }
    }

    /// Get the mnemonic.
    pub fn mnemonic(&self) -> &'static str {
        if self.is_pop {
            "pop2"
        } else {
            "push2"
        }
    }

    /// Get the opcode bytes.
    pub fn opcode(&self) -> u8 {
        if self.is_pop {
            0x8F // POP2 opcode prefix
        } else {
            0xFF // PUSH2 opcode prefix
        }
    }

    /// Encode the ModR/M byte for PUSH2/POP2.
    /// The reg field encodes reg1 (bits 2-0), and an extension in REX/REX2
    /// provides the high bit.
    pub fn encode_modrm(&self) -> u8 {
        let rm = self.reg2 & 0x7;
        let reg = self.reg1 & 0x7;
        let opcode_ext = if self.is_pop { 0 } else { 6 }; // /0 for POP2, /6 for PUSH2
        (0xC0) | ((opcode_ext & 0x7) << 3) | rm
    }
}

// ============================================================================
// APX Zero-Upper — zero upper bits on GPR writes
// ============================================================================

/// APX optionally zeros the upper 32 bits of a 64-bit GPR when writing
/// to the lower 32 bits (similar to the existing MOVSXD behavior).
/// This is controlled by a feature bit and the REX2.E bit.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ApkZeroUpper {
    /// No zero-upper (traditional behavior: upper bits preserved).
    None,
    /// Zero-upper enabled (upper 32 bits set to 0 on 32-bit GPR write).
    ZeroUpper,
    /// Zero-upper explicit (forced by instruction prefix).
    Explicit,
}

impl ApkZeroUpper {
    /// Whether this enables zero-upper behavior.
    pub fn is_enabled(&self) -> bool {
        !matches!(self, Self::None)
    }

    /// Get the REX2.EVEX bit value for this zero-upper mode.
    pub fn evex_bit(&self) -> bool {
        matches!(self, Self::Explicit)
    }
}

// ============================================================================
// APX Instruction Registry — registers all APX instructions
// ============================================================================

/// Registry of all APX instruction encodings.
#[derive(Debug, Clone)]
pub struct ApkInstructionRegistry {
    /// Map from mnemonic to instruction count.
    pub mnemonic_count: HashMap<String, usize>,
    /// Whether APX is enabled on this target.
    pub apx_enabled: bool,
    /// Whether EGPR is available.
    pub egpr_available: bool,
    /// Whether NDD forms are supported.
    pub ndd_supported: bool,
    /// Whether CCMP/CTEST is supported.
    pub ccmpx_supported: bool,
    /// Whether PUSH2/POP2 is supported.
    pub push2pop2_supported: bool,
}

impl ApkInstructionRegistry {
    pub fn new(apx_enabled: bool) -> Self {
        Self {
            mnemonic_count: HashMap::new(),
            apx_enabled,
            egpr_available: apx_enabled,
            ndd_supported: apx_enabled,
            ccmpx_supported: apx_enabled,
            push2pop2_supported: apx_enabled,
        }
    }

    /// Get the list of all APX instruction mnemonics.
    pub fn all_apx_mnemonics() -> Vec<&'static str> {
        vec![
            // BMI1-style APX extensions
            "andn", "bextr", "blsi", "blsmsk", "blsr", "bzhi", // Control-flow
            "incssp", "invpcid", // Multiply
            "mulx",    // PCOMMIT (deprecated but known)
            "pcommit", // Bit manipulation
            "pdep", "pext", // Shadow stack
            "rdsspd", "rdsspq", // Protection keys
            "rdpkru", // Shadow stack writes
            "wrssd", "wrssq", "wrussd", "wrussq",   // Restore shadow stack
            "rstorssp", // Shift without affecting flags
            "sarx", "shlx", "shrx", // Count trailing zeros
            "tzcnt", "tzcnti", // Count leading zeros
            "lzcnt",  // NDD forms of ALU operations
            "add", "sub", "and", "or", "xor", "adc", "sbb", "imul", "cmp", "shl", "shr", "sar",
            "rol", "ror", "neg", "not", "inc", "dec", // CCMP/CTEST forms
            "ccmpo", "ccmpno", "ccmpb", "ccmpnb", "ccmpz", "ccmpnz", "ccmpbe", "ccmpa", "ccmps",
            "ccmpns", "ccmpp", "ccmpnp", "ccmpl", "ccmpge", "ccmple", "ccmpg", "ccmpt", "ccmpf",
            "ctesto", "ctestno", "ctestb", "ctestnb", "ctestz", "ctestnz", "ctestbe", "ctesta",
            "ctests", "ctestns", "ctestp", "ctestnp", "ctestl", "ctestge", "ctestle", "ctestg",
            "ctestt", "ctestf", // PUSH2 / POP2
            "push2", "pop2",
        ]
    }

    /// Get the total number of APX instruction forms.
    pub fn apx_form_count() -> usize {
        // All NDD forms (18) + CCMP (18 conds) + CTEST (18 conds) + PUSH2 + POP2
        18 + 18 + 18 + 2
    }

    /// Check if a given mnemonic is an APX instruction.
    pub fn is_apx_mnemonic(mnemonic: &str) -> bool {
        Self::all_apx_mnemonics().contains(&mnemonic)
    }

    /// Return a basic description for an APX NDD instruction.
    pub fn describe_ndd(form: ApkNddForm) -> String {
        format!(
            "APX NDD {} ({} operands, commutative: {})",
            form.mnemonic(),
            form.num_operands(),
            form.is_commutative()
        )
    }

    /// Return a description for CCMP/CTEST.
    pub fn describe_ccmp(cc: &ApkConditionalCompare) -> String {
        format!(
            "APX {} (flags: {} -> {})",
            cc.mnemonic(),
            cc.src_flags.name(),
            cc.dst_flags.name()
        )
    }

    /// Return a description for PUSH2/POP2.
    pub fn describe_push2pop2(pp: &Push2Pop2) -> String {
        format!("APX {} r{}, r{}", pp.mnemonic(), pp.reg1, pp.reg2)
    }
}

impl Default for ApkInstructionRegistry {
    fn default() -> Self {
        Self::new(false)
    }
}

// ============================================================================
// APX Instruction Set — detailed instruction metadata tables
// ============================================================================

/// Describes a single APX instruction with its encoding properties.
#[derive(Debug, Clone)]
pub struct ApkInstrDesc {
    /// Mnemonic string.
    pub mnemonic: &'static str,
    /// Base opcode (not including prefix bytes).
    pub base_opcode: u8,
    /// Opcode map: 0=1-byte, 1=0F, 2=0F38.
    pub opcode_map: u8,
    /// Number of explicit operands.
    pub num_operands: u8,
    /// Needs REX2 prefix.
    pub needs_rex2: bool,
    /// Is NDD (three-operand) form.
    pub is_ndd: bool,
    /// Has side effects (writes flags, etc).
    pub has_side_effects: bool,
    /// Category string.
    pub category: &'static str,
}

/// Static table of APX instruction descriptions.
/// Includes BMI1/BMI2-style extensions, shadow stack, PKU, and NDD forms.
pub static APX_INSTRUCTION_TABLE: &[ApkInstrDesc] = &[
    // === BMI1-style APX extensions ===
    ApkInstrDesc {
        mnemonic: "andn",
        base_opcode: 0xF2,
        opcode_map: 1,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "bextr",
        base_opcode: 0xF7,
        opcode_map: 1,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "blsi",
        base_opcode: 0xF3,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "blsmsk",
        base_opcode: 0xF3,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "blsr",
        base_opcode: 0xF3,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "bzhi",
        base_opcode: 0xF5,
        opcode_map: 1,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    // === MulX ===
    ApkInstrDesc {
        mnemonic: "mulx",
        base_opcode: 0xF6,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    // === Bit manipulation (BMI2) ===
    ApkInstrDesc {
        mnemonic: "pdep",
        base_opcode: 0xF5,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    ApkInstrDesc {
        mnemonic: "pext",
        base_opcode: 0xF5,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    // === Shift without flags (BMI2) ===
    ApkInstrDesc {
        mnemonic: "sarx",
        base_opcode: 0xF7,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    ApkInstrDesc {
        mnemonic: "shlx",
        base_opcode: 0xF7,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    ApkInstrDesc {
        mnemonic: "shrx",
        base_opcode: 0xF7,
        opcode_map: 2,
        num_operands: 3,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi2",
    },
    // === Count trailing zeros ===
    ApkInstrDesc {
        mnemonic: "tzcnt",
        base_opcode: 0xBC,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    ApkInstrDesc {
        mnemonic: "tzcnti",
        base_opcode: 0xBC,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "bmi1",
    },
    // === Count leading zeros ===
    ApkInstrDesc {
        mnemonic: "lzcnt",
        base_opcode: 0xBD,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "abm",
    },
    // === Shadow stack ===
    ApkInstrDesc {
        mnemonic: "incssp",
        base_opcode: 0xAE,
        opcode_map: 1,
        num_operands: 1,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "rdsspd",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 1,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "rdsspq",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 1,
        needs_rex2: true,
        is_ndd: false,
        has_side_effects: false,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "wrssd",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "wrssq",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "wrussd",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "wrussq",
        base_opcode: 0x1E,
        opcode_map: 1,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    ApkInstrDesc {
        mnemonic: "rstorssp",
        base_opcode: 0x01,
        opcode_map: 1,
        num_operands: 1,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: true,
        category: "cet",
    },
    // === Protection keys ===
    ApkInstrDesc {
        mnemonic: "rdpkru",
        base_opcode: 0xEE,
        opcode_map: 1,
        num_operands: 0,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: false,
        category: "pku",
    },
    // === INVPCID ===
    ApkInstrDesc {
        mnemonic: "invpcid",
        base_opcode: 0x82,
        opcode_map: 2,
        num_operands: 2,
        needs_rex2: false,
        is_ndd: false,
        has_side_effects: true,
        category: "system",
    },
    // === NDD ALU forms ===
    ApkInstrDesc {
        mnemonic: "add_ndd",
        base_opcode: 0x01,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "sub_ndd",
        base_opcode: 0x29,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "and_ndd",
        base_opcode: 0x21,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "or_ndd",
        base_opcode: 0x09,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "xor_ndd",
        base_opcode: 0x31,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "adc_ndd",
        base_opcode: 0x11,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "sbb_ndd",
        base_opcode: 0x19,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "imul_ndd",
        base_opcode: 0xAF,
        opcode_map: 1,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "cmp_ndd",
        base_opcode: 0x39,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "shl_ndd",
        base_opcode: 0x20,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "shr_ndd",
        base_opcode: 0x28,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "sar_ndd",
        base_opcode: 0x38,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "rol_ndd",
        base_opcode: 0x00,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "ror_ndd",
        base_opcode: 0x08,
        opcode_map: 0,
        num_operands: 3,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "neg_ndd",
        base_opcode: 0xD8,
        opcode_map: 0,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "not_ndd",
        base_opcode: 0xD0,
        opcode_map: 0,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "inc_ndd",
        base_opcode: 0xC0,
        opcode_map: 0,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
    ApkInstrDesc {
        mnemonic: "dec_ndd",
        base_opcode: 0xC8,
        opcode_map: 0,
        num_operands: 2,
        needs_rex2: true,
        is_ndd: true,
        has_side_effects: true,
        category: "ndd",
    },
];

/// Lookup an APX instruction by mnemonic.
pub fn lookup_apx_instr(mnemonic: &str) -> Option<&'static ApkInstrDesc> {
    APX_INSTRUCTION_TABLE
        .iter()
        .find(|d| d.mnemonic == mnemonic)
}

/// Get all APX instructions of a specific category.
pub fn apx_instrs_by_category(category: &str) -> Vec<&'static ApkInstrDesc> {
    APX_INSTRUCTION_TABLE
        .iter()
        .filter(|d| d.category == category)
        .collect()
}

/// Count the number of APX instructions in a category.
pub fn apx_instr_count_by_category(category: &str) -> usize {
    APX_INSTRUCTION_TABLE
        .iter()
        .filter(|d| d.category == category)
        .count()
}

// ============================================================================
// APX Feature Detection
// ============================================================================

/// CPU feature flags relevant to APX.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
#[repr(u32)]
#[allow(non_camel_case_types)]
pub enum ApkFeature {
    /// Basic APX support (REX2 prefix).
    APX = 0,
    /// Extended GPRs (r16-r31).
    EGPR = 1,
    /// Non-destructive destination (3-operand ALU).
    NDD = 2,
    /// Conditional compare (CCMP, CTEST).
    CCMP = 3,
    /// PUSH2/POP2.
    PPX = 4,
    /// Zero-upper on GPR writes.
    ZU = 5,
    /// User interrupts.
    UINTR = 6,
    /// Implicit zeroing.
    IMZ = 7,
    /// 16-bit extended GPR (r8w-r31w).
    EGPR16 = 8,
    /// 32-bit extended GPR (r8d-r31d).
    EGPR32 = 9,
    /// NDD for BMI instructions.
    NDD_BMI = 10,
}

impl ApkFeature {
    pub fn name(&self) -> &'static str {
        match self {
            Self::APX => "apx",
            Self::EGPR => "egpr",
            Self::NDD => "ndd",
            Self::CCMP => "ccmp",
            Self::PPX => "ppx",
            Self::ZU => "zu",
            Self::UINTR => "uintr",
            Self::IMZ => "imz",
            Self::EGPR16 => "egpr16",
            Self::EGPR32 => "egpr32",
            Self::NDD_BMI => "ndd_bmi",
        }
    }

    /// Get the CPUID leaf and sub-leaf for this feature.
    pub fn cpuid_info(&self) -> (u32, u32, u32) {
        match self {
            Self::APX | Self::EGPR | Self::NDD | Self::CCMP | Self::PPX | Self::ZU => (7, 1, 0),
            Self::UINTR => (7, 0, 0),
            Self::IMZ => (7, 2, 0),
            Self::EGPR16 | Self::EGPR32 => (7, 1, 0),
            Self::NDD_BMI => (7, 1, 0),
        }
    }

    /// Get the bit position in the CPUID result.
    pub fn cpuid_bit(&self) -> u32 {
        match self {
            Self::APX => 21,
            Self::EGPR => 22,
            Self::NDD => 23,
            Self::CCMP => 24,
            Self::PPX => 25,
            Self::ZU => 26,
            Self::UINTR => 5,
            Self::IMZ => 2,
            Self::EGPR16 => 6,
            Self::EGPR32 => 7,
            Self::NDD_BMI => 28,
        }
    }

    /// Check if this feature is required for a specific APX instruction category.
    pub fn required_for_category(category: &str) -> Vec<Self> {
        match category {
            "bmi1" | "bmi2" | "abm" => vec![Self::APX],
            "cet" => vec![Self::APX],
            "pku" => vec![Self::APX],
            "system" => vec![Self::APX],
            "ndd" => vec![Self::APX, Self::NDD, Self::EGPR],
            "ccmp" => vec![Self::APX, Self::CCMP],
            "ppx" => vec![Self::APX, Self::PPX],
            _ => vec![Self::APX],
        }
    }
}

/// Check whether a target CPU supports APX extensions.
#[derive(Debug, Clone)]
pub struct ApkFeatureSet {
    /// Bitmap of enabled APX features.
    pub features: u64,
    /// Whether APX is available at all.
    pub apx_available: bool,
}

impl ApkFeatureSet {
    pub fn new(feature_bits: u64) -> Self {
        Self {
            features: feature_bits,
            apx_available: feature_bits & (1 << ApkFeature::APX as u32) != 0,
        }
    }

    /// Check if a specific feature is enabled.
    pub fn has(&self, feature: ApkFeature) -> bool {
        self.features & (1 << feature as u32) != 0
    }

    /// Check if EGPR is available.
    pub fn has_egpr(&self) -> bool {
        self.has(ApkFeature::EGPR)
    }

    /// Check if NDD forms are available.
    pub fn has_ndd(&self) -> bool {
        self.has(ApkFeature::NDD)
    }

    /// Check if CCMP/CTEST is available.
    pub fn has_ccmp(&self) -> bool {
        self.has(ApkFeature::CCMP)
    }

    /// Check if PUSH2/POP2 is available.
    pub fn has_ppx(&self) -> bool {
        self.has(ApkFeature::PPX)
    }

    /// Get a list of enabled feature names.
    pub fn enabled_features(&self) -> Vec<&'static str> {
        let all = [
            ApkFeature::APX,
            ApkFeature::EGPR,
            ApkFeature::NDD,
            ApkFeature::CCMP,
            ApkFeature::PPX,
            ApkFeature::ZU,
            ApkFeature::UINTR,
            ApkFeature::IMZ,
            ApkFeature::EGPR16,
            ApkFeature::EGPR32,
            ApkFeature::NDD_BMI,
        ];
        all.iter()
            .filter(|f| self.has(**f))
            .map(|f| f.name())
            .collect()
    }

    /// Create a feature set with all APX features enabled (for testing).
    pub fn all_enabled() -> Self {
        let mut f = 0u64;
        for feat in &[
            ApkFeature::APX,
            ApkFeature::EGPR,
            ApkFeature::NDD,
            ApkFeature::CCMP,
            ApkFeature::PPX,
            ApkFeature::ZU,
            ApkFeature::EGPR16,
            ApkFeature::EGPR32,
            ApkFeature::NDD_BMI,
        ] {
            f |= 1 << (*feat as u32);
        }
        Self::new(f)
    }
}

impl Default for ApkFeatureSet {
    fn default() -> Self {
        Self::new(0)
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_full_opcode_count() {
        // We should have exactly 722 opcode variants (400 through 1121)
        let info = X86FullInstrInfo::new();
        let count = info.infos.len();
        assert!(
            count >= 700,
            "Expected at least 700 instructions, got {}",
            count
        );
    }

    #[test]
    fn test_movrr_lookup() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::MOVrr).unwrap();
        assert_eq!(enc.mnemonic, "mov");
        assert_eq!(enc.num_operands, 2);
        assert_eq!(enc.requires_modrm, true);
        assert_eq!(enc.encoding_form, EncodingForm::Legacy);
    }

    #[test]
    fn test_cmov_classification() {
        assert!(X86FullOpcode::CMOVO.is_cmov());
        assert!(X86FullOpcode::CMOVG_FULL.is_cmov());
        assert!(!X86FullOpcode::ADD.is_cmov());
    }

    #[test]
    fn test_jcc_classification() {
        assert!(X86FullOpcode::JE_FULL.is_jcc());
        assert!(X86FullOpcode::JG_FULL.is_jcc());
        assert!(!X86FullOpcode::JMP.is_jcc());
        assert!(!X86FullOpcode::CALL.is_jcc());
    }

    #[test]
    fn test_setcc_classification() {
        assert!(X86FullOpcode::SETE.is_setcc());
        assert!(X86FullOpcode::SETG.is_setcc());
        assert!(!X86FullOpcode::ADD.is_setcc());
    }

    #[test]
    fn test_vex_classification() {
        assert!(X86FullOpcode::VADDPS.is_vex());
        assert!(X86FullOpcode::VPERMILPS.is_vex());
        assert!(!X86FullOpcode::ADDPS.is_vex());
    }

    #[test]
    fn test_evex_classification() {
        assert!(X86FullOpcode::VPADDD_Z.is_evex());
        assert!(X86FullOpcode::VCOMPRESSPS_Z.is_evex());
        assert!(!X86FullOpcode::VADDPS.is_evex());
    }

    #[test]
    fn test_system_has_side_effects() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::SYSCALL).unwrap();
        assert!(enc.has_side_effects);
        let enc = info.get(X86FullOpcode::HLT).unwrap();
        assert!(enc.has_side_effects);
    }

    #[test]
    fn test_find_by_mnemonic() {
        let info = X86FullInstrInfo::new();
        let op = info.find_by_mnemonic("add");
        assert_eq!(op, Some(X86FullOpcode::ADD));

        let op = info.find_by_mnemonic("vaddps");
        assert_eq!(op, Some(X86FullOpcode::VADDPS));

        let op = info.find_by_mnemonic("aesenc");
        assert_eq!(op, Some(X86FullOpcode::AESENC));
    }

    #[test]
    fn test_fma_instructions() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::VFMADD132PD).unwrap();
        assert_eq!(enc.encoding_form, EncodingForm::VEX3Byte);
        assert!(enc.is_commutative);
        assert!(enc.is_three_address);
    }

    #[test]
    fn test_avx512_present() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::VPADDD_Z).unwrap();
        assert_eq!(enc.encoding_form, EncodingForm::EVEX);
        assert_eq!(enc.num_operands, 3);
    }

    #[test]
    fn test_amx_present() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::TILELOADD).unwrap();
        assert!(enc.mnemonic == "tileloadd");
        let enc = info.get(X86FullOpcode::TDPBSSD).unwrap();
        assert_eq!(enc.num_operands, 3);
    }

    #[test]
    fn test_cet_present() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::ENDBR64).unwrap();
        assert_eq!(enc.num_operands, 0);
        assert!(!enc.has_side_effects);
    }

    #[test]
    fn test_serialize_present() {
        let info = X86FullInstrInfo::new();
        let enc = info.get(X86FullOpcode::SERIALIZE).unwrap();
        assert_eq!(enc.mnemonic, "serialize");
    }

    #[test]
    fn test_all_opcodes_have_mnemonic() {
        let info = X86FullInstrInfo::new();
        for (op, enc) in &info.infos {
            assert!(
                !enc.mnemonic.is_empty(),
                "Opcode {:?} has empty mnemonic",
                op
            );
        }
    }

    #[test]
    fn test_opcode_mnemonic_unique_count() {
        // Many mnemonics may repeat (e.g., multiple MOV forms), so we check
        // that we have a reasonable number of unique mnemonics.
        let info = X86FullInstrInfo::new();
        let unique_count = info.by_mnemonic.len();
        assert!(
            unique_count >= 400,
            "Expected at least 400 unique mnemonics, got {}",
            unique_count
        );
    }
}