llvm-native-core 0.1.6

//! X86 MC Instruction Information — Complete MC-layer instruction metadata,
//! analysis, and printing for all X86 instructions.
//!
//! Provides:
//! - `X86MCInstrInfoFull`: Complete instruction property database for 500+ instructions
//! - `X86MCInstrAnalysis`: Instruction analysis (branch eval, classification, latency)
//! - `X86MCInstrPrinter`: AT&T and Intel syntax printing with all addressing modes
//!
//! Instruction properties include:
//! - Scheduling: operand latency, issue latency, throughput, micro-ops, pipeline stages
//! - Hardware unit usage: ALU/AGU/FPU/SIMD ports, branch unit
//! - Flags: ZF, SF, OF, CF, PF, AF writes/reads/implicit sets
//! - Side effects: mayLoad, mayStore, hasSideEffects, isReturn, isCall, etc.
//! - Operand info: explicit operands, implicit defs/uses, constraints
//! - Encoding: min/max bytes, relaxable
//! - Memory: addressing modes, fold load/store
//! - Scheduler: resource cycles per pipeline stage for Skylake/Zen4
//!
//! Clean-room behavioral reconstruction from:
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual Vol 2
//! - AMD64 Architecture Programmer's Manual Vol 3
//! - Agner Fog's instruction tables
//! - uops.info (publicly available microarchitecture data)
//! - Intel® 64 and IA-32 Architectures Optimization Reference Manual
//!
//! Zero LLVM source code consultation.

use std::collections::HashMap;

use super::x86_register_info::{
    AH, AL, AX, BH, BL, BP, BPL, BX, CH, CL, CS, CX, DH, DI, DIL, DL, DS, DX, EAX, EBP, EBX, ECX,
    EDI, EDX, ES, ESI, ESP, FS, GS, K0, K1, K2, K3, K4, K5, K6, K7, R10, R10B, R10D, R10W, R11,
    R11B, R11D, R11W, R12, R12B, R12D, R12W, R13, R13B, R13D, R13W, R14, R14B, R14D, R14W, R15,
    R15B, R15D, R15W, R8, R8B, R8D, R8W, R9, R9B, R9D, R9W, RAX, RBP, RBX, RCX, RDI, RDX, RFLAGS,
    RIP, RSI, RSP, SI, SIL, SP, SPL, SS, XMM0, XMM1, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15,
    XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, YMM0, YMM1, YMM10, YMM11, YMM12, YMM13, YMM14,
    YMM15, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5,
    ZMM6, ZMM7,
};

// ============================================================================
// SchedPort — execution port identifiers for modern x86 microarchitectures
// ============================================================================

/// Execution port identifier covering Intel and AMD microarchitectures.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum SchedPort {
    // Intel Skylake/Ice Lake/Tiger Lake ports
    Port0,
    Port1,
    Port2,
    Port3,
    Port4,
    Port5,
    Port6,
    Port7,
    // Intel additional ports (Golden Cove+)
    Port8,
    Port9,
    Port10,
    Port11,
    Port12,
    // AMD Zen ports
    ZenAlu0,
    ZenAlu1,
    ZenAlu2,
    ZenAlu3,
    ZenAgu0,
    ZenAgu1,
    ZenAgu2,
    ZenAgu3,
    ZenFpu0,
    ZenFpu1,
    ZenFpu2,
    ZenFpu3,
    // Generic functional units
    LoadUnit,
    StoreUnit,
    StoreData,
    BranchUnit,
    IntDivider,
    IntMultiplier,
    VecAlu,
    VecShuffle,
    VecMultiplier,
    VecDivider,
}

// ============================================================================
// Flag — x86 EFLAGS/RFLAGS individual flags
// ============================================================================

/// Individual x86 flags in EFLAGS/RFLAGS register.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum Flag {
    CF, // Carry Flag (bit 0)
    PF, // Parity Flag (bit 2)
    AF, // Auxiliary Carry Flag (bit 4)
    ZF, // Zero Flag (bit 6)
    SF, // Sign Flag (bit 7)
    OF, // Overflow Flag (bit 11)
    DF, // Direction Flag (bit 10)
    IF, // Interrupt Enable Flag (bit 9)
}

impl Flag {
    /// All arithmetic status flags.
    pub const ARITHMETIC: [Flag; 6] = [Flag::CF, Flag::PF, Flag::AF, Flag::ZF, Flag::SF, Flag::OF];
}

// ============================================================================
// OperandConstraint — constraints on operand usage
// ============================================================================

/// Constraint on an instruction operand.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum OperandConstraint {
    /// Must be the same register as a specific other operand (tied).
    TiedToDef(usize),
    /// Must be an immediate in a specific range.
    ImmRange(i64, i64),
    /// Must be a specific register class.
    RegClass(&'static str),
    /// No specific constraint.
    None,
}

// ============================================================================
// AddrMode — addressing modes supported
// ============================================================================

/// Addressing mode classification for memory operands.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum AddrMode {
    /// Absolute address (disp only, no base/index).
    Absolute,
    /// Base register only.
    BaseOnly,
    /// Base + displacement.
    BaseDisp,
    /// Base + index * scale.
    BaseIndex,
    /// Base + index * scale + displacement.
    BaseIndexDisp,
    /// RIP-relative (x86-64 only).
    RIPRelative,
    /// Index * scale + displacement (no base).
    IndexDisp,
    /// No memory operand.
    None,
}

// ============================================================================
// MCInstrFlags — per-instruction flag behavior
// ============================================================================

/// Describes which flags an instruction reads and writes.
#[derive(Debug, Clone, Default)]
pub struct MCInstrFlags {
    /// Flags that are written (defined) by this instruction.
    pub writes: Vec<Flag>,
    /// Flags that are read (used) by this instruction.
    pub reads: Vec<Flag>,
    /// Flags that are implicitly set (even if not in the main semantic).
    pub implicit_sets: Vec<Flag>,
}

impl MCInstrFlags {
    pub fn new() -> Self {
        Self::default()
    }

    pub fn write(mut self, f: Flag) -> Self {
        self.writes.push(f);
        self
    }

    pub fn read(mut self, f: Flag) -> Self {
        self.reads.push(f);
        self
    }

    pub fn implicit(mut self, f: Flag) -> Self {
        self.implicit_sets.push(f);
        self
    }

    /// Returns true if this instruction writes the given flag.
    pub fn writes_flag(&self, f: Flag) -> bool {
        self.writes.contains(&f)
    }

    /// Returns true if this instruction reads the given flag.
    pub fn reads_flag(&self, f: Flag) -> bool {
        self.reads.contains(&f)
    }
}

// ============================================================================
// MCSideEffects — instruction side-effect classification
// ============================================================================

/// Side-effect properties of an instruction.
#[derive(Debug, Clone, Default)]
pub struct MCSideEffects {
    /// Instruction may read from memory.
    pub may_load: bool,
    /// Instruction may write to memory.
    pub may_store: bool,
    /// Instruction has unmodeled side effects (serializing, I/O, etc.).
    pub has_side_effects: bool,
    /// Instruction is a return from subroutine.
    pub is_return: bool,
    /// Instruction is a function call.
    pub is_call: bool,
    /// Instruction is a branch (conditional or unconditional).
    pub is_branch: bool,
    /// Instruction is a basic block terminator.
    pub is_terminator: bool,
    /// Instruction is a scheduling barrier.
    pub is_barrier: bool,
    /// Instruction is an indirect branch.
    pub is_indirect_branch: bool,
    /// Instruction is a compare (sets flags for conditional branch).
    pub is_compare: bool,
    /// Instruction is a move immediate.
    pub is_move_immediate: bool,
    /// Instruction is a bitcast (reinterpret bits without conversion).
    pub is_bitcast: bool,
    /// Instruction is a register-register copy.
    pub is_copy: bool,
}

impl MCSideEffects {
    pub fn new() -> Self {
        Self::default()
    }

    pub fn load(mut self) -> Self {
        self.may_load = true;
        self
    }
    pub fn store(mut self) -> Self {
        self.may_store = true;
        self
    }
    pub fn side_effects(mut self) -> Self {
        self.has_side_effects = true;
        self
    }
    pub fn ret(mut self) -> Self {
        self.is_return = true;
        self.is_terminator = true;
        self.is_barrier = true;
        self
    }
    pub fn call(mut self) -> Self {
        self.is_call = true;
        self.may_store = true;
        self
    }
    pub fn branch(mut self) -> Self {
        self.is_branch = true;
        self.may_load = true;
        self
    }
    pub fn terminator(mut self) -> Self {
        self.is_terminator = true;
        self.is_barrier = true;
        self
    }
    pub fn barrier(mut self) -> Self {
        self.is_barrier = true;
        self
    }
    pub fn indirect_branch(mut self) -> Self {
        self.is_indirect_branch = true;
        self.is_branch = true;
        self.may_load = true;
        self
    }
    pub fn compare(mut self) -> Self {
        self.is_compare = true;
        self
    }
    pub fn move_imm(mut self) -> Self {
        self.is_move_immediate = true;
        self
    }
    pub fn bitcast(mut self) -> Self {
        self.is_bitcast = true;
        self
    }
    pub fn copy(mut self) -> Self {
        self.is_copy = true;
        self
    }
}

// ============================================================================
// EncodingInfo — encoding properties
// ============================================================================

/// Encoding information for an instruction.
#[derive(Debug, Clone)]
pub struct EncodingInfo {
    /// Minimum encoding size in bytes.
    pub min_bytes: u8,
    /// Maximum encoding size in bytes (with all prefixes/displacements).
    pub max_bytes: u8,
    /// Whether the instruction can be relaxed (e.g., JMP short -> near).
    pub can_be_relaxed: bool,
    /// Prefix bytes required (REX, VEX, EVEX, etc.).
    pub prefix_bytes: u8,
    /// Whether this instruction uses ModR/M byte.
    pub has_modrm: bool,
    /// Whether this instruction uses SIB byte.
    pub may_use_sib: bool,
}

impl Default for EncodingInfo {
    fn default() -> Self {
        Self {
            min_bytes: 1,
            max_bytes: 15,
            can_be_relaxed: false,
            prefix_bytes: 0,
            has_modrm: false,
            may_use_sib: false,
        }
    }
}

// ============================================================================
// SchedInfo — per-uarch scheduling information
// ============================================================================

/// Scheduling information for a single microarchitecture.
#[derive(Debug, Clone)]
pub struct UarchSchedInfo {
    /// Total result latency in cycles.
    pub latency: u32,
    /// Number of micro-ops.
    pub uops: u32,
    /// Reciprocal throughput (cycles per instruction when pipelined).
    pub throughput: f64,
    /// Execution ports consumed, with cycle counts.
    pub ports: Vec<(SchedPort, u32)>,
    /// Pipeline stage counts (fetch, decode, dispatch, execute, retire).
    pub pipeline_stages: PipelineStages,
}

/// Pipeline stage cycle counts.
#[derive(Debug, Clone, Default)]
pub struct PipelineStages {
    pub fetch: u32,
    pub decode: u32,
    pub dispatch: u32,
    pub execute: u32,
    pub retire: u32,
}

// ============================================================================
// MCInstrProperties — complete properties for one instruction
// ============================================================================

/// Complete MC-level properties for a single X86 instruction.
#[derive(Debug, Clone)]
pub struct MCInstrProperties {
    /// Instruction mnemonic string.
    pub mnemonic: &'static str,
    /// Numeric opcode identifier.
    pub opcode: u32,
    /// Scheduling info for Skylake Client.
    pub skl_sched: Option<UarchSchedInfo>,
    /// Scheduling info for Zen 4.
    pub zn4_sched: Option<UarchSchedInfo>,
    /// Flag behavior.
    pub flags: MCInstrFlags,
    /// Side-effect classification.
    pub side_effects: MCSideEffects,
    /// Explicit operand types (names of operand classes).
    pub explicit_operands: Vec<&'static str>,
    /// Implicitly defined registers.
    pub implicit_defs: Vec<u16>,
    /// Implicitly used registers.
    pub implicit_uses: Vec<u16>,
    /// Operand constraints (indexed by operand position).
    pub operand_constraints: Vec<OperandConstraint>,
    /// Encoding information.
    pub encoding: EncodingInfo,
    /// Addressing modes supported for memory operands.
    pub addr_modes: Vec<AddrMode>,
    /// Whether this instruction can fold a load into a memory operand.
    pub can_fold_load: bool,
    /// Whether this instruction can fold a store.
    pub can_fold_store: bool,
    /// Whether the instruction is commutative (operands can be swapped).
    pub is_commutative: bool,
    /// Whether this is a conversion instruction (e.g., CVTSI2SD).
    pub is_conversion: bool,
    /// Whether this is a conditional move.
    pub is_conditional_move: bool,
    /// Instruction category for grouping.
    pub category: &'static str,
}

// ============================================================================
// X86MCInstrInfoFull — complete instruction property database
// ============================================================================

/// Complete MC instruction information database.
///
/// Contains detailed properties for 500+ X86 instructions including
/// scheduling, hardware unit usage, flags, side effects, operand info,
/// encoding, memory addressing, and microarchitecture-specific data.
pub struct X86MCInstrInfoFull {
    /// Lookup table: instruction mnemonic -> properties.
    pub by_mnemonic: HashMap<&'static str, MCInstrProperties>,
    /// Lookup table: numeric opcode -> properties.
    pub by_opcode: HashMap<u32, MCInstrProperties>,
    /// All properties in insertion order.
    pub all: Vec<MCInstrProperties>,
}

impl X86MCInstrInfoFull {
    /// Build the complete instruction property database.
    pub fn new() -> Self {
        let all = build_instruction_database();
        let mut by_mnemonic = HashMap::new();
        let mut by_opcode = HashMap::new();

        for props in &all {
            by_mnemonic.insert(props.mnemonic, props.clone());
            by_opcode.insert(props.opcode, props.clone());
        }

        X86MCInstrInfoFull {
            by_mnemonic,
            by_opcode,
            all,
        }
    }

    /// Get instruction properties by mnemonic.
    pub fn lookup(&self, mnemonic: &str) -> Option<&MCInstrProperties> {
        self.by_mnemonic.get(mnemonic)
    }

    /// Get instruction properties by opcode number.
    pub fn lookup_opcode(&self, opcode: u32) -> Option<&MCInstrProperties> {
        self.by_opcode.get(&opcode)
    }

    /// Get the total number of instructions in the database.
    pub fn len(&self) -> usize {
        self.all.len()
    }

    /// Returns true if the database is empty.
    pub fn is_empty(&self) -> bool {
        self.all.is_empty()
    }

    /// Get all instructions in a given category.
    pub fn by_category(&self, category: &str) -> Vec<&MCInstrProperties> {
        self.all.iter().filter(|p| p.category == category).collect()
    }

    /// Get all arithmetic instructions.
    pub fn arithmetic_instructions(&self) -> Vec<&MCInstrProperties> {
        self.by_category("arithmetic")
    }

    /// Get all logical instructions.
    pub fn logical_instructions(&self) -> Vec<&MCInstrProperties> {
        self.by_category("logical")
    }

    /// Get all SIMD instructions.
    pub fn simd_instructions(&self) -> Vec<&MCInstrProperties> {
        self.by_category("simd")
    }

    /// Get all control flow instructions.
    pub fn control_flow_instructions(&self) -> Vec<&MCInstrProperties> {
        self.by_category("control_flow")
    }
}

// ============================================================================
// Instruction Database Builder
// ============================================================================

/// Helper to build scheduling info for Skylake.
fn skl(
    latency: u32,
    uops: u32,
    throughput: f64,
    ports: &[(SchedPort, u32)],
) -> Option<UarchSchedInfo> {
    Some(UarchSchedInfo {
        latency,
        uops,
        throughput,
        ports: ports.to_vec(),
        pipeline_stages: PipelineStages {
            fetch: 1,
            decode: 1,
            dispatch: 1,
            execute: latency,
            retire: 1,
        },
    })
}

/// Helper to build scheduling info for Zen 4.
fn zn4(
    latency: u32,
    uops: u32,
    throughput: f64,
    ports: &[(SchedPort, u32)],
) -> Option<UarchSchedInfo> {
    Some(UarchSchedInfo {
        latency,
        uops,
        throughput,
        ports: ports.to_vec(),
        pipeline_stages: PipelineStages {
            fetch: 1,
            decode: 1,
            dispatch: 1,
            execute: latency,
            retire: 1,
        },
    })
}

/// Convenience: Skylake simple ALU op (1 cycle, 1 uop, 0.25 throughput on p0/p1/p5/p6).
fn skl_alu_simple() -> Option<UarchSchedInfo> {
    skl(
        1,
        1,
        0.25,
        &[
            (SchedPort::Port0, 1),
            (SchedPort::Port1, 1),
            (SchedPort::Port5, 1),
            (SchedPort::Port6, 1),
        ],
    )
}

/// Convenience: Zen 4 simple ALU op (1 cycle, 1 uop, 0.25 throughput).
fn zn4_alu_simple() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.25,
        &[
            (SchedPort::ZenAlu0, 1),
            (SchedPort::ZenAlu1, 1),
            (SchedPort::ZenAlu2, 1),
            (SchedPort::ZenAlu3, 1),
        ],
    )
}

/// Convenience: Skylake load (5 cycle L1 load latency).
fn skl_load() -> Option<UarchSchedInfo> {
    skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)])
}

/// Convenience: Zen 4 load (4 cycle L1 load latency).
fn zn4_load() -> Option<UarchSchedInfo> {
    zn4(
        4,
        1,
        0.5,
        &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
    )
}

/// Convenience: Skylake store (1 cycle store data, store AGU on p4/p7).
fn skl_store() -> Option<UarchSchedInfo> {
    skl(1, 1, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port7, 1)])
}

/// Convenience: Zen 4 store.
fn zn4_store() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.5,
        &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
    )
}

/// Convenience: Skylake load+ALU (address generation LEA-style).
fn skl_load_alu() -> Option<UarchSchedInfo> {
    skl(3, 1, 0.5, &[(SchedPort::Port1, 1), (SchedPort::Port5, 1)])
}

/// Convenience: Zen 4 load+ALU.
fn zn4_load_alu() -> Option<UarchSchedInfo> {
    zn4(
        3,
        1,
        0.5,
        &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
    )
}

/// Convenience: Skylake integer multiply (3-4 cycle).
fn skl_imul() -> Option<UarchSchedInfo> {
    skl(3, 1, 1.0, &[(SchedPort::Port1, 1)])
}

/// Convenience: Zen 4 integer multiply.
fn zn4_imul() -> Option<UarchSchedInfo> {
    zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 1)])
}

/// Convenience: Skylake int divide (32-bit, 20-26 cycle).
fn skl_idiv32() -> Option<UarchSchedInfo> {
    skl(26, 1, 6.0, &[(SchedPort::IntDivider, 26)])
}

/// Convenience: Zen 4 int divide.
fn zn4_idiv32() -> Option<UarchSchedInfo> {
    zn4(22, 1, 6.0, &[(SchedPort::IntDivider, 22)])
}

/// Convenience: Skylake single-precision FP add.
fn skl_fp_add() -> Option<UarchSchedInfo> {
    skl(4, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)])
}

/// Convenience: Zen 4 single-precision FP add.
fn zn4_fp_add() -> Option<UarchSchedInfo> {
    zn4(
        3,
        1,
        0.5,
        &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
    )
}

/// Convenience: Skylake single-precision FP multiply.
fn skl_fp_mul() -> Option<UarchSchedInfo> {
    skl(4, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)])
}

/// Convenience: Zen 4 single-precision FP multiply.
fn zn4_fp_mul() -> Option<UarchSchedInfo> {
    zn4(
        3,
        1,
        0.5,
        &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu2, 1)],
    )
}

/// Convenience: Skylake FP divide (SSE scalar).
fn skl_fp_div_ss() -> Option<UarchSchedInfo> {
    skl(13, 1, 4.0, &[(SchedPort::Port0, 13)])
}

/// Convenience: Zen 4 FP divide (SSE scalar).
fn zn4_fp_div_ss() -> Option<UarchSchedInfo> {
    zn4(11, 1, 4.0, &[(SchedPort::ZenFpu3, 11)])
}

/// Convenience: Skylake SIMD integer add (128-bit).
fn skl_simd_int_add() -> Option<UarchSchedInfo> {
    skl(
        1,
        1,
        0.5,
        &[
            (SchedPort::Port0, 1),
            (SchedPort::Port1, 1),
            (SchedPort::Port5, 1),
        ],
    )
}

/// Convenience: Zen 4 SIMD integer add.
fn zn4_simd_int_add() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.5,
        &[
            (SchedPort::ZenFpu0, 1),
            (SchedPort::ZenFpu1, 1),
            (SchedPort::ZenFpu2, 1),
            (SchedPort::ZenFpu3, 1),
        ],
    )
}

/// Convenience: Skylake SIMD integer multiply (128-bit, PMULLD).
fn skl_simd_int_mul() -> Option<UarchSchedInfo> {
    skl(10, 1, 2.0, &[(SchedPort::Port0, 10)])
}

/// Convenience: Zen 4 SIMD integer multiply.
fn zn4_simd_int_mul() -> Option<UarchSchedInfo> {
    zn4(4, 1, 1.0, &[(SchedPort::ZenFpu0, 4)])
}

/// Convenience: Skylake SIMD shuffle (128-bit).
fn skl_simd_shuffle() -> Option<UarchSchedInfo> {
    skl(1, 1, 1.0, &[(SchedPort::Port5, 1)])
}

/// Convenience: Zen 4 SIMD shuffle.
fn zn4_simd_shuffle() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.5,
        &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
    )
}

/// Convenience: Skylake branch (predicted taken / not taken).
fn skl_branch() -> Option<UarchSchedInfo> {
    skl(1, 1, 0.5, &[(SchedPort::Port6, 1)])
}

/// Convenience: Zen 4 branch.
fn zn4_branch() -> Option<UarchSchedInfo> {
    zn4(1, 1, 0.5, &[(SchedPort::BranchUnit, 1)])
}

/// Convenience: Skylake NOP (zero uops in modern uarchs via register rename).
fn skl_nop() -> Option<UarchSchedInfo> {
    skl(
        0,
        0,
        0.25,
        &[
            (SchedPort::Port0, 1),
            (SchedPort::Port1, 1),
            (SchedPort::Port5, 1),
            (SchedPort::Port6, 1),
        ],
    )
}

/// Convenience: Zen 4 NOP.
fn zn4_nop() -> Option<UarchSchedInfo> {
    zn4(
        0,
        0,
        0.25,
        &[
            (SchedPort::ZenAlu0, 1),
            (SchedPort::ZenAlu1, 1),
            (SchedPort::ZenAlu2, 1),
            (SchedPort::ZenAlu3, 1),
        ],
    )
}

/// Convenience: Skylake cmp/test (flag-setting ALU).
fn skl_cmp() -> Option<UarchSchedInfo> {
    skl(
        1,
        1,
        0.25,
        &[
            (SchedPort::Port0, 1),
            (SchedPort::Port1, 1),
            (SchedPort::Port5, 1),
            (SchedPort::Port6, 1),
        ],
    )
}

/// Convenience: Zen 4 cmp/test.
fn zn4_cmp() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.25,
        &[
            (SchedPort::ZenAlu0, 1),
            (SchedPort::ZenAlu1, 1),
            (SchedPort::ZenAlu2, 1),
            (SchedPort::ZenAlu3, 1),
        ],
    )
}

/// Convenience: Skylake variable-shift (shift by CL).
fn skl_shift_var() -> Option<UarchSchedInfo> {
    skl(2, 2, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)])
}

/// Convenience: Zen 4 variable-shift.
fn zn4_shift_var() -> Option<UarchSchedInfo> {
    zn4(2, 1, 1.0, &[(SchedPort::ZenAlu2, 2)])
}

/// Convenience: Skylake MOVD/MOVQ between GPR and XMM.
fn skl_movd() -> Option<UarchSchedInfo> {
    skl(1, 1, 1.0, &[(SchedPort::Port5, 1)])
}

/// Convenience: Zen 4 MOVD/MOVQ.
fn zn4_movd() -> Option<UarchSchedInfo> {
    zn4(
        1,
        1,
        0.5,
        &[(SchedPort::ZenFpu2, 1), (SchedPort::ZenFpu3, 1)],
    )
}

/// Convenience: Skylake FMA (128-bit, VFMADD132PS).
fn skl_fma128() -> Option<UarchSchedInfo> {
    skl(4, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)])
}

/// Convenience: Zen 4 FMA (128-bit).
fn zn4_fma128() -> Option<UarchSchedInfo> {
    zn4(
        4,
        1,
        0.5,
        &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
    )
}

/// Convenience: Skylake FMA (256-bit).
fn skl_fma256() -> Option<UarchSchedInfo> {
    skl(4, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)])
}

/// Convenience: Zen 4 FMA (256-bit).
fn zn4_fma256() -> Option<UarchSchedInfo> {
    zn4(
        4,
        1,
        0.5,
        &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
    )
}

/// Convenience: Skylake AVX-512 FMA (512-bit).
fn skl_fma512() -> Option<UarchSchedInfo> {
    skl(4, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)])
}

/// Convenience: Zen 4 AVX-512 FMA (512-bit, double-pumped).
fn zn4_fma512() -> Option<UarchSchedInfo> {
    zn4(
        4,
        2,
        1.0,
        &[(SchedPort::ZenFpu0, 2), (SchedPort::ZenFpu1, 2)],
    )
}

// ============================================================================
// Flag helpers
// ============================================================================

/// Flag writes for arithmetic instructions that set all arithmetic flags from result.
fn flag_writes_arith() -> MCInstrFlags {
    MCInstrFlags::new()
        .write(Flag::CF)
        .write(Flag::PF)
        .write(Flag::AF)
        .write(Flag::ZF)
        .write(Flag::SF)
        .write(Flag::OF)
}

/// Flag writes for logical instructions (CF=0, OF=0, AF=undefined).
fn flag_writes_logic() -> MCInstrFlags {
    MCInstrFlags::new()
        .write(Flag::CF)
        .write(Flag::PF)
        .write(Flag::ZF)
        .write(Flag::SF)
        .write(Flag::OF)
}

/// Flag writes for INC/DEC (all except CF).
fn flag_writes_incdec() -> MCInstrFlags {
    MCInstrFlags::new()
        .write(Flag::PF)
        .write(Flag::AF)
        .write(Flag::ZF)
        .write(Flag::SF)
        .write(Flag::OF)
}

/// Flag writes for TEST (CF=0, OF=0, AF=undefined).
fn flag_writes_test() -> MCInstrFlags {
    MCInstrFlags::new()
        .write(Flag::CF)
        .write(Flag::PF)
        .write(Flag::ZF)
        .write(Flag::SF)
        .write(Flag::OF)
}

/// Flag writes for CMP.
fn flag_writes_cmp() -> MCInstrFlags {
    flag_writes_arith()
}

/// No flag effects.
fn flag_none() -> MCInstrFlags {
    MCInstrFlags::new()
}

/// Flag writes for shift instructions.
fn flag_writes_shift() -> MCInstrFlags {
    MCInstrFlags::new()
        .write(Flag::CF)
        .write(Flag::PF)
        .write(Flag::ZF)
        .write(Flag::SF)
        .write(Flag::OF)
}

/// Flag reads for conditional branches (reads all arithmetic flags).
fn flag_reads_cond() -> MCInstrFlags {
    MCInstrFlags::new()
        .read(Flag::CF)
        .read(Flag::PF)
        .read(Flag::AF)
        .read(Flag::ZF)
        .read(Flag::SF)
        .read(Flag::OF)
}

// ============================================================================
// Encoding helpers
// ============================================================================

fn enc_rr(min: u8, max: u8) -> EncodingInfo {
    EncodingInfo {
        min_bytes: min,
        max_bytes: max,
        has_modrm: true,
        ..Default::default()
    }
}

fn enc_rm(min: u8, max: u8) -> EncodingInfo {
    EncodingInfo {
        min_bytes: min,
        max_bytes: max,
        has_modrm: true,
        may_use_sib: true,
        ..Default::default()
    }
}

fn enc_branch_short() -> EncodingInfo {
    EncodingInfo {
        min_bytes: 2,
        max_bytes: 2,
        can_be_relaxed: true,
        ..Default::default()
    }
}

fn enc_branch_near() -> EncodingInfo {
    EncodingInfo {
        min_bytes: 5,
        max_bytes: 6,
        can_be_relaxed: false,
        ..Default::default()
    }
}

fn enc_nop() -> EncodingInfo {
    EncodingInfo {
        min_bytes: 1,
        max_bytes: 9,
        ..Default::default()
    }
}

fn enc_simple() -> EncodingInfo {
    EncodingInfo {
        min_bytes: 1,
        max_bytes: 1,
        ..Default::default()
    }
}

fn enc_ri(min: u8, max: u8) -> EncodingInfo {
    EncodingInfo {
        min_bytes: min,
        max_bytes: max,
        has_modrm: true,
        ..Default::default()
    }
}

fn enc_vex_rr(min: u8, max: u8) -> EncodingInfo {
    EncodingInfo {
        min_bytes: min,
        max_bytes: max,
        prefix_bytes: 2,
        has_modrm: true,
        ..Default::default()
    }
}

fn enc_evex_rr(min: u8, max: u8) -> EncodingInfo {
    EncodingInfo {
        min_bytes: min,
        max_bytes: max,
        prefix_bytes: 4,
        has_modrm: true,
        ..Default::default()
    }
}

// ============================================================================
// Operand name constants
// ============================================================================

const OP_R8: &str = "r8";
const OP_R16: &str = "r16";
const OP_R32: &str = "r32";
const OP_R64: &str = "r64";
const OP_M8: &str = "m8";
const OP_M16: &str = "m16";
const OP_M32: &str = "m32";
const OP_M64: &str = "m64";
const OP_M128: &str = "m128";
const OP_M256: &str = "m256";
const OP_M512: &str = "m512";
const OP_I8: &str = "i8";
const OP_I16: &str = "i16";
const OP_I32: &str = "i32";
const OP_I64: &str = "i64";
const OP_REL8: &str = "rel8";
const OP_REL32: &str = "rel32";
const OP_XMM: &str = "xmm";
const OP_YMM: &str = "ymm";
const OP_ZMM: &str = "zmm";
const OP_K: &str = "k";
const OP_MM: &str = "mm";

// ============================================================================
// Register number constants (physical register IDs as u16)
// ============================================================================

const R_EFLAGS: u16 = 300;
const R_RAX: u16 = RAX;
const R_RCX: u16 = RCX;
const R_RDX: u16 = RDX;
const R_RSP: u16 = RSP;
const R_EAX: u16 = EAX;
const R_EBX: u16 = EBX;
const R_ECX: u16 = ECX;
const R_EDX: u16 = EDX;

// ============================================================================
// build_instruction_database — the main instruction property table
// ============================================================================

fn build_instruction_database() -> Vec<MCInstrProperties> {
    vec![
        // ====================================================================
        // NOP / Misc
        // ====================================================================
        MCInstrProperties {
            mnemonic: "NOP",
            opcode: 0,
            skl_sched: skl_nop(),
            zn4_sched: zn4_nop(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: enc_nop(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "misc",
        },
        MCInstrProperties {
            mnemonic: "INT3",
            opcode: 1000,
            skl_sched: skl(100, 1, 100.0, &[(SchedPort::Port0, 100)]),
            zn4_sched: zn4(100, 1, 100.0, &[(SchedPort::ZenAlu0, 100)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier().terminator(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "misc",
        },
        MCInstrProperties {
            mnemonic: "UD2",
            opcode: 1001,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 1.0, &[(SchedPort::ZenAlu0, 1)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier().terminator(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 2,
                max_bytes: 2,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "misc",
        },
        // ====================================================================
        // Data Movement — MOV variants
        // ====================================================================
        MCInstrProperties {
            mnemonic: "MOV32rr",
            opcode: 1,
            skl_sched: skl(
                1,
                1,
                0.25,
                &[
                    (SchedPort::Port0, 1),
                    (SchedPort::Port1, 1),
                    (SchedPort::Port5, 1),
                    (SchedPort::Port6, 1),
                ],
            ),
            zn4_sched: zn4_alu_simple(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().copy(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV64rr",
            opcode: 2,
            skl_sched: skl(
                1,
                1,
                0.25,
                &[
                    (SchedPort::Port0, 1),
                    (SchedPort::Port1, 1),
                    (SchedPort::Port5, 1),
                    (SchedPort::Port6, 1),
                ],
            ),
            zn4_sched: zn4_alu_simple(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().copy(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV32rm",
            opcode: 3,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
                AddrMode::Absolute,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV64rm",
            opcode: 4,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R64, OP_M64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(3, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
                AddrMode::Absolute,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV32mr",
            opcode: 5,
            skl_sched: skl_store(),
            zn4_sched: zn4_store(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_M32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV64mr",
            opcode: 6,
            skl_sched: skl_store(),
            zn4_sched: zn4_store(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_M64, OP_R64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(3, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV32ri",
            opcode: 7,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().move_imm(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(5, 8),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV64ri",
            opcode: 8,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().move_imm(),
            explicit_operands: vec![OP_R64, OP_I64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(7, 10),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOV32mi",
            opcode: 9,
            skl_sched: skl(2, 2, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port7, 1)]),
            zn4_sched: zn4(
                1,
                2,
                0.5,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store().move_imm(),
            explicit_operands: vec![OP_M32, OP_I32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(5, 12),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // MOVSX (sign extension)
        MCInstrProperties {
            mnemonic: "MOVSX32rr8",
            opcode: 10,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOVSX64rr32",
            opcode: 11,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOVSX32rm8",
            opcode: 12,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "data_movement",
        },
        // MOVZX (zero extension)
        MCInstrProperties {
            mnemonic: "MOVZX32rr8",
            opcode: 13,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "MOVZX32rm8",
            opcode: 14,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "data_movement",
        },
        // LEA
        MCInstrProperties {
            mnemonic: "LEA32r",
            opcode: 15,
            skl_sched: skl_load_alu(),
            zn4_sched: zn4_load_alu(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::IndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "LEA64r",
            opcode: 16,
            skl_sched: skl_load_alu(),
            zn4_sched: zn4_load_alu(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_M64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(3, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
                AddrMode::IndexDisp,
            ],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // XCHG
        MCInstrProperties {
            mnemonic: "XCHG32rr",
            opcode: 17,
            skl_sched: skl(
                2,
                3,
                1.5,
                &[
                    (SchedPort::Port0, 1),
                    (SchedPort::Port1, 1),
                    (SchedPort::Port5, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                3,
                1.5,
                &[
                    (SchedPort::ZenAlu0, 1),
                    (SchedPort::ZenAlu1, 1),
                    (SchedPort::ZenAlu2, 1),
                ],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::TiedToDef(1),
            ],
            encoding: enc_rr(1, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // CMOVcc (conditional moves)
        MCInstrProperties {
            mnemonic: "CMOV32rr",
            opcode: 18,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: MCInstrFlags::new()
                .read(Flag::CF)
                .read(Flag::ZF)
                .read(Flag::SF)
                .read(Flag::OF)
                .read(Flag::PF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: true,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "CMOV64rr",
            opcode: 19,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: MCInstrFlags::new()
                .read(Flag::CF)
                .read(Flag::ZF)
                .read(Flag::SF)
                .read(Flag::OF)
                .read(Flag::PF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: true,
            category: "data_movement",
        },
        // ====================================================================
        // Arithmetic — ADD, ADC, SUB, SBB
        // ====================================================================
        MCInstrProperties {
            mnemonic: "ADD32rr",
            opcode: 100,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD64rr",
            opcode: 101,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD32rm",
            opcode: 102,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD32ri",
            opcode: 103,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD32mi",
            opcode: 104,
            skl_sched: skl(
                2,
                2,
                0.5,
                &[
                    (SchedPort::Port2, 1),
                    (SchedPort::Port3, 1),
                    (SchedPort::Port4, 1),
                    (SchedPort::Port7, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                2,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu2, 1)],
            ),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load().store(),
            explicit_operands: vec![OP_M32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 12),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADC32rr",
            opcode: 105,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(1, 1, 1.0, &[(SchedPort::ZenAlu0, 1)]),
            flags: flag_writes_arith().read(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB32rr",
            opcode: 110,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB64rr",
            opcode: 111,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB32rm",
            opcode: 112,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB32ri",
            opcode: 113,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SBB32rr",
            opcode: 115,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(1, 1, 1.0, &[(SchedPort::ZenAlu0, 1)]),
            flags: flag_writes_arith().read(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        // ====================================================================
        // Arithmetic — MUL, IMUL, DIV, IDIV
        // ====================================================================
        MCInstrProperties {
            mnemonic: "MUL32r",
            opcode: 120,
            skl_sched: skl_imul(),
            zn4_sched: zn4_imul(),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EDX, R_EAX, R_EFLAGS],
            implicit_uses: vec![R_EAX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "IMUL32rr",
            opcode: 121,
            skl_sched: skl_imul(),
            zn4_sched: zn4_imul(),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "IMUL64rr",
            opcode: 122,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "IMUL32rri",
            opcode: 123,
            skl_sched: skl_imul(),
            zn4_sched: zn4_imul(),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(-2147483648, 2147483647),
            ],
            encoding: enc_ri(3, 7),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "DIV32r",
            opcode: 125,
            skl_sched: skl_idiv32(),
            zn4_sched: zn4_idiv32(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EAX, R_EDX],
            implicit_uses: vec![R_EAX, R_EDX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "IDIV32r",
            opcode: 126,
            skl_sched: skl_idiv32(),
            zn4_sched: zn4_idiv32(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EAX, R_EDX],
            implicit_uses: vec![R_EAX, R_EDX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        // ====================================================================
        // INC / DEC / NEG
        // ====================================================================
        MCInstrProperties {
            mnemonic: "INC32r",
            opcode: 130,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_incdec(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(1, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "INC64r",
            opcode: 131,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_incdec(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR64")],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "DEC32r",
            opcode: 132,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_incdec(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(1, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "NEG32r",
            opcode: 134,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith().read(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        // ====================================================================
        // Logical — AND, OR, XOR, NOT, TEST
        // ====================================================================
        MCInstrProperties {
            mnemonic: "AND32rr",
            opcode: 200,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "AND64rr",
            opcode: 201,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "AND32rm",
            opcode: 202,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "AND32ri",
            opcode: 203,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR32rr",
            opcode: 210,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR64rr",
            opcode: 211,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR32rm",
            opcode: 212,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR32ri",
            opcode: 213,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "XOR32rr",
            opcode: 220,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "XOR64rr",
            opcode: 221,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "NOT32r",
            opcode: 225,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "TEST32rr",
            opcode: 230,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_test(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "TEST64rr",
            opcode: 231,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_test(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "TEST32ri",
            opcode: 232,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_test(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        // ====================================================================
        // Compare — CMP
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CMP32rr",
            opcode: 300,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_cmp(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "CMP64rr",
            opcode: 301,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_cmp(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R64, OP_R64],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "CMP32rm",
            opcode: 302,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_cmp(),
            side_effects: MCSideEffects::new().load().compare(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "CMP32ri",
            opcode: 303,
            skl_sched: skl_cmp(),
            zn4_sched: zn4_cmp(),
            flags: flag_writes_cmp(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_R32, OP_I32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        // ====================================================================
        // Shifts and Rotates — SHL, SHR, SAR, ROL, ROR
        // ====================================================================
        MCInstrProperties {
            mnemonic: "SHL32r1",
            opcode: 400,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHL64r1",
            opcode: 401,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R64, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHL32rCL",
            opcode: 402,
            skl_sched: skl_shift_var(),
            zn4_sched: zn4_shift_var(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_RCX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHL32ri",
            opcode: 403,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(0, 255)],
            encoding: enc_ri(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHR32r1",
            opcode: 410,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHR32rCL",
            opcode: 411,
            skl_sched: skl_shift_var(),
            zn4_sched: zn4_shift_var(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_RCX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SHR32ri",
            opcode: 412,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(0, 255)],
            encoding: enc_ri(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SAR32r1",
            opcode: 420,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "SAR32rCL",
            opcode: 421,
            skl_sched: skl_shift_var(),
            zn4_sched: zn4_shift_var(),
            flags: flag_writes_shift(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_RCX],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "ROL32r1",
            opcode: 430,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        MCInstrProperties {
            mnemonic: "ROR32r1",
            opcode: 431,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::ImmRange(1, 1)],
            encoding: enc_ri(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "shift_rotate",
        },
        // ====================================================================
        // PUSH / POP
        // ====================================================================
        MCInstrProperties {
            mnemonic: "PUSH32r",
            opcode: 500,
            skl_sched: skl(2, 2, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                1,
                2,
                0.5,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(1, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "PUSH64r",
            opcode: 501,
            skl_sched: skl(2, 2, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                1,
                2,
                0.5,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_R64],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![OperandConstraint::RegClass("GR64")],
            encoding: enc_rr(1, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "POP32r",
            opcode: 502,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(1, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "POP64r",
            opcode: 503,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R64],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![OperandConstraint::RegClass("GR64")],
            encoding: enc_rr(1, 2),
            addr_modes: vec![AddrMode::None],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // ====================================================================
        // Control Flow — JMP, Jcc, CALL, RET
        // ====================================================================
        MCInstrProperties {
            mnemonic: "JMP_1",
            opcode: 600,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().branch().terminator().barrier(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JMP_4",
            opcode: 601,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().branch().terminator().barrier(),
            explicit_operands: vec![OP_REL32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_near(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        // Conditional branches (JE, JNE, etc.)
        MCInstrProperties {
            mnemonic: "JE_1",
            opcode: 610,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JE_4",
            opcode: 611,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL32],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_near(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JNE_1",
            opcode: 612,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JL_1",
            opcode: 614,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::SF).read(Flag::OF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JLE_1",
            opcode: 615,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new()
                .read(Flag::SF)
                .read(Flag::OF)
                .read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JG_1",
            opcode: 616,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new()
                .read(Flag::SF)
                .read(Flag::OF)
                .read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JGE_1",
            opcode: 617,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::SF).read(Flag::OF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JB_1",
            opcode: 618,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::CF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JBE_1",
            opcode: 619,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::CF).read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JA_1",
            opcode: 620,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::CF).read(Flag::ZF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JO_1",
            opcode: 622,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::OF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JS_1",
            opcode: 623,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::SF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "JP_1",
            opcode: 624,
            skl_sched: skl_branch(),
            zn4_sched: zn4_branch(),
            flags: MCInstrFlags::new().read(Flag::PF),
            side_effects: MCSideEffects::new().branch().terminator(),
            explicit_operands: vec![OP_REL8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None],
            encoding: enc_branch_short(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        // CALL / RET
        MCInstrProperties {
            mnemonic: "CALLpcrel32",
            opcode: 630,
            skl_sched: skl(
                2,
                3,
                1.0,
                &[
                    (SchedPort::Port6, 1),
                    (SchedPort::Port4, 1),
                    (SchedPort::Port3, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                3,
                1.0,
                &[
                    (SchedPort::ZenAgu2, 1),
                    (SchedPort::ZenAgu3, 1),
                    (SchedPort::BranchUnit, 1),
                ],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().call(),
            explicit_operands: vec![OP_REL32],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 5,
                max_bytes: 5,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        MCInstrProperties {
            mnemonic: "RETQ",
            opcode: 631,
            skl_sched: skl(5, 2, 1.0, &[(SchedPort::Port6, 1), (SchedPort::Port2, 1)]),
            zn4_sched: zn4(
                5,
                2,
                1.0,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::BranchUnit, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().ret(),
            explicit_operands: vec![],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 1,
                max_bytes: 1,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        // ====================================================================
        // SETcc — conditional set byte
        // ====================================================================
        MCInstrProperties {
            mnemonic: "SETEr",
            opcode: 700,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new().read(Flag::ZF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::RegClass("GR8")],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        MCInstrProperties {
            mnemonic: "SETNEr",
            opcode: 701,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new().read(Flag::ZF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8],
            implicit_defs: vec![],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::RegClass("GR8")],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // ====================================================================
        // SSE — MOVSS, MOVSD, MOVAPS, MOVUPS, MOVDQA, MOVDQU
        // ====================================================================
        MCInstrProperties {
            mnemonic: "MOVSSrr",
            opcode: 800,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSSrm",
            opcode: 801,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSSmr",
            opcode: 802,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port7, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_M32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSDrr",
            opcode: 810,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSDrm",
            opcode: 811,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVAPSrr",
            opcode: 820,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVAPSrm",
            opcode: 821,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M128],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVUPSrm",
            opcode: 822,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M128],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVDQArr",
            opcode: 830,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVDQArm",
            opcode: 831,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M128],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE — Scalar FP arithmetic: ADDSS, SUBSS, MULSS, DIVSS, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "ADDSSrr",
            opcode: 900,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "ADDSSrm",
            opcode: 901,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "ADDSDrr",
            opcode: 902,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SUBSSrr",
            opcode: 910,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SUBSDrr",
            opcode: 911,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MULSSrr",
            opcode: 920,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MULSDrr",
            opcode: 921,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "DIVSSrr",
            opcode: 930,
            skl_sched: skl_fp_div_ss(),
            zn4_sched: zn4_fp_div_ss(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "DIVSDrr",
            opcode: 931,
            skl_sched: skl(20, 1, 8.0, &[(SchedPort::Port0, 20)]),
            zn4_sched: zn4(18, 1, 8.0, &[(SchedPort::ZenFpu3, 18)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SQRTSSr",
            opcode: 940,
            skl_sched: skl(12, 1, 6.0, &[(SchedPort::Port0, 12)]),
            zn4_sched: zn4(10, 1, 6.0, &[(SchedPort::ZenFpu3, 10)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SQRTSDr",
            opcode: 941,
            skl_sched: skl(18, 1, 10.0, &[(SchedPort::Port0, 18)]),
            zn4_sched: zn4(16, 1, 10.0, &[(SchedPort::ZenFpu3, 16)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE — Comparison: CMPSS, CMPSD, COMISS, COMISD, UCOMISS, UCOMISD
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CMPSSrr",
            opcode: 950,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(2, 1, 1.0, &[(SchedPort::ZenFpu0, 2)]),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 7),
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "UCOMISSrr",
            opcode: 951,
            skl_sched: skl(2, 1, 1.0, &[(SchedPort::Port0, 2)]),
            zn4_sched: zn4(2, 1, 1.0, &[(SchedPort::ZenFpu0, 2)]),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE — Packed FP arithmetic: ADDPS, SUBPS, MULPS, DIVPS, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "ADDPSrr",
            opcode: 1000,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MULPSrr",
            opcode: 1010,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "ADDPDrr",
            opcode: 1020,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MULPDrr",
            opcode: 1021,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE — Conversions: CVTSI2SS, CVTSI2SD, CVTSS2SI, CVTSD2SI, CVTT*
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CVTSI2SSrr",
            opcode: 1100,
            skl_sched: skl(4, 1, 1.0, &[(SchedPort::Port1, 4)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSI2SDrr",
            opcode: 1101,
            skl_sched: skl(4, 1, 1.0, &[(SchedPort::Port1, 4)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSI642SSrr",
            opcode: 1102,
            skl_sched: skl(4, 1, 1.0, &[(SchedPort::Port1, 4)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_R64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSS2SIrr",
            opcode: 1110,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSD2SIrr",
            opcode: 1111,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTTSD2SIrr",
            opcode: 1112,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSS2SDrr",
            opcode: 1120,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "CVTSD2SSrr",
            opcode: 1121,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: true,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE — Integer SIMD: PADDB/W/D/Q, PSUBB/W/D/Q, PMULLD, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "PADDDrr",
            opcode: 1200,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PADDWrr",
            opcode: 1201,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PADDBrr",
            opcode: 1202,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PADDQrr",
            opcode: 1203,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PSUBDrr",
            opcode: 1210,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMULLDrr",
            opcode: 1220,
            skl_sched: skl_simd_int_mul(),
            zn4_sched: zn4_simd_int_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMULLWrr",
            opcode: 1221,
            skl_sched: skl(5, 1, 1.0, &[(SchedPort::Port0, 5)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // PAND / POR / PXOR / PANDN
        MCInstrProperties {
            mnemonic: "PANDrr",
            opcode: 1230,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PORrr",
            opcode: 1231,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PXORrr",
            opcode: 1232,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PANDNrr",
            opcode: 1233,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // PMIN / PMAX variants
        MCInstrProperties {
            mnemonic: "PMINSDrr",
            opcode: 1240,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMAXSDrr",
            opcode: 1241,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // AVX — 256-bit versions of packed operations
        // ====================================================================
        MCInstrProperties {
            mnemonic: "VADDPSYrr",
            opcode: 1300,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VMULPSYrr",
            opcode: 1301,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VADDPDYrr",
            opcode: 1302,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // AVX — MOVD/MOVQ between GPR and XMM/YMM
        // ====================================================================
        MCInstrProperties {
            mnemonic: "VMOVDrr",
            opcode: 1310,
            skl_sched: skl_movd(),
            zn4_sched: zn4_movd(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().bitcast(),
            explicit_operands: vec![OP_XMM, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VMOVDrm",
            opcode: 1311,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load().bitcast(),
            explicit_operands: vec![OP_XMM, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VMOVDmr",
            opcode: 1312,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port4, 1), (SchedPort::Port7, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenAgu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store().bitcast(),
            explicit_operands: vec![OP_M32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::Absolute,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // AVX — Integer SIMD 256-bit
        // ====================================================================
        MCInstrProperties {
            mnemonic: "VPADDDrr",
            opcode: 1350,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPADDDYrr",
            opcode: 1351,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // FMA — VFMADD132PS/PD/SS/SD and variants
        // ====================================================================
        MCInstrProperties {
            mnemonic: "VFMADD132PSr",
            opcode: 1400,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD213PSr",
            opcode: 1401,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD231PSr",
            opcode: 1402,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD132PSYr",
            opcode: 1410,
            skl_sched: skl_fma256(),
            zn4_sched: zn4_fma256(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD132PDr",
            opcode: 1411,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD132SSr",
            opcode: 1412,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // FMA — FNMADD, FMSUB, FNMSUB variants
        MCInstrProperties {
            mnemonic: "VFNMADD132PSr",
            opcode: 1420,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMSUB132PSr",
            opcode: 1421,
            skl_sched: skl_fma128(),
            zn4_sched: zn4_fma128(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // BMI / BMI2 — BEXTR, BLSI, BLSMSK, BLSR, BZHI, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "ANDN32rr",
            opcode: 1500,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "BLSI32rr",
            opcode: 1501,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "BLSMSK32rr",
            opcode: 1502,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "BLSR32rr",
            opcode: 1503,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "BEXTR32rr",
            opcode: 1504,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                1.0,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        // BMI2 — BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX
        MCInstrProperties {
            mnemonic: "BZHI32rr",
            opcode: 1510,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                1.0,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "MULX32rr",
            opcode: 1511,
            skl_sched: skl_imul(),
            zn4_sched: zn4_imul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "PDEP32rr",
            opcode: 1512,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "PEXT32rr",
            opcode: 1513,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        MCInstrProperties {
            mnemonic: "SHLX32rr",
            opcode: 1514,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bmi",
        },
        // ====================================================================
        // AVX-512 — ZMM operations with EVEX encoding
        // ====================================================================
        MCInstrProperties {
            mnemonic: "VADDPSZrr",
            opcode: 2000,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VADDPSZrrk",
            opcode: 2001,
            skl_sched: skl_fp_add(),
            zn4_sched: zn4_fp_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_K, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VMULPSZrr",
            opcode: 2002,
            skl_sched: skl_fp_mul(),
            zn4_sched: zn4_fp_mul(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VFMADD132PSZr",
            opcode: 2010,
            skl_sched: skl_fma512(),
            zn4_sched: zn4_fma512(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // AVX-512 — VPADDD ZMM
        MCInstrProperties {
            mnemonic: "VPADDDZrr",
            opcode: 2020,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // Shuffles — PSHUFD, PSHUFB, SHUFPS, SHUFPD, UNPCK*, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "PSHUFDrr",
            opcode: 1600,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PSHUFBrr",
            opcode: 1601,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SHUFPSrr",
            opcode: 1610,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "UNPCKLPSrr",
            opcode: 1620,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // System instructions — CPUID, RDTSC, MFENCE, LFENCE, SFENCE
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CPUID",
            opcode: 2500,
            skl_sched: skl(100, 1, 100.0, &[(SchedPort::Port0, 100)]),
            zn4_sched: zn4(100, 1, 100.0, &[(SchedPort::ZenAlu0, 100)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EAX, R_EBX, R_ECX, R_EDX],
            implicit_uses: vec![R_EAX, R_ECX],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 2,
                max_bytes: 2,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "RDTSC",
            opcode: 2501,
            skl_sched: skl(25, 2, 10.0, &[(SchedPort::Port0, 25)]),
            zn4_sched: zn4(20, 2, 10.0, &[(SchedPort::ZenAlu0, 20)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EAX, R_EDX],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 2,
                max_bytes: 2,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "MFENCE",
            opcode: 2502,
            skl_sched: skl(33, 1, 33.0, &[(SchedPort::Port2, 33)]),
            zn4_sched: zn4(33, 1, 33.0, &[(SchedPort::ZenAgu0, 33)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 3,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "LFENCE",
            opcode: 2503,
            skl_sched: skl(5, 1, 5.0, &[(SchedPort::Port2, 5)]),
            zn4_sched: zn4(5, 1, 5.0, &[(SchedPort::ZenAgu0, 5)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 3,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "SFENCE",
            opcode: 2504,
            skl_sched: skl(7, 1, 7.0, &[(SchedPort::Port4, 7)]),
            zn4_sched: zn4(7, 1, 7.0, &[(SchedPort::ZenAgu2, 7)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects().barrier(),
            explicit_operands: vec![],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 3,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        // ====================================================================
        // Flag instructions — STC, CLC, CMC, CLD, STD, LAHF, SAHF, PUSHF, POPF
        // ====================================================================
        MCInstrProperties {
            mnemonic: "STC",
            opcode: 2600,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: MCInstrFlags::new().write(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "CLC",
            opcode: 2601,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: MCInstrFlags::new().write(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "CMC",
            opcode: 2602,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: MCInstrFlags::new().write(Flag::CF).read(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "LAHF",
            opcode: 2603,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 1.0, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new()
                .read(Flag::CF)
                .read(Flag::PF)
                .read(Flag::AF)
                .read(Flag::ZF)
                .read(Flag::SF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![AH],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "SAHF",
            opcode: 2604,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 1.0, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new()
                .write(Flag::CF)
                .write(Flag::PF)
                .write(Flag::AF)
                .write(Flag::ZF)
                .write(Flag::SF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![AH],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "PUSHF32",
            opcode: 2605,
            skl_sched: skl(
                2,
                3,
                1.0,
                &[
                    (SchedPort::Port4, 1),
                    (SchedPort::Port7, 1),
                    (SchedPort::Port3, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                3,
                1.0,
                &[
                    (SchedPort::ZenAgu2, 1),
                    (SchedPort::ZenAgu3, 1),
                    (SchedPort::ZenAlu0, 1),
                ],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP, R_EFLAGS],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "POPF32",
            opcode: 2606,
            skl_sched: skl(
                5,
                3,
                2.0,
                &[
                    (SchedPort::Port2, 1),
                    (SchedPort::Port3, 1),
                    (SchedPort::Port0, 1),
                ],
            ),
            zn4_sched: zn4(
                4,
                3,
                2.0,
                &[
                    (SchedPort::ZenAgu0, 1),
                    (SchedPort::ZenAgu1, 1),
                    (SchedPort::ZenAlu0, 1),
                ],
            ),
            flags: MCInstrFlags::new()
                .write(Flag::CF)
                .write(Flag::PF)
                .write(Flag::AF)
                .write(Flag::ZF)
                .write(Flag::SF)
                .write(Flag::OF)
                .write(Flag::DF)
                .write(Flag::IF),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![],
            implicit_defs: vec![R_RSP, R_EFLAGS],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        // ====================================================================
        // CMPXCHG / CMPXCHG8B / CMPXCHG16B — atomic compare-and-exchange
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CMPXCHG32rr",
            opcode: 2700,
            skl_sched: skl(
                2,
                2,
                1.0,
                &[
                    (SchedPort::Port2, 1),
                    (SchedPort::Port3, 1),
                    (SchedPort::Port4, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                2,
                1.0,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu2, 1)],
            ),
            flags: flag_writes_arith()
                .read(Flag::CF)
                .read(Flag::ZF)
                .read(Flag::SF)
                .read(Flag::OF)
                .read(Flag::PF)
                .read(Flag::AF),
            side_effects: MCSideEffects::new().load().store(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS, R_EAX],
            implicit_uses: vec![R_EAX, R_EFLAGS],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "atomic",
        },
        MCInstrProperties {
            mnemonic: "CMPXCHG8B",
            opcode: 2701,
            skl_sched: skl(
                15,
                3,
                5.0,
                &[
                    (SchedPort::Port2, 3),
                    (SchedPort::Port3, 3),
                    (SchedPort::Port4, 3),
                ],
            ),
            zn4_sched: zn4(
                15,
                3,
                5.0,
                &[(SchedPort::ZenAgu0, 3), (SchedPort::ZenAgu2, 3)],
            ),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load().store().side_effects(),
            explicit_operands: vec![OP_M64],
            implicit_defs: vec![R_EFLAGS, R_EAX, R_EDX],
            implicit_uses: vec![R_EAX, R_EDX, R_EBX, R_ECX],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 4,
                max_bytes: 9,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "atomic",
        },
        // ====================================================================
        // XADD — atomic exchange and add
        // ====================================================================
        MCInstrProperties {
            mnemonic: "XADD32rr",
            opcode: 2750,
            skl_sched: skl(
                2,
                2,
                1.0,
                &[
                    (SchedPort::Port2, 1),
                    (SchedPort::Port3, 1),
                    (SchedPort::Port4, 1),
                ],
            ),
            zn4_sched: zn4(
                2,
                2,
                1.0,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu2, 1)],
            ),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load().store(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "atomic",
        },
        // ====================================================================
        // BSWAP — byte swap
        // ====================================================================
        MCInstrProperties {
            mnemonic: "BSWAP32r",
            opcode: 2800,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port1, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenAlu0, 1), (SchedPort::ZenAlu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // ====================================================================
        // MOVBE — byte-order-swapping move (Atom)
        // ====================================================================
        MCInstrProperties {
            mnemonic: "MOVBE32rm",
            opcode: 2850,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R32, OP_M32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(4, 9),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
                AddrMode::RIPRelative,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "data_movement",
        },
        // ====================================================================
        // SSE4.1 — PBLENDVB, BLENDVPS, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "BLENDVPSrr0",
            opcode: 1650,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![XMM0],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PBLENDVBrr0",
            opcode: 1651,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![XMM0],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE4.1 — PMULLD, PMULDQ, etc.
        // ====================================================================
        MCInstrProperties {
            mnemonic: "PMULDQrr",
            opcode: 1660,
            skl_sched: skl(5, 1, 1.0, &[(SchedPort::Port0, 5)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // SSE4.2 — CRC32
        // ====================================================================
        MCInstrProperties {
            mnemonic: "CRC32r32r32",
            opcode: 1700,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ====================================================================
        // LZCNT / TZCNT / POPCNT
        // ====================================================================
        MCInstrProperties {
            mnemonic: "LZCNT32rr",
            opcode: 2900,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::ZF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bitmanip",
        },
        MCInstrProperties {
            mnemonic: "TZCNT32rr",
            opcode: 2901,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: MCInstrFlags::new().write(Flag::CF).write(Flag::ZF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bitmanip",
        },
        MCInstrProperties {
            mnemonic: "POPCNT32rr",
            opcode: 2902,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port1, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenAlu1, 3)]),
            flags: flag_writes_logic().read(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "bitmanip",
        },
        // ====================================================================
        // IRET — interrupt return
        // ====================================================================
        MCInstrProperties {
            mnemonic: "IRET32",
            opcode: 3000,
            skl_sched: skl(20, 5, 10.0, &[(SchedPort::Port2, 5), (SchedPort::Port3, 5)]),
            zn4_sched: zn4(
                20,
                5,
                10.0,
                &[(SchedPort::ZenAgu0, 5), (SchedPort::ZenAgu1, 5)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().ret(),
            explicit_operands: vec![],
            implicit_defs: vec![R_RSP],
            implicit_uses: vec![R_RSP],
            operand_constraints: vec![],
            encoding: enc_simple(),
            addr_modes: vec![AddrMode::None],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "control_flow",
        },
        // ================================================================
        // Additional Integer Arithmetic — 8/16-bit variants
        // ================================================================
        MCInstrProperties {
            mnemonic: "ADD8rr",
            opcode: 3001,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_R8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD16rr",
            opcode: 3002,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R16, OP_R16],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB8rr",
            opcode: 3003,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_R8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB16rr",
            opcode: 3004,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R16, OP_R16],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "AND8rr",
            opcode: 3005,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_R8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "AND16rr",
            opcode: 3006,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R16, OP_R16],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR8rr",
            opcode: 3007,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_R8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "OR16rr",
            opcode: 3008,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R16, OP_R16],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "XOR8rr",
            opcode: 3009,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_R8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(2, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        MCInstrProperties {
            mnemonic: "XOR16rr",
            opcode: 3010,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R16, OP_R16],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(3, 3),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        // ================================================================
        // Additional Integer Arithmetic — memory variants
        // ================================================================
        MCInstrProperties {
            mnemonic: "ADD8rm",
            opcode: 3020,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R8, OP_M8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADD8ri",
            opcode: 3021,
            skl_sched: skl_alu_simple(),
            zn4_sched: zn4_alu_simple(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R8, OP_I8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_ri(2, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "SUB8rm",
            opcode: 3022,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R8, OP_M8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "AND8rm",
            opcode: 3023,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_R8, OP_M8],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(2, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "logical",
        },
        // ================================================================
        // Additional SSE/SSE2 — Integer SIMD 128-bit
        // ================================================================
        MCInstrProperties {
            mnemonic: "PCMPEQDrr",
            opcode: 3100,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PCMPGTDrr",
            opcode: 3101,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PCMPEQBWrr",
            opcode: 3102,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PACKSSDWrr",
            opcode: 3103,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PACKSSWBrr",
            opcode: 3104,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PUNPCKLDQrr",
            opcode: 3105,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PUNPCKHDQrr",
            opcode: 3106,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // SSE3 — HADDPS, HSUBPS, ADDSUBPS, MOVSHDUP, MOVSLDUP
        // ================================================================
        MCInstrProperties {
            mnemonic: "HADDPSrr",
            opcode: 3200,
            skl_sched: skl(
                5,
                3,
                2.0,
                &[
                    (SchedPort::Port0, 1),
                    (SchedPort::Port1, 1),
                    (SchedPort::Port5, 1),
                ],
            ),
            zn4_sched: zn4(
                4,
                2,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "HSUBPSrr",
            opcode: 3201,
            skl_sched: skl(
                5,
                3,
                2.0,
                &[
                    (SchedPort::Port0, 1),
                    (SchedPort::Port1, 1),
                    (SchedPort::Port5, 1),
                ],
            ),
            zn4_sched: zn4(
                4,
                2,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "ADDSUBPSrr",
            opcode: 3202,
            skl_sched: skl(3, 2, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                3,
                2,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSHDUPrm",
            opcode: 3203,
            skl_sched: skl_load(),
            zn4_sched: zn4_load(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M128],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 8),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "MOVSLDUPrr",
            opcode: 3204,
            skl_sched: skl_simd_shuffle(),
            zn4_sched: zn4_simd_shuffle(),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(3, 4),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // SSSE3 — PALIGNR, PHADDW, PHSUBD, PMADDUBSW, PSIGNB, PABSD
        // ================================================================
        MCInstrProperties {
            mnemonic: "PALIGNRrri",
            opcode: 3300,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PHADDWrr",
            opcode: 3301,
            skl_sched: skl(3, 2, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                3,
                2,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PHSUBDrr",
            opcode: 3302,
            skl_sched: skl(3, 2, 1.0, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                3,
                2,
                1.0,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMADDUBSWrr",
            opcode: 3303,
            skl_sched: skl(5, 1, 1.0, &[(SchedPort::Port0, 5)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PSIGNBrr",
            opcode: 3304,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PABSDrr",
            opcode: 3305,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenFpu0, 1)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // SSE4.1 — PBLENDW, PMINSB, PMAXUW, PACKUSDW, PMULDQ
        // ================================================================
        MCInstrProperties {
            mnemonic: "PBLENDWrri",
            opcode: 3400,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMINSBrr",
            opcode: 3401,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PMAXUWrr",
            opcode: 3402,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port1, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu0, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PACKUSDWrr",
            opcode: 3403,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "EXTRACTPSrr",
            opcode: 3404,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(2, 1, 1.0, &[(SchedPort::ZenFpu0, 2)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 3),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "INSERTPSrr",
            opcode: 3405,
            skl_sched: skl(1, 1, 1.0, &[(SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // SSE4.2 — PCMPESTRI, PCMPISTRI, PCMPGTQ
        // ================================================================
        MCInstrProperties {
            mnemonic: "PCMPEstrIrr",
            opcode: 3450,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu3, 3)]),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![R_EFLAGS, R_ECX],
            implicit_uses: vec![R_EAX, R_EDX],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PCMPIstrIrr",
            opcode: 3451,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu3, 3)]),
            flags: flag_writes_arith(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![R_EFLAGS, R_ECX],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "PCMPGTQrr",
            opcode: 3452,
            skl_sched: skl_simd_int_add(),
            zn4_sched: zn4_simd_int_add(),
            flags: flag_none(),
            side_effects: MCSideEffects::new().compare(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // AVX2 — VPBROADCAST, VPERM*, VPGATHER*, VPMASKMOV
        // ================================================================
        MCInstrProperties {
            mnemonic: "VPBROADCASTDrr",
            opcode: 3500,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu2, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPBROADCASTDYrr",
            opcode: 3501,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu2, 1), (SchedPort::ZenFpu3, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPERMILPSrr",
            opcode: 3502,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                1,
                1,
                0.5,
                &[(SchedPort::ZenFpu1, 1), (SchedPort::ZenFpu2, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPERM2I128rr",
            opcode: 3503,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port5, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_YMM, OP_YMM, OP_YMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPGATHERDDrm",
            opcode: 3510,
            skl_sched: skl(
                20,
                5,
                4.0,
                &[
                    (SchedPort::Port2, 4),
                    (SchedPort::Port3, 4),
                    (SchedPort::Port4, 1),
                ],
            ),
            zn4_sched: zn4(
                20,
                5,
                4.0,
                &[(SchedPort::ZenAgu0, 4), (SchedPort::ZenAgu1, 4)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_XMM, OP_M32, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(5, 10),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPMASKMOVDrr",
            opcode: 3511,
            skl_sched: skl(2, 2, 1.0, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                2,
                2,
                1.0,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load().store(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_M128],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_vex_rr(5, 10),
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // Additional AVX-512 — VPERM*Z, VCOMPRESS*, VEXPAND*, VSCATTER*
        // ================================================================
        MCInstrProperties {
            mnemonic: "VPERMDZrr",
            opcode: 3600,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port5, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu1, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::None,
            ],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VCOMPRESSPSZmr",
            opcode: 3601,
            skl_sched: skl(3, 2, 1.0, &[(SchedPort::Port4, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(
                3,
                2,
                1.0,
                &[(SchedPort::ZenAgu2, 1), (SchedPort::ZenFpu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_M512, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VEXPANDPSZrm",
            opcode: 3602,
            skl_sched: skl(5, 1, 0.5, &[(SchedPort::Port2, 1), (SchedPort::Port3, 1)]),
            zn4_sched: zn4(
                4,
                1,
                0.5,
                &[(SchedPort::ZenAgu0, 1), (SchedPort::ZenAgu1, 1)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load(),
            explicit_operands: vec![OP_ZMM, OP_M512],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VSCATTERDPSZmr",
            opcode: 3603,
            skl_sched: skl(
                25,
                5,
                5.0,
                &[
                    (SchedPort::Port2, 4),
                    (SchedPort::Port3, 4),
                    (SchedPort::Port4, 4),
                ],
            ),
            zn4_sched: zn4(
                25,
                5,
                5.0,
                &[(SchedPort::ZenAgu0, 4), (SchedPort::ZenAgu2, 4)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store(),
            explicit_operands: vec![OP_M512, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPCONFLICTDrr",
            opcode: 3610,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port5, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenFpu0, 1)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "VPLZCNTDrr",
            opcode: 3611,
            skl_sched: skl(3, 1, 1.0, &[(SchedPort::Port0, 3)]),
            zn4_sched: zn4(3, 1, 1.0, &[(SchedPort::ZenFpu0, 3)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_ZMM, OP_ZMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_evex_rr(6, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // SHA / AES — SHA1RNDS4, SHA256RNDS2, AESENC, AESDEC, AESKEYGENASSIST
        // ================================================================
        MCInstrProperties {
            mnemonic: "SHA1RNDS4rri",
            opcode: 3700,
            skl_sched: skl(5, 1, 2.0, &[(SchedPort::Port0, 5)]),
            zn4_sched: zn4(5, 1, 2.0, &[(SchedPort::ZenFpu0, 5)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::TiedToDef(0),
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 3),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "SHA256RNDS2rr",
            opcode: 3701,
            skl_sched: skl(8, 2, 4.0, &[(SchedPort::Port0, 4), (SchedPort::Port5, 4)]),
            zn4_sched: zn4(
                8,
                2,
                4.0,
                &[(SchedPort::ZenFpu0, 4), (SchedPort::ZenFpu3, 4)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![XMM0],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "AESENCrr",
            opcode: 3702,
            skl_sched: skl(4, 1, 1.0, &[(SchedPort::Port0, 4)]),
            zn4_sched: zn4(4, 1, 1.0, &[(SchedPort::ZenFpu0, 4)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "AESDECrr",
            opcode: 3703,
            skl_sched: skl(4, 1, 1.0, &[(SchedPort::Port0, 4)]),
            zn4_sched: zn4(4, 1, 1.0, &[(SchedPort::ZenFpu0, 4)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::TiedToDef(0), OperandConstraint::None],
            encoding: enc_vex_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        MCInstrProperties {
            mnemonic: "AESKEYGENASSISTrr",
            opcode: 3704,
            skl_sched: skl(10, 1, 2.0, &[(SchedPort::Port0, 10)]),
            zn4_sched: zn4(10, 1, 2.0, &[(SchedPort::ZenFpu0, 10)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_XMM, OP_XMM, OP_I8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![
                OperandConstraint::None,
                OperandConstraint::None,
                OperandConstraint::ImmRange(0, 255),
            ],
            encoding: enc_vex_rr(5, 6),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "simd",
        },
        // ================================================================
        // ADX — ADCX, ADOX (arbitrary-precision arithmetic)
        // ================================================================
        MCInstrProperties {
            mnemonic: "ADCX32rr",
            opcode: 3800,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new().write(Flag::CF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        MCInstrProperties {
            mnemonic: "ADOX32rr",
            opcode: 3801,
            skl_sched: skl(1, 1, 0.5, &[(SchedPort::Port0, 1), (SchedPort::Port6, 1)]),
            zn4_sched: zn4(1, 1, 0.5, &[(SchedPort::ZenAlu0, 1)]),
            flags: MCInstrFlags::new().write(Flag::OF),
            side_effects: MCSideEffects::new(),
            explicit_operands: vec![OP_R32, OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![R_EFLAGS],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: true,
            is_conversion: false,
            is_conditional_move: false,
            category: "arithmetic",
        },
        // ================================================================
        // MOVDIRI / MOVDIR64B — direct store instructions
        // ================================================================
        MCInstrProperties {
            mnemonic: "MOVDIRI32mr",
            opcode: 3900,
            skl_sched: skl(10, 1, 5.0, &[(SchedPort::Port4, 10)]),
            zn4_sched: zn4(10, 1, 5.0, &[(SchedPort::ZenAgu2, 10)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store().side_effects(),
            explicit_operands: vec![OP_M32, OP_R32],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(5, 10),
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "MOVDIR64Bmr",
            opcode: 3901,
            skl_sched: skl(
                30,
                3,
                10.0,
                &[
                    (SchedPort::Port2, 3),
                    (SchedPort::Port3, 3),
                    (SchedPort::Port4, 3),
                ],
            ),
            zn4_sched: zn4(
                30,
                3,
                10.0,
                &[(SchedPort::ZenAgu0, 3), (SchedPort::ZenAgu2, 3)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store().side_effects(),
            explicit_operands: vec![OP_M256, OP_R64],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None, OperandConstraint::None],
            encoding: enc_rm(5, 10),
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        // ================================================================
        // CLFLUSH / CLFLUSHOPT / CLWB — cache line management
        // ================================================================
        MCInstrProperties {
            mnemonic: "CLFLUSH",
            opcode: 4000,
            skl_sched: skl(10, 1, 5.0, &[(SchedPort::Port2, 10)]),
            zn4_sched: zn4(10, 1, 5.0, &[(SchedPort::ZenAgu0, 10)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load().side_effects(),
            explicit_operands: vec![OP_M8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 8,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "CLFLUSHOPT",
            opcode: 4001,
            skl_sched: skl(8, 1, 4.0, &[(SchedPort::Port2, 8)]),
            zn4_sched: zn4(8, 1, 4.0, &[(SchedPort::ZenAgu0, 8)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().side_effects(),
            explicit_operands: vec![OP_M8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 4,
                max_bytes: 9,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "CLWB",
            opcode: 4002,
            skl_sched: skl(8, 1, 4.0, &[(SchedPort::Port2, 8)]),
            zn4_sched: zn4(8, 1, 4.0, &[(SchedPort::ZenAgu0, 8)]),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load().side_effects(),
            explicit_operands: vec![OP_M8],
            implicit_defs: vec![],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 4,
                max_bytes: 9,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![
                AddrMode::BaseOnly,
                AddrMode::BaseDisp,
                AddrMode::BaseIndex,
                AddrMode::BaseIndexDisp,
            ],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        // ================================================================
        // XSAVE / XRSTOR / XSAVEOPT — extended state management
        // ================================================================
        MCInstrProperties {
            mnemonic: "XSAVE",
            opcode: 4100,
            skl_sched: skl(
                60,
                5,
                20.0,
                &[
                    (SchedPort::Port2, 5),
                    (SchedPort::Port3, 5),
                    (SchedPort::Port4, 5),
                ],
            ),
            zn4_sched: zn4(
                60,
                5,
                20.0,
                &[(SchedPort::ZenAgu0, 5), (SchedPort::ZenAgu2, 5)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().store().side_effects(),
            explicit_operands: vec![OP_M512],
            implicit_defs: vec![],
            implicit_uses: vec![R_EAX, R_EDX],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 8,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: false,
            can_fold_store: true,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "XRSTOR",
            opcode: 4101,
            skl_sched: skl(60, 5, 20.0, &[(SchedPort::Port2, 5), (SchedPort::Port3, 5)]),
            zn4_sched: zn4(
                60,
                5,
                20.0,
                &[(SchedPort::ZenAgu0, 5), (SchedPort::ZenAgu1, 5)],
            ),
            flags: flag_none(),
            side_effects: MCSideEffects::new().load().side_effects(),
            explicit_operands: vec![OP_M512],
            implicit_defs: vec![],
            implicit_uses: vec![R_EAX, R_EDX],
            operand_constraints: vec![OperandConstraint::None],
            encoding: EncodingInfo {
                min_bytes: 3,
                max_bytes: 8,
                has_modrm: true,
                may_use_sib: true,
                ..Default::default()
            },
            addr_modes: vec![AddrMode::BaseOnly, AddrMode::BaseDisp],
            can_fold_load: true,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        // ================================================================
        // RDRAND / RDSEED — hardware random number generators
        // ================================================================
        MCInstrProperties {
            mnemonic: "RDRAND32r",
            opcode: 4200,
            skl_sched: skl(100, 10, 100.0, &[(SchedPort::Port0, 100)]),
            zn4_sched: zn4(100, 10, 100.0, &[(SchedPort::ZenAlu0, 100)]),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new().side_effects(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
        MCInstrProperties {
            mnemonic: "RDSEED32r",
            opcode: 4201,
            skl_sched: skl(100, 10, 100.0, &[(SchedPort::Port0, 100)]),
            zn4_sched: zn4(100, 10, 100.0, &[(SchedPort::ZenAlu0, 100)]),
            flags: flag_writes_logic(),
            side_effects: MCSideEffects::new().side_effects(),
            explicit_operands: vec![OP_R32],
            implicit_defs: vec![R_EFLAGS],
            implicit_uses: vec![],
            operand_constraints: vec![OperandConstraint::RegClass("GR32")],
            encoding: enc_rr(4, 5),
            addr_modes: vec![AddrMode::None],
            can_fold_load: false,
            can_fold_store: false,
            is_commutative: false,
            is_conversion: false,
            is_conditional_move: false,
            category: "system",
        },
    ]
}

// ============================================================================
// X86MCInstrAnalysis — instruction analysis utilities
// ============================================================================

/// X86 MC instruction analysis — evaluate branches, classify instructions,
/// compute latencies, determine fold compatibility, commute operands.
pub struct X86MCInstrAnalysis {
    /// The instruction property database.
    pub info: X86MCInstrInfoFull,
}

impl X86MCInstrAnalysis {
    /// Create a new analysis instance backed by the instruction database.
    pub fn new() -> Self {
        X86MCInstrAnalysis {
            info: X86MCInstrInfoFull::new(),
        }
    }

    // ========================================================================
    // Branch evaluation
    // ========================================================================

    /// Evaluate a direct branch target.
    ///
    /// Given the current instruction address (`current_pc`), the branch opcode,
    /// and the branch's operands (relative offset), compute the target address.
    /// Returns `None` if the branch is not a direct PC-relative branch.
    pub fn evaluate_branch(
        &self,
        current_pc: u64,
        mnemonic: &str,
        operands: &[i64],
    ) -> Option<u64> {
        let props = self.info.lookup(mnemonic)?;

        if !props.side_effects.is_branch {
            return None;
        }

        if operands.is_empty() {
            return None;
        }

        let offset = operands[0];

        // For relative branches, add the instruction length plus the offset
        // Simple model: assume the branch instruction itself is the size of the
        // short encoding (2 bytes) for 8-bit offsets, or the near encoding
        // (5-6 bytes) for 32-bit offsets.
        let instr_size: i64 = if offset >= -128 && offset <= 127 {
            props.encoding.min_bytes as i64
        } else {
            props.encoding.max_bytes as i64
        };

        let target = (current_pc as i64)
            .wrapping_add(instr_size)
            .wrapping_add(offset);

        Some(target as u64)
    }

    /// Evaluate a conditional branch target. Returns the fallthrough and taken
    /// addresses.
    pub fn evaluate_conditional_branch(
        &self,
        current_pc: u64,
        mnemonic: &str,
        operands: &[i64],
        fallthrough_instr_size: u64,
    ) -> Option<(u64, u64)> {
        let taken = self.evaluate_branch(current_pc, mnemonic, operands)?;
        let fallthrough = current_pc + fallthrough_instr_size;
        Some((fallthrough, taken))
    }

    // ========================================================================
    // Instruction classification
    // ========================================================================

    /// Returns true if the instruction is a function call.
    pub fn is_call(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_call)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a return from function.
    pub fn is_return(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_return)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is any kind of branch.
    pub fn is_branch(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_branch)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is an unconditional branch (JMP, RET, etc.).
    pub fn is_unconditional_branch(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| {
                p.side_effects.is_branch
                    && !p.flags.reads.is_empty() == false
                    && (p.mnemonic.starts_with("JMP")
                        || p.mnemonic.starts_with("RET")
                        || p.mnemonic.starts_with("IRET"))
            })
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a conditional branch.
    pub fn is_conditional_branch(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| {
                p.side_effects.is_branch && !p.flags.reads.is_empty() && !p.side_effects.is_return
            })
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a compare (sets flags for conditional branches).
    pub fn is_compare(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_compare)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a move-immediate.
    pub fn is_move_immediate(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_move_immediate)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a bitcast (reinterprets bits).
    pub fn is_bitcast(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_bitcast)
            .unwrap_or(false)
    }

    // ========================================================================
    // Arithmetic detection
    // ========================================================================

    /// Returns true if the instruction is an ADD.
    pub fn is_add(&self, mnemonic: &str) -> bool {
        mnemonic.starts_with("ADD") && !mnemonic.contains("SUB") && !mnemonic.contains("XADD")
    }

    /// Returns true if the instruction is a SUB.
    pub fn is_sub(&self, mnemonic: &str) -> bool {
        mnemonic.starts_with("SUB") && !mnemonic.contains("PSUB")
    }

    /// Returns true if the instruction is a MUL or IMUL.
    pub fn is_mul(&self, mnemonic: &str) -> bool {
        (mnemonic.starts_with("MUL") || mnemonic.starts_with("IMUL"))
            && !mnemonic.starts_with("MULX")
            && !mnemonic.starts_with("MULH")
    }

    // ========================================================================
    // Data movement detection
    // ========================================================================

    /// Returns true if the instruction is a register-register copy.
    pub fn is_copy(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.side_effects.is_copy)
            .unwrap_or(false)
    }

    /// Returns true if the instruction is a register move (MOV with no memory).
    pub fn is_move_reg(&self, mnemonic: &str) -> bool {
        mnemonic.starts_with("MOV") && mnemonic.ends_with("rr")
    }

    // ========================================================================
    // Scheduling queries
    // ========================================================================

    /// Get the Skylake latency for an instruction.
    pub fn get_latency_skl(&self, mnemonic: &str) -> Option<u32> {
        self.info
            .lookup(mnemonic)?
            .skl_sched
            .as_ref()
            .map(|s| s.latency)
    }

    /// Get the Zen 4 latency for an instruction.
    pub fn get_latency_zn4(&self, mnemonic: &str) -> Option<u32> {
        self.info
            .lookup(mnemonic)?
            .zn4_sched
            .as_ref()
            .map(|s| s.latency)
    }

    /// Get the latency for an instruction on the default uarch (Skylake).
    pub fn get_latency(&self, mnemonic: &str) -> Option<u32> {
        self.get_latency_skl(mnemonic)
    }

    /// Get the number of micro-ops for an instruction on Skylake.
    pub fn get_num_micro_ops_skl(&self, mnemonic: &str) -> Option<u32> {
        self.info
            .lookup(mnemonic)?
            .skl_sched
            .as_ref()
            .map(|s| s.uops)
    }

    /// Get the number of micro-ops for an instruction on Zen 4.
    pub fn get_num_micro_ops_zn4(&self, mnemonic: &str) -> Option<u32> {
        self.info
            .lookup(mnemonic)?
            .zn4_sched
            .as_ref()
            .map(|s| s.uops)
    }

    /// Get the number of micro-ops on the default uarch (Skylake).
    pub fn get_num_micro_ops(&self, mnemonic: &str) -> Option<u32> {
        self.get_num_micro_ops_skl(mnemonic)
    }

    /// Get the throughput (reciprocal) for an instruction.
    pub fn get_throughput_skl(&self, mnemonic: &str) -> Option<f64> {
        self.info
            .lookup(mnemonic)?
            .skl_sched
            .as_ref()
            .map(|s| s.throughput)
    }

    // ========================================================================
    // Memory fold compatibility
    // ========================================================================

    /// Returns true if this instruction can fold a memory load into one of its
    /// operands (i.e., the reg-reg form can be converted to reg-mem).
    pub fn can_fold_load(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.can_fold_load)
            .unwrap_or(false)
    }

    /// Returns true if this instruction can fold a memory store.
    pub fn can_fold_store(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.can_fold_store)
            .unwrap_or(false)
    }

    /// Returns true if this instruction can fold a memory operand
    /// (either load or store depending on the operand position).
    pub fn can_fold_memory(&self, mnemonic: &str) -> bool {
        self.can_fold_load(mnemonic) || self.can_fold_store(mnemonic)
    }

    // ========================================================================
    // Operand commutation
    // ========================================================================

    /// Check if the instruction is commutative (i.e., the source operands can
    /// be swapped without changing the result).
    pub fn is_commutative(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.is_commutative)
            .unwrap_or(false)
    }

    /// Commute the operands of a commutative instruction.
    ///
    /// Given a mnemonic and its operands, returns new operands with the two
    /// source operands swapped. Returns `None` if the instruction is not
    /// commutative or cannot be commuted.
    pub fn commute_instruction(&self, mnemonic: &str, operands: &[i64]) -> Option<Vec<i64>> {
        if !self.is_commutative(mnemonic) {
            return None;
        }

        let props = self.info.lookup(mnemonic)?;

        // Find which operands are the commutative pair.
        // For tied operands, we swap the non-tied source with the source.
        // Simple heuristic: look for constraints where first operand is tied to def,
        // and second is not — swap the last two source operands.
        if operands.len() < 2 {
            return None;
        }

        let has_tied = props
            .operand_constraints
            .iter()
            .any(|c| matches!(c, OperandConstraint::TiedToDef(0)));
        if has_tied && operands.len() >= 3 {
            // For 3-operand tied instructions like ADDSSrr (tied dest, src1, src2),
            // swap the two source operands (index 1 and 2)
            let mut new_ops = operands.to_vec();
            new_ops.swap(1, 2);
            Some(new_ops)
        } else {
            // For 2-operand instructions (dest/src, src), swap the two
            let mut new_ops = operands.to_vec();
            new_ops.swap(0, 1);
            Some(new_ops)
        }
    }

    // ========================================================================
    // Operand class queries
    // ========================================================================

    /// Get the register class name for a given operand position.
    ///
    /// Returns a string like "GR32", "GR64", "VR128", "VR256", "VR512", "FR32",
    /// "FR64", "VK1", "VK8", etc.
    pub fn get_reg_class(&self, mnemonic: &str, operand_index: usize) -> Option<&'static str> {
        let props = self.info.lookup(mnemonic)?;
        if operand_index >= props.explicit_operands.len() {
            return None;
        }

        let op_type = props.explicit_operands[operand_index];
        Some(match op_type {
            "r8" => "GR8",
            "r16" => "GR16",
            "r32" => "GR32",
            "r64" => "GR64",
            "xmm" => "VR128",
            "ymm" => "VR256",
            "zmm" => "VR512",
            "k" => "VK1",
            "mm" => "VR64",
            "m8" | "m16" | "m32" | "m64" | "m128" | "m256" | "m512" => "MEM",
            "i8" | "i16" | "i32" | "i64" => "IMM",
            "rel8" | "rel32" => "IMM",
            _ => "UNKNOWN",
        })
    }

    /// Returns true if the instruction is a floating-point operation.
    pub fn is_floating_point(&self, mnemonic: &str) -> bool {
        let upper = mnemonic.to_uppercase();
        // Check for FP-specific patterns in the mnemonic
        (upper.contains("SS")
            && !upper.contains("SSE")
            && !upper.contains("MSS")
            && (upper.contains("ADD")
                || upper.contains("SUB")
                || upper.contains("MUL")
                || upper.contains("DIV")
                || upper.contains("SQRT")
                || upper.contains("MAX")
                || upper.contains("MIN")
                || upper.contains("CMP")
                || upper.contains("CVT")))
            || (upper.contains("SD")
                && !upper.contains("PSD")
                && (upper.contains("ADD")
                    || upper.contains("SUB")
                    || upper.contains("MUL")
                    || upper.contains("DIV")
                    || upper.contains("SQRT")
                    || upper.contains("MAX")
                    || upper.contains("MIN")
                    || upper.contains("CMP")
                    || upper.contains("CVT")))
            || upper.contains("PS")
                && (upper.contains("ADD")
                    || upper.contains("SUB")
                    || upper.contains("MUL")
                    || upper.contains("DIV")
                    || upper.contains("SQRT")
                    || upper.contains("MAX")
                    || upper.contains("MIN"))
            || upper.contains("PD")
                && (upper.contains("ADD")
                    || upper.contains("SUB")
                    || upper.contains("MUL")
                    || upper.contains("DIV")
                    || upper.contains("SQRT")
                    || upper.contains("MAX")
                    || upper.contains("MIN"))
            || upper.contains("FMA")
            || upper.contains("FNMADD")
            || upper.contains("FNMSUB")
            || upper.contains("FMSUB")
            || upper.contains("FMADD")
    }

    /// Returns true if the instruction is a SIMD instruction.
    pub fn is_simd(&self, mnemonic: &str) -> bool {
        self.info
            .lookup(mnemonic)
            .map(|p| p.category == "simd")
            .unwrap_or(false)
    }

    /// Get the instruction category.
    pub fn get_category(&self, mnemonic: &str) -> Option<&'static str> {
        self.info.lookup(mnemonic).map(|p| p.category)
    }
}

impl Default for X86MCInstrAnalysis {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// X86MCInstrPrinter — instruction printing (AT&T and Intel syntax)
// ============================================================================

/// Assembly syntax style.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum AsmSyntaxStyle {
    /// AT&T syntax: `mnemonic src, dst` with `%` register prefix, `$` immediate prefix.
    ATTSyntax,
    /// Intel syntax: `mnemonic dst, src` without prefixes.
    IntelSyntax,
}

/// X86 MC instruction printer.
///
/// Formats instructions in either AT&T or Intel syntax, including:
/// - Register names
/// - Memory operands with all addressing modes (base, index, scale, displacement)
/// - Immediate values
/// - AVX-512 decorators (mask, zero-mask, rounding, SAE, broadcast)
pub struct X86MCInstrPrinter {
    /// The syntax style to use.
    pub syntax: AsmSyntaxStyle,
    /// Register name table (physical reg ID -> name string).
    pub reg_names: HashMap<u16, &'static str>,
}

impl X86MCInstrPrinter {
    /// Create a new printer with AT&T syntax (default).
    pub fn new() -> Self {
        let mut reg_names = HashMap::new();
        // Build register name table
        reg_names.insert(RAX, "rax");
        reg_names.insert(RBX, "rbx");
        reg_names.insert(RCX, "rcx");
        reg_names.insert(RDX, "rdx");
        reg_names.insert(RSI, "rsi");
        reg_names.insert(RDI, "rdi");
        reg_names.insert(RBP, "rbp");
        reg_names.insert(RSP, "rsp");
        reg_names.insert(R8, "r8");
        reg_names.insert(R9, "r9");
        reg_names.insert(R10, "r10");
        reg_names.insert(R11, "r11");
        reg_names.insert(R12, "r12");
        reg_names.insert(R13, "r13");
        reg_names.insert(R14, "r14");
        reg_names.insert(R15, "r15");

        reg_names.insert(EAX, "eax");
        reg_names.insert(EBX, "ebx");
        reg_names.insert(ECX, "ecx");
        reg_names.insert(EDX, "edx");
        reg_names.insert(ESI, "esi");
        reg_names.insert(EDI, "edi");
        reg_names.insert(EBP, "ebp");
        reg_names.insert(ESP, "esp");

        reg_names.insert(R8D, "r8d");
        reg_names.insert(R9D, "r9d");
        reg_names.insert(R10D, "r10d");
        reg_names.insert(R11D, "r11d");
        reg_names.insert(R12D, "r12d");
        reg_names.insert(R13D, "r13d");
        reg_names.insert(R14D, "r14d");
        reg_names.insert(R15D, "r15d");

        reg_names.insert(R8W, "r8w");
        reg_names.insert(R9W, "r9w");
        reg_names.insert(R10W, "r10w");
        reg_names.insert(R11W, "r11w");
        reg_names.insert(R12W, "r12w");
        reg_names.insert(R13W, "r13w");
        reg_names.insert(R14W, "r14w");
        reg_names.insert(R15W, "r15w");

        reg_names.insert(R8B, "r8b");
        reg_names.insert(R9B, "r9b");
        reg_names.insert(R10B, "r10b");
        reg_names.insert(R11B, "r11b");
        reg_names.insert(R12B, "r12b");
        reg_names.insert(R13B, "r13b");
        reg_names.insert(R14B, "r14b");
        reg_names.insert(R15B, "r15b");

        reg_names.insert(AL, "al");
        reg_names.insert(BL, "bl");
        reg_names.insert(CL, "cl");
        reg_names.insert(DL, "dl");
        reg_names.insert(SIL, "sil");
        reg_names.insert(DIL, "dil");
        reg_names.insert(BPL, "bpl");
        reg_names.insert(SPL, "spl");
        reg_names.insert(AH, "ah");
        reg_names.insert(BH, "bh");
        reg_names.insert(CH, "ch");
        reg_names.insert(DH, "dh");

        reg_names.insert(AX, "ax");
        reg_names.insert(BX, "bx");
        reg_names.insert(CX, "cx");
        reg_names.insert(DX, "dx");
        reg_names.insert(SI, "si");
        reg_names.insert(DI, "di");
        reg_names.insert(BP, "bp");
        reg_names.insert(SP, "sp");

        reg_names.insert(XMM0, "xmm0");
        reg_names.insert(XMM1, "xmm1");
        reg_names.insert(XMM2, "xmm2");
        reg_names.insert(XMM3, "xmm3");
        reg_names.insert(XMM4, "xmm4");
        reg_names.insert(XMM5, "xmm5");
        reg_names.insert(XMM6, "xmm6");
        reg_names.insert(XMM7, "xmm7");
        reg_names.insert(XMM8, "xmm8");
        reg_names.insert(XMM9, "xmm9");
        reg_names.insert(XMM10, "xmm10");
        reg_names.insert(XMM11, "xmm11");
        reg_names.insert(XMM12, "xmm12");
        reg_names.insert(XMM13, "xmm13");
        reg_names.insert(XMM14, "xmm14");
        reg_names.insert(XMM15, "xmm15");

        reg_names.insert(YMM0, "ymm0");
        reg_names.insert(YMM1, "ymm1");
        reg_names.insert(YMM2, "ymm2");
        reg_names.insert(YMM3, "ymm3");
        reg_names.insert(YMM4, "ymm4");
        reg_names.insert(YMM5, "ymm5");
        reg_names.insert(YMM6, "ymm6");
        reg_names.insert(YMM7, "ymm7");
        reg_names.insert(YMM8, "ymm8");
        reg_names.insert(YMM9, "ymm9");
        reg_names.insert(YMM10, "ymm10");
        reg_names.insert(YMM11, "ymm11");
        reg_names.insert(YMM12, "ymm12");
        reg_names.insert(YMM13, "ymm13");
        reg_names.insert(YMM14, "ymm14");
        reg_names.insert(YMM15, "ymm15");

        reg_names.insert(ZMM0, "zmm0");
        reg_names.insert(ZMM1, "zmm1");
        reg_names.insert(ZMM2, "zmm2");
        reg_names.insert(ZMM3, "zmm3");
        reg_names.insert(ZMM4, "zmm4");
        reg_names.insert(ZMM5, "zmm5");
        reg_names.insert(ZMM6, "zmm6");
        reg_names.insert(ZMM7, "zmm7");

        reg_names.insert(K0, "k0");
        reg_names.insert(K1, "k1");
        reg_names.insert(K2, "k2");
        reg_names.insert(K3, "k3");
        reg_names.insert(K4, "k4");
        reg_names.insert(K5, "k5");
        reg_names.insert(K6, "k6");
        reg_names.insert(K7, "k7");

        reg_names.insert(RFLAGS, "eflags");
        reg_names.insert(RIP, "rip");
        reg_names.insert(CS, "cs");
        reg_names.insert(DS, "ds");
        reg_names.insert(ES, "es");
        reg_names.insert(SS, "ss");
        reg_names.insert(FS, "fs");
        reg_names.insert(GS, "gs");

        X86MCInstrPrinter {
            syntax: AsmSyntaxStyle::ATTSyntax,
            reg_names,
        }
    }

    /// Create a printer with Intel syntax.
    pub fn new_intel() -> Self {
        let mut printer = Self::new();
        printer.syntax = AsmSyntaxStyle::IntelSyntax;
        printer
    }

    /// Create a printer with AT&T syntax.
    pub fn new_att() -> Self {
        Self::new()
    }

    /// Get the register name for a physical register ID.
    pub fn reg_name(&self, reg: u16) -> &str {
        self.reg_names.get(&reg).copied().unwrap_or("<?>")
    }

    // ====================================================================
    // Operand formatting
    // ====================================================================

    /// Format a register operand.
    pub fn format_register(&self, reg: u16) -> String {
        let name = self.reg_name(reg);
        match self.syntax {
            AsmSyntaxStyle::ATTSyntax => format!("%{}", name),
            AsmSyntaxStyle::IntelSyntax => name.to_string(),
        }
    }

    /// Format an immediate operand.
    pub fn format_immediate(&self, value: i64, _size: u8) -> String {
        match self.syntax {
            AsmSyntaxStyle::ATTSyntax => {
                if value < 0 {
                    format!("$-{}", -value)
                } else {
                    format!("${}", value)
                }
            }
            AsmSyntaxStyle::IntelSyntax => {
                if value < 0 {
                    format!("-{}", -value)
                } else {
                    format!("{}", value)
                }
            }
        }
    }

    /// Format a memory operand.
    ///
    /// Parameters:
    /// - `seg`: segment register override (0 = none)
    /// - `base`: base register (0 = none)
    /// - `index`: index register (0 = none)
    /// - `scale`: scale factor (1, 2, 4, 8; 0 = no index)
    /// - `disp`: displacement value
    /// - `disp_size`: displacement size in bytes (1, 2, 4)
    pub fn format_memory(
        &self,
        seg: u16,
        base: u16,
        index: u16,
        scale: u8,
        disp: i64,
        _disp_size: u8,
    ) -> String {
        let mut parts = Vec::new();

        // Displacement
        if disp != 0 || (base == 0 && index == 0) {
            if disp < 0 {
                parts.push(format!("-{}", -disp));
            } else if disp > 0 {
                parts.push(format!("{}", disp));
            }
        }

        // Build effective address expression
        let mut addr_parts = Vec::new();
        if base != 0 {
            addr_parts.push(self.reg_name(base).to_string());
        }
        if index != 0 {
            let scale_str = match scale {
                0 | 1 => String::new(),
                2 => ",2".to_string(),
                4 => ",4".to_string(),
                8 => ",8".to_string(),
                _ => format!(",{}", scale),
            };
            addr_parts.push(format!("{}{}", self.reg_name(index), scale_str));
        }

        let addr_str = addr_parts.join("+");

        match self.syntax {
            AsmSyntaxStyle::ATTSyntax => {
                let mut mem = String::new();
                if seg != 0 {
                    mem.push_str(&format!("%{}:", self.reg_name(seg)));
                }
                if disp != 0 || (base == 0 && index == 0) {
                    if disp < 0 {
                        mem.push_str(&format!("-{}", -disp));
                    } else {
                        mem.push_str(&disp.to_string());
                    }
                }
                if !addr_str.is_empty() {
                    mem.push('(');
                    mem.push_str(&addr_str);
                    mem.push(')');
                }
                mem
            }
            AsmSyntaxStyle::IntelSyntax => {
                let mut mem = String::new();
                if seg != 0 {
                    mem.push_str(&format!("{}:", self.reg_name(seg)));
                }
                mem.push('[');
                if !addr_str.is_empty() {
                    mem.push_str(&addr_str);
                    if disp > 0 {
                        mem.push_str(&format!(" + {}", disp));
                    } else if disp < 0 {
                        mem.push_str(&format!(" - {}", -disp));
                    }
                } else if disp != 0 || base == 0 && index == 0 {
                    mem.push_str(&disp.to_string());
                }
                mem.push(']');
                mem
            }
        }
    }

    /// Format RIP-relative memory operand.
    pub fn format_rip_relative(&self, disp: i64) -> String {
        match self.syntax {
            AsmSyntaxStyle::ATTSyntax => {
                format!("{}(%rip)", disp)
            }
            AsmSyntaxStyle::IntelSyntax => {
                if disp >= 0 {
                    format!("[rip + {}]", disp)
                } else {
                    format!("[rip - {}]", -disp)
                }
            }
        }
    }

    // ====================================================================
    // AVX-512 decorators
    // ====================================================================

    /// Format AVX-512 decorators.
    ///
    /// These are the annotations that appear in curly braces after the
    /// instruction, e.g., `{k1}`, `{z}`, `{rn-sae}`, `{1to16}`.
    pub fn format_evex_decorators(
        &self,
        mask_reg: Option<u16>,
        zero_mask: bool,
        rounding: Option<&str>, // e.g., "rn-sae", "rd-sae", "ru-sae", "rz-sae"
        broadcast: Option<u8>,  // broadcast factor: 2, 4, 8, 16
    ) -> String {
        let mut decorators = Vec::new();

        if let Some(k) = mask_reg {
            decorators.push(format!("k{}", k));
        }

        if zero_mask {
            decorators.push("{z}".to_string());
        } else if mask_reg.is_some() {
            // mask without zero: just the mask name
        }

        if let Some(round) = rounding {
            decorators.push(round.to_string());
        } else if let Some(b) = broadcast {
            decorators.push(format!("1to{}", b));
        }

        if decorators.is_empty() {
            String::new()
        } else {
            format!("{{{}}}", decorators.join(", "))
        }
    }

    // ====================================================================
    // Full instruction printing
    // ====================================================================

    /// Print a complete instruction.
    ///
    /// Parameters:
    /// - `mnemonic`: instruction mnemonic
    /// - `operands`: list of operand strings (already formatted)
    /// - `decorators`: optional AVX-512 decorator string
    pub fn print_instruction(
        &self,
        mnemonic: &str,
        operands: &[String],
        decorators: Option<&str>,
    ) -> String {
        let mnem_lower = mnemonic.to_lowercase();
        let mnem = match self.syntax {
            AsmSyntaxStyle::ATTSyntax => {
                // Add AT&T size suffix when appropriate
                self.add_att_suffix(&mnem_lower)
            }
            AsmSyntaxStyle::IntelSyntax => mnem_lower,
        };

        if operands.is_empty() {
            if let Some(dec) = decorators {
                format!("{} {}", mnem, dec)
            } else {
                mnem
            }
        } else {
            let op_str = match self.syntax {
                AsmSyntaxStyle::ATTSyntax => {
                    // AT&T: src, dst (reversed from Intel order)
                    let mut rev = operands.to_vec();
                    if rev.len() >= 2 {
                        rev.reverse();
                    }
                    rev.join(", ")
                }
                AsmSyntaxStyle::IntelSyntax => operands.join(", "),
            };

            if let Some(dec) = decorators {
                format!("{} {} {}", mnem, op_str, dec)
            } else {
                format!("{} {}", mnem, op_str)
            }
        }
    }

    /// Add AT&T size suffix to the mnemonic.
    fn add_att_suffix(&self, mnemonic: &str) -> String {
        let mnem = mnemonic.to_uppercase();

        // Determine suffix from mnemonic pattern
        let suffix = if mnem.ends_with("SD") && !mnem.contains("PSD") {
            "sd"
        } else if mnem.ends_with("SS") && !mnem.contains("MSS") {
            "ss"
        } else if mnem.ends_with("PS") {
            "ps"
        } else if mnem.ends_with("PD") {
            "pd"
        } else if mnem.contains("32") || mnem.ends_with("L") {
            "l"
        } else if mnem.contains("64") || mnem.ends_with("Q") {
            "q"
        } else if mnem.contains("16") || mnem.ends_with("W") {
            "w"
        } else if mnem.contains("8") || mnem.ends_with("B") {
            "b"
        } else {
            // Default: no suffix for control flow, system, etc.
            ""
        };

        if suffix.is_empty() {
            mnemonic.to_lowercase()
        } else {
            format!("{}{}", mnemonic.to_lowercase(), suffix)
        }
    }

    /// Print a memory addressing mode description (for debugging).
    pub fn format_addressing_mode(&self, mode: AddrMode) -> &'static str {
        match mode {
            AddrMode::Absolute => "absolute",
            AddrMode::BaseOnly => "base",
            AddrMode::BaseDisp => "base+disp",
            AddrMode::BaseIndex => "base+index",
            AddrMode::BaseIndexDisp => "base+index+disp",
            AddrMode::RIPRelative => "rip-relative",
            AddrMode::IndexDisp => "index+disp",
            AddrMode::None => "none",
        }
    }
}

impl Default for X86MCInstrPrinter {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    // ========================================================================
    // Database tests
    // ========================================================================

    #[test]
    fn test_database_size() {
        let db = X86MCInstrInfoFull::new();
        assert!(
            db.len() >= 100,
            "Database should contain at least 100 instructions"
        );
    }

    #[test]
    fn test_lookup_by_mnemonic() {
        let db = X86MCInstrInfoFull::new();
        let add = db.lookup("ADD32rr").expect("ADD32rr should be in database");
        assert_eq!(add.mnemonic, "ADD32rr");
        assert_eq!(add.category, "arithmetic");
        assert!(add.is_commutative);
    }

    #[test]
    fn test_lookup_by_opcode() {
        let db = X86MCInstrInfoFull::new();
        let mov = db.lookup_opcode(1).expect("MOV32rr should have opcode 1");
        assert_eq!(mov.mnemonic, "MOV32rr");
    }

    #[test]
    fn test_category_filter() {
        let db = X86MCInstrInfoFull::new();
        let arith = db.arithmetic_instructions();
        assert!(!arith.is_empty());
        assert!(arith.iter().all(|p| p.category == "arithmetic"));

        let cf = db.control_flow_instructions();
        assert!(!cf.is_empty());
        assert!(cf.iter().all(|p| p.category == "control_flow"));
    }

    #[test]
    fn test_nop_properties() {
        let db = X86MCInstrInfoFull::new();
        let nop = db.lookup("NOP").expect("NOP should exist");
        assert_eq!(nop.flags.writes.len(), 0);
        assert_eq!(nop.flags.reads.len(), 0);
        assert!(!nop.side_effects.is_branch);
        assert!(!nop.side_effects.is_return);
    }

    #[test]
    fn test_flag_properties_add() {
        let db = X86MCInstrInfoFull::new();
        let add = db.lookup("ADD32rr").unwrap();
        // ADD should write all arithmetic flags
        assert!(add.flags.writes_flag(Flag::ZF));
        assert!(add.flags.writes_flag(Flag::SF));
        assert!(add.flags.writes_flag(Flag::OF));
        assert!(add.flags.writes_flag(Flag::CF));
    }

    #[test]
    fn test_flag_properties_cmp() {
        let db = X86MCInstrInfoFull::new();
        let cmp = db.lookup("CMP32rr").unwrap();
        assert!(cmp.side_effects.is_compare);
        assert!(cmp.flags.writes_flag(Flag::ZF));
        assert!(cmp.flags.writes_flag(Flag::CF));
    }

    #[test]
    fn test_branch_properties() {
        let db = X86MCInstrInfoFull::new();
        let je = db.lookup("JE_1").unwrap();
        assert!(je.side_effects.is_branch);
        assert!(je.side_effects.is_terminator);
        assert!(!je.side_effects.is_return);
        // JE reads ZF
        assert!(je.flags.reads_flag(Flag::ZF));
    }

    #[test]
    fn test_call_properties() {
        let db = X86MCInstrInfoFull::new();
        let call = db.lookup("CALLpcrel32").unwrap();
        assert!(call.side_effects.is_call);
        assert!(call.side_effects.may_store);
    }

    #[test]
    fn test_ret_properties() {
        let db = X86MCInstrInfoFull::new();
        let ret = db.lookup("RETQ").unwrap();
        assert!(ret.side_effects.is_return);
        assert!(ret.side_effects.is_terminator);
        assert!(ret.side_effects.is_barrier);
    }

    #[test]
    fn test_scheduling_info() {
        let db = X86MCInstrInfoFull::new();
        let add = db.lookup("ADD32rr").unwrap();
        assert!(add.skl_sched.is_some());
        assert!(add.zn4_sched.is_some());

        let skl = add.skl_sched.as_ref().unwrap();
        assert_eq!(skl.latency, 1);
        assert_eq!(skl.uops, 1);
        assert!(!skl.ports.is_empty());
    }

    #[test]
    fn test_encoding_info() {
        let db = X86MCInstrInfoFull::new();
        let add_rr = db.lookup("ADD32rr").unwrap();
        assert!(add_rr.encoding.has_modrm);
        assert!(add_rr.encoding.min_bytes >= 2);

        let nop = db.lookup("NOP").unwrap();
        assert!(nop.encoding.min_bytes >= 1);
    }

    #[test]
    fn test_memory_fold() {
        let db = X86MCInstrInfoFull::new();
        let add_rm = db.lookup("ADD32rm").unwrap();
        assert!(add_rm.can_fold_load);
        assert!(add_rm.side_effects.may_load);

        let mov_mr = db.lookup("MOV32mr").unwrap();
        assert!(mov_mr.can_fold_store);
        assert!(mov_mr.side_effects.may_store);
    }

    #[test]
    fn test_implicit_registers() {
        let db = X86MCInstrInfoFull::new();
        let div = db.lookup("DIV32r").unwrap();
        assert!(!div.implicit_defs.is_empty());
        assert!(!div.implicit_uses.is_empty());
    }

    // ========================================================================
    // Analysis tests
    // ========================================================================

    #[test]
    fn test_is_call() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_call("CALLpcrel32"));
        assert!(!analysis.is_call("ADD32rr"));
    }

    #[test]
    fn test_is_return() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_return("RETQ"));
        assert!(!analysis.is_return("JMP_1"));
    }

    #[test]
    fn test_is_branch() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_branch("JMP_1"));
        assert!(analysis.is_branch("JE_1"));
        assert!(!analysis.is_branch("ADD32rr"));
    }

    #[test]
    fn test_is_conditional_branch() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_conditional_branch("JE_1"));
        assert!(analysis.is_conditional_branch("JNE_1"));
        assert!(analysis.is_conditional_branch("JL_1"));
        assert!(!analysis.is_conditional_branch("JMP_1"));
        assert!(!analysis.is_conditional_branch("RETQ"));
    }

    #[test]
    fn test_is_unconditional_branch() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_unconditional_branch("JMP_1"));
        assert!(!analysis.is_unconditional_branch("JE_1"));
    }

    #[test]
    fn test_is_compare() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_compare("CMP32rr"));
        assert!(analysis.is_compare("TEST32rr"));
        assert!(!analysis.is_compare("ADD32rr"));
    }

    #[test]
    fn test_is_move_immediate() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_move_immediate("MOV32ri"));
        assert!(analysis.is_move_immediate("MOV32mi"));
        assert!(!analysis.is_move_immediate("MOV32rr"));
    }

    #[test]
    fn test_is_bitcast() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_bitcast("VMOVDrr"));
        assert!(analysis.is_bitcast("VMOVDrm"));
        assert!(!analysis.is_bitcast("ADD32rr"));
    }

    #[test]
    fn test_is_add_sub_mul() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_add("ADD32rr"));
        assert!(analysis.is_add("ADD64rr"));
        assert!(!analysis.is_add("SUB32rr"));
        assert!(!analysis.is_add("XADD32rr"));

        assert!(analysis.is_sub("SUB32rr"));
        assert!(!analysis.is_sub("PSUBDrr"));

        assert!(analysis.is_mul("IMUL32rr"));
        assert!(analysis.is_mul("MUL32r"));
        assert!(!analysis.is_mul("MULX32rr"));
    }

    #[test]
    fn test_is_copy() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_copy("MOV32rr"));
        assert!(analysis.is_copy("MOV64rr"));
        assert!(!analysis.is_copy("MOV32ri"));
    }

    #[test]
    fn test_is_move_reg() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_move_reg("MOV32rr"));
        assert!(analysis.is_move_reg("MOV64rr"));
        assert!(!analysis.is_move_reg("MOV32ri"));
        assert!(!analysis.is_move_reg("MOV32rm"));
        assert!(!analysis.is_move_reg("MOV32mr"));
    }

    #[test]
    fn test_get_latency() {
        let analysis = X86MCInstrAnalysis::new();
        let lat = analysis.get_latency("ADD32rr");
        assert!(lat.is_some());
        assert_eq!(lat.unwrap(), 1);

        let lat_mul = analysis.get_latency("MULSSrr");
        assert!(lat_mul.is_some());
        assert!(lat_mul.unwrap() >= 3);

        let lat_div = analysis.get_latency("DIV32r");
        assert!(lat_div.is_some());
        assert!(lat_div.unwrap() >= 20);
    }

    #[test]
    fn test_get_num_micro_ops() {
        let analysis = X86MCInstrAnalysis::new();
        let uops = analysis.get_num_micro_ops("ADD32rr");
        assert_eq!(uops, Some(1));

        let uops_xchg = analysis.get_num_micro_ops("XCHG32rr");
        assert!(uops_xchg.unwrap() >= 2);
    }

    #[test]
    fn test_can_fold_load() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.can_fold_load("ADD32rm"));
        assert!(analysis.can_fold_load("MOV32rm"));
        assert!(!analysis.can_fold_load("ADD32rr"));
    }

    #[test]
    fn test_can_fold_store() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.can_fold_store("MOV32mr"));
        assert!(!analysis.can_fold_store("MOV32rm"));
    }

    #[test]
    fn test_commute_add() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_commutative("ADD32rr"));
        let result = analysis.commute_instruction("ADD32rr", &[1, 2]);
        assert!(result.is_some());
        assert_eq!(result.unwrap(), vec![2, 1]);
    }

    #[test]
    fn test_commute_non_commutative() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(!analysis.is_commutative("SUB32rr"));
        let result = analysis.commute_instruction("SUB32rr", &[1, 2]);
        assert!(result.is_none());
    }

    #[test]
    fn test_commute_addss() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_commutative("ADDSSrr"));
        let result = analysis.commute_instruction("ADDSSrr", &[10, 20, 30]);
        assert!(result.is_some());
        assert_eq!(result.unwrap(), vec![10, 30, 20]);
    }

    #[test]
    fn test_get_reg_class() {
        let analysis = X86MCInstrAnalysis::new();
        assert_eq!(analysis.get_reg_class("ADD32rr", 0), Some("GR32"));
        assert_eq!(analysis.get_reg_class("ADD64rr", 0), Some("GR64"));
        assert_eq!(analysis.get_reg_class("ADD32ri", 1), Some("IMM"));
        assert_eq!(analysis.get_reg_class("MOVSSrr", 0), Some("VR128"));
        assert_eq!(analysis.get_reg_class("ADD32rm", 1), Some("MEM"));
    }

    #[test]
    fn test_evaluate_branch() {
        let analysis = X86MCInstrAnalysis::new();
        // JMP_1 with offset 10 from PC=0x1000, instruc size=2
        let target = analysis.evaluate_branch(0x1000, "JMP_1", &[10]);
        assert_eq!(target, Some(0x1000 + 2 + 10));

        // Backward branch
        let target2 = analysis.evaluate_branch(0x2000, "JE_1", &[-5]);
        assert_eq!(target2, Some(0x2000 + 2 - 5));

        // Non-branch should return None
        let target3 = analysis.evaluate_branch(0x1000, "ADD32rr", &[1, 2]);
        assert_eq!(target3, None);
    }

    #[test]
    fn test_is_floating_point() {
        let analysis = X86MCInstrAnalysis::new();
        assert!(analysis.is_floating_point("ADDSSrr"));
        assert!(analysis.is_floating_point("MULSDrr"));
        assert!(analysis.is_floating_point("ADDPSrr"));
        assert!(analysis.is_floating_point("VFMADD132PSr"));
        assert!(!analysis.is_floating_point("ADD32rr"));
    }

    // ========================================================================
    // Printer tests
    // ========================================================================

    #[test]
    fn test_printer_att_register() {
        let printer = X86MCInstrPrinter::new_att();
        assert_eq!(printer.format_register(RAX), "%rax");
        assert_eq!(printer.format_register(R12), "%r12");
    }

    #[test]
    fn test_printer_intel_register() {
        let printer = X86MCInstrPrinter::new_intel();
        assert_eq!(printer.format_register(RAX), "rax");
        assert_eq!(printer.format_register(XMM0), "xmm0");
    }

    #[test]
    fn test_printer_att_immediate() {
        let printer = X86MCInstrPrinter::new_att();
        assert_eq!(printer.format_immediate(42, 4), "$42");
        assert_eq!(printer.format_immediate(-10, 4), "$-10");
    }

    #[test]
    fn test_printer_intel_immediate() {
        let printer = X86MCInstrPrinter::new_intel();
        assert_eq!(printer.format_immediate(42, 4), "42");
        assert_eq!(printer.format_immediate(-10, 4), "-10");
    }

    #[test]
    fn test_printer_att_memory_base_disp() {
        let printer = X86MCInstrPrinter::new_att();
        let result = printer.format_memory(0, RAX, 0, 0, 8, 4);
        assert_eq!(result, "8(%rax)");
    }

    #[test]
    fn test_printer_att_memory_base_index_scale() {
        let printer = X86MCInstrPrinter::new_att();
        let result = printer.format_memory(0, RAX, RCX, 4, 0, 4);
        assert_eq!(result, "(%rax,%rcx,4)");
    }

    #[test]
    fn test_printer_intel_memory_base_disp() {
        let printer = X86MCInstrPrinter::new_intel();
        let result = printer.format_memory(0, RAX, 0, 0, 8, 4);
        assert_eq!(result, "[rax + 8]");
    }

    #[test]
    fn test_printer_intel_memory_base_index_scale() {
        let printer = X86MCInstrPrinter::new_intel();
        let result = printer.format_memory(0, RAX, RCX, 4, 0, 4);
        assert_eq!(result, "[rax + rcx*4]");
    }

    #[test]
    fn test_printer_intel_negative_disp() {
        let printer = X86MCInstrPrinter::new_intel();
        let result = printer.format_memory(0, RAX, 0, 0, -4, 4);
        assert_eq!(result, "[rax - 4]");
    }

    #[test]
    fn test_printer_rip_relative() {
        let att = X86MCInstrPrinter::new_att();
        assert_eq!(att.format_rip_relative(42), "42(%rip)");

        let intel = X86MCInstrPrinter::new_intel();
        assert_eq!(intel.format_rip_relative(42), "[rip + 42]");
        assert_eq!(intel.format_rip_relative(-10), "[rip - 10]");
    }

    #[test]
    fn test_evex_decorators_mask_only() {
        let printer = X86MCInstrPrinter::new();
        let dec = printer.format_evex_decorators(Some(3), false, None, None);
        assert_eq!(dec, "{k3}");
    }

    #[test]
    fn test_evex_decorators_mask_zero() {
        let printer = X86MCInstrPrinter::new();
        let dec = printer.format_evex_decorators(Some(5), true, None, None);
        assert_eq!(dec, "{k5, {z}}");
    }

    #[test]
    fn test_evex_decorators_rounding() {
        let printer = X86MCInstrPrinter::new();
        let dec = printer.format_evex_decorators(None, false, Some("rn-sae"), None);
        assert_eq!(dec, "{rn-sae}");
    }

    #[test]
    fn test_evex_decorators_broadcast() {
        let printer = X86MCInstrPrinter::new();
        let dec = printer.format_evex_decorators(None, false, None, Some(16));
        assert_eq!(dec, "{1to16}");
    }

    #[test]
    fn test_print_instruction_att_two_operands() {
        let printer = X86MCInstrPrinter::new_att();
        let result =
            printer.print_instruction("ADD32rr", &["%eax".to_string(), "%ebx".to_string()], None);
        assert!(result.contains("addl"), "AT&T should use size suffix");
        assert!(result.contains("%ebx"), "AT&T has src first");
        assert!(result.contains("%eax"), "AT&T has dst second");
    }

    #[test]
    fn test_print_instruction_intel_two_operands() {
        let printer = X86MCInstrPrinter::new_intel();
        let result =
            printer.print_instruction("ADD32rr", &["%eax".to_string(), "%ebx".to_string()], None);
        assert!(result.contains("add"), "Intel has no size suffix");
        assert!(result.contains("%eax"), "Intel has dst first");
        assert!(result.contains("%ebx"), "Intel has src second");
    }

    #[test]
    fn test_print_instruction_no_operands() {
        let printer = X86MCInstrPrinter::new_att();
        let result = printer.print_instruction("RETQ", &[], None);
        assert_eq!(result, "retq");
    }

    #[test]
    fn test_print_with_decorators() {
        let printer = X86MCInstrPrinter::new_intel();
        let result = printer.print_instruction(
            "VADDPSZrr",
            &["zmm1".to_string(), "zmm2".to_string(), "zmm3".to_string()],
            Some("{k1}"),
        );
        assert!(result.contains("vaddps"));
        assert!(result.contains("{k1}"));
    }

    #[test]
    fn test_att_suffix() {
        let printer = X86MCInstrPrinter::new_att();

        // Test ADD32rr -> addl
        let result =
            printer.print_instruction("ADD32rr", &["%eax".to_string(), "%ebx".to_string()], None);
        assert!(result.contains("addl"));

        // Test ADD64rr -> addq
        let result =
            printer.print_instruction("ADD64rr", &["%rax".to_string(), "%rbx".to_string()], None);
        assert!(result.contains("addq"));

        // Test MOVSSrr -> movss
        let result =
            printer.print_instruction("MOVSSrr", &["%xmm0".to_string(), "%xmm1".to_string()], None);
        assert!(result.contains("movss"));

        // Test ADDSDrr -> addsd
        let result =
            printer.print_instruction("ADDSDrr", &["%xmm0".to_string(), "%xmm1".to_string()], None);
        assert!(result.contains("addsd"));
    }

    #[test]
    fn test_format_addressing_mode() {
        let printer = X86MCInstrPrinter::new();
        assert_eq!(
            printer.format_addressing_mode(AddrMode::BaseIndexDisp),
            "base+index+disp"
        );
        assert_eq!(
            printer.format_addressing_mode(AddrMode::RIPRelative),
            "rip-relative"
        );
        assert_eq!(printer.format_addressing_mode(AddrMode::None), "none");
    }

    // ========================================================================
    // Integration tests
    // ========================================================================

    #[test]
    fn test_simd_instruction_properties() {
        let db = X86MCInstrInfoFull::new();
        let addps = db.lookup("ADDPSrr").unwrap();
        assert_eq!(addps.category, "simd");
        assert!(addps.is_commutative);

        let paddd = db.lookup("PADDDrr").unwrap();
        assert_eq!(paddd.category, "simd");

        let vaddps = db.lookup("VADDPSYrr").unwrap();
        assert_eq!(vaddps.category, "simd");
    }

    #[test]
    fn test_fma_instruction_properties() {
        let db = X86MCInstrInfoFull::new();
        let fma = db.lookup("VFMADD132PSr").unwrap();
        assert_eq!(fma.category, "simd");
        assert!(!fma.is_commutative); // FMA is not fully commutative
    }

    #[test]
    fn test_bmi_instruction_properties() {
        let db = X86MCInstrInfoFull::new();
        let andn = db.lookup("ANDN32rr").unwrap();
        assert_eq!(andn.category, "bmi");
    }

    #[test]
    fn test_atomic_instruction_properties() {
        let db = X86MCInstrInfoFull::new();
        let cmpxchg = db.lookup("CMPXCHG32rr").unwrap();
        assert_eq!(cmpxchg.category, "atomic");
        assert!(cmpxchg.side_effects.may_load);
        assert!(cmpxchg.side_effects.may_store);
    }

    #[test]
    fn test_all_categories_present() {
        let db = X86MCInstrInfoFull::new();
        let categories: Vec<&str> = vec![
            "misc",
            "data_movement",
            "arithmetic",
            "logical",
            "shift_rotate",
            "control_flow",
            "simd",
            "bmi",
            "atomic",
            "bitmanip",
            "system",
        ];
        for cat in categories {
            let instrs = db.by_category(cat);
            assert!(
                !instrs.is_empty(),
                "Category '{}' should have instructions",
                cat
            );
        }
    }

    #[test]
    fn test_scheduling_data_consistency() {
        let db = X86MCInstrInfoFull::new();
        for prop in &db.all {
            if let Some(ref skl) = prop.skl_sched {
                assert!(
                    skl.latency > 0 || prop.mnemonic == "NOP",
                    "{}: Skylake latency should be > 0 (or NOP)",
                    prop.mnemonic
                );
            }
            if let Some(ref zn4) = prop.zn4_sched {
                assert!(
                    zn4.latency > 0 || prop.mnemonic == "NOP",
                    "{}: Zen4 latency should be > 0 (or NOP)",
                    prop.mnemonic
                );
            }
        }
    }

    #[test]
    fn test_encoding_data_consistency() {
        let db = X86MCInstrInfoFull::new();
        for prop in &db.all {
            assert!(
                prop.encoding.min_bytes >= 1,
                "{}: min_bytes must be >= 1",
                prop.mnemonic
            );
            assert!(
                prop.encoding.max_bytes >= prop.encoding.min_bytes,
                "{}: max_bytes must be >= min_bytes",
                prop.mnemonic
            );
            assert!(
                prop.encoding.max_bytes <= 15,
                "{}: max_bytes must be <= 15 (x86 limit)",
                prop.mnemonic
            );
        }
    }

    #[test]
    fn test_commutative_consistency() {
        let analysis = X86MCInstrAnalysis::new();
        // ADD, AND, OR, XOR, MUL are commutative
        assert!(analysis.is_commutative("ADD32rr"));
        assert!(analysis.is_commutative("AND32rr"));
        assert!(analysis.is_commutative("OR32rr"));
        assert!(analysis.is_commutative("XOR32rr"));
        assert!(analysis.is_commutative("IMUL32rr"));

        // SUB, SBB, DIV are not commutative
        assert!(!analysis.is_commutative("SUB32rr"));
        assert!(!analysis.is_commutative("SBB32rr"));

        // FP add/mul are commutative
        assert!(analysis.is_commutative("ADDSSrr"));
        assert!(analysis.is_commutative("MULSSrr"));
        assert!(analysis.is_commutative("ADDPSrr"));
        assert!(analysis.is_commutative("MULPSrr"));

        // FP sub/div are not commutative
        assert!(!analysis.is_commutative("SUBSSrr"));
        assert!(!analysis.is_commutative("DIVSSrr"));
    }

    #[test]
    fn test_operand_tied_constraints() {
        let db = X86MCInstrInfoFull::new();
        // ADDSSrr has tied first operand
        let addss = db.lookup("ADDSSrr").unwrap();
        let has_tied = addss
            .operand_constraints
            .iter()
            .any(|c| matches!(c, OperandConstraint::TiedToDef(0)));
        assert!(has_tied, "ADDSSrr should have tied operand constraint");
    }

    #[test]
    fn test_implicit_defs_uses() {
        let db = X86MCInstrInfoFull::new();
        // DIV uses EAX:EDX, defines EAX:EDX
        let div = db.lookup("DIV32r").unwrap();
        assert!(!div.implicit_defs.is_empty());
        assert!(!div.implicit_uses.is_empty());
    }

    #[test]
    fn test_printer_roundtrip_att() {
        let printer = X86MCInstrPrinter::new_att();
        let result = printer.print_instruction(
            "ADD32rr",
            &[printer.format_register(EAX), printer.format_register(EBX)],
            None,
        );
        assert!(result.contains("addl"));
        assert!(result.contains("%ebx"));
        assert!(result.contains("%eax"));
    }

    #[test]
    fn test_printer_roundtrip_intel() {
        let printer = X86MCInstrPrinter::new_intel();
        let result = printer.print_instruction(
            "ADD32rr",
            &[printer.format_register(EAX), printer.format_register(EBX)],
            None,
        );
        assert!(result.contains("add"));
        assert!(
            !result.contains("%"),
            "Intel syntax should not have % prefix in operand"
        );
        assert!(result.contains("eax"));
        assert!(result.contains("ebx"));
    }

    #[test]
    fn test_analysis_on_full_database() {
        let analysis = X86MCInstrAnalysis::new();
        let db = &analysis.info;

        for prop in &db.all {
            // Every instruction should return consistent results
            let lat = analysis.get_latency(prop.mnemonic);
            let uops = analysis.get_num_micro_ops(prop.mnemonic);

            if let Some(skl) = &prop.skl_sched {
                assert_eq!(
                    lat,
                    Some(skl.latency),
                    "get_latency mismatch for {}",
                    prop.mnemonic
                );
                assert_eq!(
                    uops,
                    Some(skl.uops),
                    "get_num_micro_ops mismatch for {}",
                    prop.mnemonic
                );
            }
        }
    }

    #[test]
    fn test_avx512_properties() {
        let db = X86MCInstrInfoFull::new();
        let vaddpsz = db.lookup("VADDPSZrr").unwrap();
        assert_eq!(vaddpsz.category, "simd");
        assert!(
            vaddpsz.encoding.prefix_bytes == 4,
            "AVX-512 uses 4-byte EVEX prefix"
        );

        let vaddpszk = db.lookup("VADDPSZrrk").unwrap();
        assert_eq!(vaddpszk.explicit_operands.len(), 4); // zmm, k, zmm, zmm
    }
}