llvm-native-core 0.1.4

//! X86 Scheduling Models — per-CPU microarchitectural scheduling information.
//!
//! Maps instructions to execution ports, latencies, and micro-op counts for
//! key Intel and AMD microarchitectures.
//!
//! Clean-room behavioral reconstruction from:
//! - Intel® 64 and IA-32 Architectures Optimization Reference Manual
//! - AMD Software Optimization Guide for AMD Family Processors
//! - Agner Fog's instruction tables (publicly available microarchitecture data)
//! - uops.info (publicly available instruction throughput/latency data)
//!
//! Supported microarchitectures:
//! - Intel Skylake Client (SKL)
//! - Intel Ice Lake Client (ICL)
//! - Intel Alder Lake P-core / Golden Cove (ADL)
//! - Intel Granite Rapids / Redwood Cove (GNR)
//! - AMD Zen 3 (ZN3)
//! - AMD Zen 4 (ZN4)
//! - AMD Zen 5 (ZN5)
//! - Intel Meteor Lake (Redwood Cove P-core + Crestmont E-core)
//! - Intel Lunar Lake (Lion Cove P-core + Skymont E-core)
//! - Intel Arrow Lake (Lion Cove + Skymont desktop)
//! - Intel Sierra Forest (Sierra Glen E-core)
//! - Intel Clearwater Forest (Darkmont E-core)
//! - AMD Zen 5c (Prometheus dense core)
//! - AMD Zen 6 (Morpheus)
//! - AMD Zen 6c (Morpheus dense)
//! - Hybrid scheduling: P-core / E-core preference hints
//! - Thread Director integration
//! - AVX-512 frequency scaling detection

use crate::mc_streamer::x86_opcodes;

// ============================================================================
// Core scheduling types
// ============================================================================

/// Processor resource: an execution port, pipeline, or functional unit.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum ProcResource {
    // Intel-style execution ports
    Port0,
    Port1,
    Port2,
    Port3,
    Port4,
    Port5,
    Port6,
    Port7,
    Port8,
    Port9,
    Port10,
    Port11,
    Port12,
    Port13,
    Port14,
    Port15,
    // AMD-style functional units
    ALU0,
    ALU1,
    ALU2,
    ALU3,
    ALU4,
    ALU5,
    AGU0,
    AGU1,
    AGU2,
    AGU3,
    FPU0,
    FPU1,
    FPU2,
    FPU3,
    // Unified resources
    UnifiedScheduler,
    LoadUnit,
    StoreUnit,
    BranchUnit,
    IntegerDivider,
    IntegerMultiplier,
    VectorALU,
    VectorShuffle,
    VectorMultiplier,
}

/// Write resource: specifies which resources a uop uses when it executes.
#[derive(Debug, Clone)]
pub struct WriteRes {
    /// The resource consumed.
    pub resource: ProcResource,
    /// Number of cycles the resource is held.
    pub cycles: u32,
}

/// Read advance: specifies how many cycles earlier a dependent instruction
/// can read the result (bypass / forwarding latency).
#[derive(Debug, Clone)]
pub struct ReadAdvance {
    /// The write resource this bypass applies to.
    pub write_resource: ProcResource,
    /// Cycles of latency reduction (0 = no bypass).
    pub cycles: u32,
}

/// Write latency: latency from an instruction producing a result to it being
/// available for a dependent instruction.
#[derive(Debug, Clone)]
pub struct WriteLatency {
    /// The resource producing the result.
    pub resource: ProcResource,
    /// Latency in cycles.
    pub cycles: u32,
}

/// Instruction itinerary: complete scheduling information for one instruction.
#[derive(Debug, Clone)]
pub struct InstrItinerary {
    /// The opcode this itinerary applies to.
    pub opcode: u32,
    /// Total latency in cycles (result production).
    pub latency: u32,
    /// Number of micro-ops this instruction decodes to.
    pub uops: u32,
    /// Write resources used by this instruction.
    pub write_resources: Vec<WriteRes>,
    /// Read advances (bypass latencies).
    pub read_advances: Vec<ReadAdvance>,
    /// Write latencies.
    pub write_latencies: Vec<WriteLatency>,
}

/// Machine model: describes the overall microarchitecture capabilities.
#[derive(Debug, Clone)]
pub struct SchedMachineModel {
    /// Microarchitecture name.
    pub name: &'static str,
    /// Maximum instructions issued per cycle (dispatch width).
    pub issue_width: u32,
    /// Size of the micro-op buffer (between decode and dispatch).
    pub micro_op_buffer_size: u32,
    /// Load latency in cycles (L1 cache hit).
    pub load_latency: u32,
    /// Store latency in cycles.
    pub store_latency: u32,
    /// High-latency operation threshold (cycles above this are "high latency").
    pub high_latency: u32,
    /// Misfetch penalty in cycles (branch misprediction cost).
    pub misfetch_penalty: u32,
    /// Reorder buffer size.
    pub rob_size: u32,
    /// Number of physical registers.
    pub phys_reg_count: u32,
    /// Whether this model supports out-of-order execution.
    pub out_of_order: bool,
    /// Number of load buffers.
    pub load_buffers: u32,
    /// Number of store buffers.
    pub store_buffers: u32,
    /// L1 instruction cache size (bytes).
    pub l1i_cache_size: u32,
    /// L1 data cache size (bytes).
    pub l1d_cache_size: u32,
    /// L2 cache size (bytes).
    pub l2_cache_size: u32,
    /// L3 cache size (bytes).
    pub l3_cache_size: u32,
}

/// Complete scheduling model for a CPU microarchitecture.
#[derive(Debug, Clone)]
pub struct SchedModel {
    /// Machine-level parameters.
    pub machine: SchedMachineModel,
    /// Available processor resources.
    pub resources: Vec<ProcResource>,
    /// Instruction itineraries.
    pub itineraries: Vec<InstrItinerary>,
}

// ============================================================================
// Intel Skylake Client (SKL)
// ============================================================================

/// Intel Skylake Client scheduling model.
///
/// Key characteristics:
/// - 8 execution ports: p0, p1, p2, p3, p4, p5, p6, p7
/// - 4-wide decode, 6-wide uop queue, 8-wide issue
/// - 224-entry ROB, 97-entry scheduler
/// - 32 KB L1i, 32 KB L1d, 256 KB L2, up to 8 MB L3
pub fn skylake_client_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Skylake Client",
        issue_width: 8,
        micro_op_buffer_size: 64,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 16,
        rob_size: 224,
        phys_reg_count: 168,
        out_of_order: true,
        load_buffers: 72,
        store_buffers: 56,
        l1i_cache_size: 32768,
        l1d_cache_size: 32768,
        l2_cache_size: 262144,
        l3_cache_size: 8388608,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
    ];

    let itineraries = skylake_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn skylake_itineraries() -> Vec<InstrItinerary> {
    vec![
        // NOP: 0-cycle, no resources
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // MOV r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // ADD r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // SUB r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // AND r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // OR r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // XOR r,r: 1 cycle, p0156 (zero idiom: eliminated at rename)
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // CMP r,r: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // LEA: 1 cycle, p1 or p5 (complex LEA) or p0156 (simple)
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        // IMUL r,r: 3 cycles, p1
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        // SHL r,1: 1 cycle, p06 (p0 or p6)
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // SHR r,1: 1 cycle, p06
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // MUL: 3-4 cycles (depends on operand size), p1
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        // DIV: 23-26 cycles (64-bit), p1, p5, p6 (microcoded)
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 23,
            uops: 36,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port0,
                    cycles: 9,
                },
                WriteRes {
                    resource: ProcResource::Port1,
                    cycles: 6,
                },
                WriteRes {
                    resource: ProcResource::Port5,
                    cycles: 9,
                },
                WriteRes {
                    resource: ProcResource::Port6,
                    cycles: 8,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 23,
            }],
        },
        // PUSH r: 1 cycle, p237 (store ports) + p4
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // POP r: 1 cycle, p237 (load ports)
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        // CALL: 1 cycle, p6 (branch)
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // RET: 1 cycle, p6 (branch)
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // JMP: 1 cycle, p6 (predicted taken branch)
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // JE/JNE: 1 cycle, p6
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // NOT/NEG: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // INC/DEC: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // TEST: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // BSWAP: 1 cycle, p1
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        // XCHG r,r: 2 cycles, p0156 (2 uops)
        InstrItinerary {
            opcode: x86_opcodes::XCHG,
            latency: 2,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 2,
            }],
        },
        // BT: 1 cycle, p06
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // BTS/BTR/BTC: 1 cycle, p06
        InstrItinerary {
            opcode: x86_opcodes::BTS,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // BSF/BSR: 3 cycles, p1
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        // MOVSX/MOVZX: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // MOVSXD: 1 cycle, p0156
        InstrItinerary {
            opcode: x86_opcodes::MOVSXD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // CMOVcc: 1-2 cycles, p06
        InstrItinerary {
            opcode: x86_opcodes::CMOVE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMOVNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // ADC/SBB: 1 cycle, p06
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SBB,
            latency: 1,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        // RDTSC: ~20 cycles, p1 (microcoded)
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 20,
            uops: 18,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 18,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 20,
            }],
        },
        // CPUID: ~100 cycles (microcoded)
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 100,
            uops: 100,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // CBW/CWDE/CDQE: eliminated at rename (0 cycles)
        InstrItinerary {
            opcode: x86_opcodes::CBW,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CWDE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CDQE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        // SYSCALL: microcoded, ~30 cycles
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 30,
            uops: 30,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Ice Lake Client (ICL)
// ============================================================================

/// Intel Ice Lake Client scheduling model.
///
/// Key characteristics:
/// - 10 execution ports: p0-p9 (wider than Skylake)
/// - 5-wide decode, 10-wide issue
/// - 352-entry ROB, 160-entry scheduler
/// - Sunny Cove microarchitecture
pub fn ice_lake_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Ice Lake Client",
        issue_width: 10,
        micro_op_buffer_size: 70,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 18,
        rob_size: 352,
        phys_reg_count: 224,
        out_of_order: true,
        load_buffers: 128,
        store_buffers: 72,
        l1i_cache_size: 32768,
        l1d_cache_size: 49152,
        l2_cache_size: 524288,
        l3_cache_size: 8388608,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
        ProcResource::Port8,
        ProcResource::Port9,
    ];

    let itineraries = ice_lake_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn ice_lake_itineraries() -> Vec<InstrItinerary> {
    // Ice Lake generally improves latencies and adds more execution ports.
    // Many simple ops remain at 1 cycle but have more port choices.
    vec![
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 17,
            uops: 18,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port0,
                    cycles: 5,
                },
                WriteRes {
                    resource: ProcResource::Port1,
                    cycles: 4,
                },
                WriteRes {
                    resource: ProcResource::Port5,
                    cycles: 5,
                },
                WriteRes {
                    resource: ProcResource::Port6,
                    cycles: 4,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 17,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XCHG,
            latency: 2,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTS,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSXD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        // CMOV: Ice Lake improves to 1 cycle for all CMOV forms
        InstrItinerary {
            opcode: x86_opcodes::CMOVE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMOVNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SBB,
            latency: 1,
            uops: 2,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 2,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 20,
            uops: 18,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 18,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 20,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 100,
            uops: 100,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 30,
            uops: 30,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Alder Lake P-Core (Golden Cove) — ADL
// ============================================================================

/// Intel Alder Lake P-core (Golden Cove) scheduling model.
///
/// Key characteristics:
/// - 12 execution ports
/// - 6-wide decode
/// - 512-entry ROB
pub fn alder_lake_pcore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Alder Lake P-core (Golden Cove)",
        issue_width: 12,
        micro_op_buffer_size: 72,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 20,
        rob_size: 512,
        phys_reg_count: 280,
        out_of_order: true,
        load_buffers: 192,
        store_buffers: 114,
        l1i_cache_size: 32768,
        l1d_cache_size: 49152,
        l2_cache_size: 1310720,
        l3_cache_size: 31457280,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
        ProcResource::Port8,
        ProcResource::Port9,
        ProcResource::Port10,
        ProcResource::Port11,
    ];

    let itineraries = alder_lake_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn alder_lake_itineraries() -> Vec<InstrItinerary> {
    vec![
        // Golden Cove further reduces some latencies.
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 14,
            uops: 16,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port0,
                    cycles: 4,
                },
                WriteRes {
                    resource: ProcResource::Port1,
                    cycles: 4,
                },
                WriteRes {
                    resource: ProcResource::Port5,
                    cycles: 4,
                },
                WriteRes {
                    resource: ProcResource::Port6,
                    cycles: 4,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 14,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 25,
            uops: 25,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Granite Rapids (Redwood Cove) — GNR
// ============================================================================

/// Intel Granite Rapids (Redwood Cove) scheduling model.
///
/// Key characteristics:
/// - 8-wide decode
/// - 8 ALU ports
/// - Server-focused core
pub fn granite_rapids_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Granite Rapids (Redwood Cove)",
        issue_width: 8,
        micro_op_buffer_size: 96,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 18,
        rob_size: 512,
        phys_reg_count: 320,
        out_of_order: true,
        load_buffers: 256,
        store_buffers: 128,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 2097152,
        l3_cache_size: 1073741824,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
    ];

    let itineraries = granite_rapids_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn granite_rapids_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 12,
            uops: 14,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 14,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 12,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 22,
            uops: 22,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 3 (ZN3)
// ============================================================================

/// AMD Zen 3 scheduling model.
///
/// Key characteristics:
/// - 4 ALU + 3 AGU ports
/// - Unified scheduler
/// - 256-entry ROB
pub fn zen3_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 3",
        issue_width: 6,
        micro_op_buffer_size: 48,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 16,
        rob_size: 256,
        phys_reg_count: 192,
        out_of_order: true,
        load_buffers: 116,
        store_buffers: 64,
        l1i_cache_size: 32768,
        l1d_cache_size: 32768,
        l2_cache_size: 524288,
        l3_cache_size: 33554432,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::FPU0,
        ProcResource::FPU1,
    ];

    let itineraries = zen3_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen3_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 17,
            uops: 17,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 17,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 17,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::AGU0,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::AGU1,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 28,
            uops: 28,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 4 (ZN4)
// ============================================================================

/// AMD Zen 4 scheduling model.
///
/// Key characteristics:
/// - 4 ALU + 3 AGU (same as Zen 3)
/// - AVX-512 double-pumping (256-bit native, 512-bit via two cycles)
/// - 320-entry ROB
pub fn zen4_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 4",
        issue_width: 6,
        micro_op_buffer_size: 64,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 16,
        rob_size: 320,
        phys_reg_count: 224,
        out_of_order: true,
        load_buffers: 120,
        store_buffers: 72,
        l1i_cache_size: 32768,
        l1d_cache_size: 32768,
        l2_cache_size: 1048576,
        l3_cache_size: 33554432,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::FPU0,
        ProcResource::FPU1,
    ];

    let itineraries = zen4_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen4_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 15,
            uops: 15,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 15,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 15,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 24,
            uops: 24,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 5 (ZN5)
// ============================================================================

/// AMD Zen 5 scheduling model.
///
/// Key characteristics:
/// - 6 ALU + 4 AGU (wider than Zen 4)
/// - Full-width AVX-512 (native 512-bit pipeline)
/// - Larger scheduler
pub fn zen5_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 5",
        issue_width: 8,
        micro_op_buffer_size: 72,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 16,
        rob_size: 448,
        phys_reg_count: 256,
        out_of_order: true,
        load_buffers: 144,
        store_buffers: 96,
        l1i_cache_size: 32768,
        l1d_cache_size: 49152,
        l2_cache_size: 1048576,
        l3_cache_size: 33554432,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::AGU3,
        ProcResource::FPU0,
        ProcResource::FPU1,
        ProcResource::FPU2,
        ProcResource::FPU3,
    ];

    let itineraries = zen5_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen5_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 12,
            uops: 12,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 12,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 12,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 20,
            uops: 20,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Meteor Lake (Redwood Cove P-core + Crestmont E-core)
// ============================================================================

/// Intel Meteor Lake P-core (Redwood Cove) scheduling model.
///
/// Key characteristics:
/// - 8 execution ports: p0-p7
/// - 6-wide decode, 8-wide issue, 8-wide retire
/// - 512-entry ROB
/// - Larger L2 cache (2 MB per P-core)
/// - Improved branch predictor (8K BTB)
pub fn meteor_lake_pcore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Meteor Lake P-core (Redwood Cove)",
        issue_width: 8,
        micro_op_buffer_size: 96,
        load_latency: 4,
        store_latency: 1,
        high_latency: 22,
        misfetch_penalty: 16,
        rob_size: 512,
        phys_reg_count: 280,
        out_of_order: true,
        load_buffers: 192,
        store_buffers: 114,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 2097152,
        l3_cache_size: 25165824,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
    ];

    let itineraries = meteor_lake_pcore_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn meteor_lake_pcore_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 17,
            uops: 24,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port0,
                    cycles: 6,
                },
                WriteRes {
                    resource: ProcResource::Port1,
                    cycles: 6,
                },
                WriteRes {
                    resource: ProcResource::Port5,
                    cycles: 6,
                },
                WriteRes {
                    resource: ProcResource::Port6,
                    cycles: 6,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 17,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SBB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTS,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CBW,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CWDE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CDQE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 20,
            uops: 18,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 18,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 20,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 100,
            uops: 100,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 30,
            uops: 30,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

/// Intel Meteor Lake E-core (Crestmont) scheduling model.
///
/// Key characteristics:
/// - In-order dual-cluster architecture (2 clusters of 3-wide decode)
/// - 6-wide decode total, 2x3-wide issue
/// - No SMT, shallow OoO window
/// - Lower power, lower peak performance
/// - Ideal for throughput-oriented background tasks
pub fn meteor_lake_ecore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Meteor Lake E-core (Crestmont)",
        issue_width: 6,
        micro_op_buffer_size: 48,
        load_latency: 5,
        store_latency: 1,
        high_latency: 18,
        misfetch_penalty: 18,
        rob_size: 128,
        phys_reg_count: 96,
        out_of_order: true,
        load_buffers: 48,
        store_buffers: 32,
        l1i_cache_size: 65536,
        l1d_cache_size: 32768,
        l2_cache_size: 2097152,
        l3_cache_size: 25165824,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::BranchUnit,
    ];

    let itineraries = meteor_lake_ecore_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn meteor_lake_ecore_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 25,
            uops: 30,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::ALU0,
                    cycles: 10,
                },
                WriteRes {
                    resource: ProcResource::ALU1,
                    cycles: 10,
                },
                WriteRes {
                    resource: ProcResource::ALU2,
                    cycles: 10,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 25,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 5,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU1,
                cycles: 5,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 120,
            uops: 120,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

/// Intel Meteor Lake hybrid scheduling model combining P-core and E-core.
///
/// This model provides thread director hints for the OS scheduler:
/// - Class 1 (EE): background tasks → E-core preferred
/// - Class 2 (efficient): throughput tasks → E-core preferred
/// - Class 3 (balanced): normal priority → any core
/// - Class 4 (performance): single-thread perf → P-core preferred
/// - Class 5 (peak): maximum performance → P-core only
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ThreadDirectorClass {
    /// Energy Efficient — background / very low priority.
    EE = 1,
    /// Efficient — throughput-oriented.
    Efficient = 2,
    /// Balanced — normal priority.
    Balanced = 3,
    /// Performance — single-thread latency sensitive.
    Performance = 4,
    /// Peak — maximum available performance.
    Peak = 5,
}

/// Thread Director hint for OS scheduling on hybrid architectures.
#[derive(Debug, Clone)]
pub struct ThreadDirectorHint {
    /// Preferred core type for this instruction stream.
    pub preferred_core: HybridCoreType,
    /// Scheduling class (1-5).
    pub class: ThreadDirectorClass,
    /// Performance/energy score (0-255).
    pub perf_score: u8,
    /// Energy efficiency score (0-255).
    pub energy_score: u8,
}

/// Hybrid core type for scheduling decisions.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum HybridCoreType {
    /// Performance core — high single-thread throughput.
    Pcore,
    /// Efficiency core — power-optimized, good multi-thread throughput.
    Ecore,
    /// Either core type is acceptable.
    Any,
}

/// Calculate a thread director hint based on instruction characteristics.
///
/// Returns a hint that helps the OS scheduler place threads optimally.
pub fn thread_director_hint(
    has_avx512: bool,
    has_branch_density_high: bool,
    is_latency_bound: bool,
    is_throughput_heavy: bool,
) -> ThreadDirectorHint {
    if has_avx512 || is_latency_bound {
        ThreadDirectorHint {
            preferred_core: HybridCoreType::Pcore,
            class: ThreadDirectorClass::Peak,
            perf_score: 255,
            energy_score: 0,
        }
    } else if has_branch_density_high {
        ThreadDirectorHint {
            preferred_core: HybridCoreType::Pcore,
            class: ThreadDirectorClass::Performance,
            perf_score: 200,
            energy_score: 50,
        }
    } else if is_throughput_heavy {
        ThreadDirectorHint {
            preferred_core: HybridCoreType::Ecore,
            class: ThreadDirectorClass::Efficient,
            perf_score: 100,
            energy_score: 180,
        }
    } else {
        ThreadDirectorHint {
            preferred_core: HybridCoreType::Any,
            class: ThreadDirectorClass::Balanced,
            perf_score: 128,
            energy_score: 128,
        }
    }
}

/// AVX-512 frequency scaling information for a specific CPU model.
#[derive(Debug, Clone)]
pub struct Avx512FreqInfo {
    /// Base frequency without AVX-512 (MHz).
    pub base_freq_mhz: u32,
    /// Frequency with AVX-512 light (scalar, 128-bit) (MHz).
    pub avx512_light_freq_mhz: u32,
    /// Frequency with AVX-512 heavy (512-bit) (MHz).
    pub avx512_heavy_freq_mhz: u32,
    /// Frequency offset per active core (MHz/core).
    pub freq_offset_per_core: u32,
    /// Maximum all-core AVX-512 frequency (MHz).
    pub all_core_avx512_max_mhz: u32,
}

impl Avx512FreqInfo {
    /// Estimate effective clock frequency given number of active AVX-512 cores.
    pub fn effective_freq_mhz(&self, active_avx512_cores: u32, is_heavy: bool) -> u32 {
        let base = if is_heavy {
            self.avx512_heavy_freq_mhz
        } else {
            self.avx512_light_freq_mhz
        };
        let offset = self
            .freq_offset_per_core
            .saturating_mul(active_avx512_cores.saturating_sub(1));
        let freq = base.saturating_sub(offset);
        freq.max(self.all_core_avx512_max_mhz)
    }

    /// Return the frequency penalty ratio for AVX-512 vs scalar code.
    pub fn avx512_penalty_ratio(&self) -> f64 {
        self.avx512_heavy_freq_mhz as f64 / self.base_freq_mhz as f64
    }

    /// Build freq info for Intel Meteor Lake.
    pub fn meteor_lake() -> Self {
        Self {
            base_freq_mhz: 3700,
            avx512_light_freq_mhz: 3200,
            avx512_heavy_freq_mhz: 2800,
            freq_offset_per_core: 100,
            all_core_avx512_max_mhz: 2400,
        }
    }

    /// Build freq info for Intel Lunar Lake.
    pub fn lunar_lake() -> Self {
        Self {
            base_freq_mhz: 4000,
            avx512_light_freq_mhz: 3500,
            avx512_heavy_freq_mhz: 3000,
            freq_offset_per_core: 100,
            all_core_avx512_max_mhz: 2600,
        }
    }

    /// Build freq info for AMD Zen 5 with AVX-512.
    pub fn zen5() -> Self {
        Self {
            base_freq_mhz: 4700,
            avx512_light_freq_mhz: 4400,
            avx512_heavy_freq_mhz: 4100,
            freq_offset_per_core: 75,
            all_core_avx512_max_mhz: 3800,
        }
    }

    /// Build freq info for AMD Zen 6.
    pub fn zen6() -> Self {
        Self {
            base_freq_mhz: 5000,
            avx512_light_freq_mhz: 4700,
            avx512_heavy_freq_mhz: 4500,
            freq_offset_per_core: 50,
            all_core_avx512_max_mhz: 4200,
        }
    }
}

// ============================================================================
// Intel Lunar Lake (Lion Cove P-core + Skymont E-core)
// ============================================================================

/// Intel Lunar Lake P-core (Lion Cove) scheduling model.
///
/// Key characteristics:
/// - 8 execution ports: p0-p7
/// - 8-wide decode, 8-wide issue, 12-wide retire
/// - 576-entry ROB (largest ever for Intel client)
/// - Hyper-threading removed for security
/// - Larger L1i (64 KB), L1d (48 KB), L2 (2.5 MB)
pub fn lunar_lake_pcore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Lunar Lake P-core (Lion Cove)",
        issue_width: 8,
        micro_op_buffer_size: 112,
        load_latency: 4,
        store_latency: 1,
        high_latency: 24,
        misfetch_penalty: 14,
        rob_size: 576,
        phys_reg_count: 320,
        out_of_order: true,
        load_buffers: 224,
        store_buffers: 128,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 2621440,
        l3_cache_size: 12582912,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
    ];

    let itineraries = lunar_lake_pcore_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn lunar_lake_pcore_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 15,
            uops: 22,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 22,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 15,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SBB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTS,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CBW,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CWDE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CDQE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 18,
            uops: 16,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 16,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 18,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 90,
            uops: 90,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 25,
            uops: 25,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

/// Intel Lunar Lake E-core (Skymont) scheduling model.
///
/// Key characteristics:
/// - 9-wide decode (3 clusters of 3-wide)
/// - Significantly improved IPC over Crestmont
/// - Larger OoO window, deeper buffers
/// - Supports AVX2 (not AVX-512)
pub fn lunar_lake_ecore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Lunar Lake E-core (Skymont)",
        issue_width: 9,
        micro_op_buffer_size: 72,
        load_latency: 5,
        store_latency: 1,
        high_latency: 18,
        misfetch_penalty: 16,
        rob_size: 192,
        phys_reg_count: 128,
        out_of_order: true,
        load_buffers: 72,
        store_buffers: 48,
        l1i_cache_size: 65536,
        l1d_cache_size: 32768,
        l2_cache_size: 2097152,
        l3_cache_size: 12582912,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::BranchUnit,
    ];

    let itineraries = lunar_lake_ecore_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn lunar_lake_ecore_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 20,
            uops: 24,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::ALU0,
                    cycles: 8,
                },
                WriteRes {
                    resource: ProcResource::ALU1,
                    cycles: 8,
                },
                WriteRes {
                    resource: ProcResource::ALU2,
                    cycles: 8,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 20,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 100,
            uops: 100,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Arrow Lake (Lion Cove + Skymont desktop)
// ============================================================================

/// Intel Arrow Lake P-core (Lion Cove desktop) scheduling model.
///
/// Key characteristics:
/// - 8 execution ports: p0-p7 (same as Lunar Lake P-core)
/// - Higher frequencies (5.7 GHz+ turbo)
/// - Larger L3 cache (36 MB for desktop)
/// - DDR5 memory support, higher memory bandwidth
pub fn arrow_lake_pcore_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Arrow Lake P-core (Lion Cove Desktop)",
        issue_width: 8,
        micro_op_buffer_size: 112,
        load_latency: 4,
        store_latency: 1,
        high_latency: 24,
        misfetch_penalty: 14,
        rob_size: 576,
        phys_reg_count: 320,
        out_of_order: true,
        load_buffers: 256,
        store_buffers: 144,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 3145728,
        l3_cache_size: 37748736,
    };

    let resources = vec![
        ProcResource::Port0,
        ProcResource::Port1,
        ProcResource::Port2,
        ProcResource::Port3,
        ProcResource::Port4,
        ProcResource::Port5,
        ProcResource::Port6,
        ProcResource::Port7,
    ];

    let itineraries = arrow_lake_pcore_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn arrow_lake_pcore_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 15,
            uops: 22,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port1,
                cycles: 22,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port1,
                cycles: 15,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 2,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::Port2,
                    cycles: 1,
                },
                WriteRes {
                    resource: ProcResource::Port4,
                    cycles: 1,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::Port2,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::Port6,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 90,
            uops: 90,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Sierra Forest (Sierra Glen E-core only)
// ============================================================================

/// Intel Sierra Forest (Sierra Glen E-core) scheduling model.
///
/// Key characteristics:
/// - E-core only server processor (up to 288 cores)
/// - Crestmont-derived microarchitecture optimized for cloud/container
/// - Dual-cluster design: 2 or 4 cores share L2
/// - No SMT, no AVX-512, full AVX2
/// - Optimized for throughput density (perf/watt, perf/area)
/// - Large shared L3 cache (up to 108 MB)
pub fn sierra_forest_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Sierra Forest (Sierra Glen)",
        issue_width: 6,
        micro_op_buffer_size: 48,
        load_latency: 5,
        store_latency: 1,
        high_latency: 22,
        misfetch_penalty: 20,
        rob_size: 128,
        phys_reg_count: 96,
        out_of_order: true,
        load_buffers: 48,
        store_buffers: 32,
        l1i_cache_size: 65536,
        l1d_cache_size: 32768,
        l2_cache_size: 4194304,
        l3_cache_size: 113246208,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::BranchUnit,
    ];

    let itineraries = sierra_forest_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn sierra_forest_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 28,
            uops: 32,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::ALU0,
                    cycles: 12,
                },
                WriteRes {
                    resource: ProcResource::ALU1,
                    cycles: 10,
                },
                WriteRes {
                    resource: ProcResource::ALU2,
                    cycles: 10,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 28,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 5,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU1,
                cycles: 5,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 130,
            uops: 130,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// Intel Clearwater Forest (Darkmont E-core)
// ============================================================================

/// Intel Clearwater Forest (Darkmont E-core) scheduling model.
///
/// Key characteristics:
/// - Next-gen E-core (Darkmont) for servers, up to 384 cores
/// - Improved single-thread performance over Sierra Glen
/// - Wider decode (9-wide, 3 clusters of 3-wide)
/// - Larger OoO resources, deeper ROB
/// - Intel 18A process technology
pub fn clearwater_forest_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "Intel Clearwater Forest (Darkmont)",
        issue_width: 9,
        micro_op_buffer_size: 72,
        load_latency: 5,
        store_latency: 1,
        high_latency: 24,
        misfetch_penalty: 18,
        rob_size: 224,
        phys_reg_count: 144,
        out_of_order: true,
        load_buffers: 80,
        store_buffers: 48,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 4194304,
        l3_cache_size: 150994944,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::BranchUnit,
    ];

    let itineraries = clearwater_forest_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn clearwater_forest_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 18,
            uops: 20,
            write_resources: vec![
                WriteRes {
                    resource: ProcResource::ALU0,
                    cycles: 8,
                },
                WriteRes {
                    resource: ProcResource::ALU1,
                    cycles: 6,
                },
                WriteRes {
                    resource: ProcResource::ALU2,
                    cycles: 6,
                },
            ],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 18,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 5,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU1,
                cycles: 5,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 100,
            uops: 100,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 5c (Prometheus dense core)
// ============================================================================

/// AMD Zen 5c (Prometheus dense core) scheduling model.
///
/// Key characteristics:
/// - Compact version of Zen 5 (same ISA, smaller physical design)
/// - Same Zen 5 core but with reduced L3 cache per core
/// - 2x density vs Zen 5, ideal for cloud/container workloads
/// - Reduced pipeline resources: smaller ROB, fewer load/store buffers
/// - Same dispatch width, lower peak frequency
/// - Optimized for throughput density
pub fn zen5c_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 5c (Prometheus Dense)",
        issue_width: 6,
        micro_op_buffer_size: 48,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 18,
        rob_size: 256,
        phys_reg_count: 224,
        out_of_order: true,
        load_buffers: 72,
        store_buffers: 48,
        l1i_cache_size: 32768,
        l1d_cache_size: 32768,
        l2_cache_size: 1048576,
        l3_cache_size: 16777216,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::AGU3,
        ProcResource::FPU0,
        ProcResource::FPU1,
        ProcResource::FPU2,
        ProcResource::FPU3,
        ProcResource::BranchUnit,
    ];

    let itineraries = zen5c_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen5c_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 15,
            uops: 15,
            write_resources: vec![WriteRes {
                resource: ProcResource::IntegerDivider,
                cycles: 15,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::IntegerDivider,
                cycles: 15,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTS,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BTC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CBW,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CWDE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CDQE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 25,
            uops: 22,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 22,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 25,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 110,
            uops: 110,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 35,
            uops: 35,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 6 (Morpheus)
// ============================================================================

/// AMD Zen 6 (Morpheus) scheduling model.
///
/// Key characteristics:
/// - 8-wide decode (up from 6-wide in Zen 5)
/// - Full 512-bit datapath (single cycle 512-bit operations)
/// - 8 ALU ports + 4 AGU ports
/// - Improved branch predictor with 16K BTB
/// - Larger structures: 640-entry ROB, 384 physical registers
/// - AVX-512 with full throughput (no port sharing penalty)
/// - AI acceleration instructions (AVX-512 VNNI, BF16)
pub fn zen6_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 6 (Morpheus)",
        issue_width: 8,
        micro_op_buffer_size: 80,
        load_latency: 4,
        store_latency: 1,
        high_latency: 22,
        misfetch_penalty: 14,
        rob_size: 640,
        phys_reg_count: 384,
        out_of_order: true,
        load_buffers: 144,
        store_buffers: 96,
        l1i_cache_size: 65536,
        l1d_cache_size: 49152,
        l2_cache_size: 2097152,
        l3_cache_size: 67108864,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::AGU3,
        ProcResource::FPU0,
        ProcResource::FPU1,
        ProcResource::FPU2,
        ProcResource::FPU3,
        ProcResource::VectorALU,
        ProcResource::VectorMultiplier,
        ProcResource::VectorShuffle,
        ProcResource::BranchUnit,
    ];

    let itineraries = zen6_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen6_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 10,
            uops: 10,
            write_resources: vec![WriteRes {
                resource: ProcResource::IntegerDivider,
                cycles: 10,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::IntegerDivider,
                cycles: 10,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NOT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::NEG,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::TEST,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SBB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSWAP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::PUSH,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::POP,
            latency: 4,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::AGU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::AGU0,
                cycles: 4,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SAR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ROR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVSX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOVZX,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BT,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSF,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::BSR,
            latency: 3,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 3,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CBW,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CWDE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CDQE,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RDTSC,
            latency: 15,
            uops: 12,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 12,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 15,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 80,
            uops: 80,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::SYSCALL,
            latency: 18,
            uops: 18,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

// ============================================================================
// AMD Zen 6c (Morpheus dense)
// ============================================================================

/// AMD Zen 6c (Morpheus dense core) scheduling model.
///
/// Key characteristics:
/// - Compact version of Zen 6, same ISA, half the area
/// - 6-wide decode
/// - Smaller ROB (384), fewer physical registers (256)
/// - Reduced L3 cache per core
/// - Same full AVX-512 datapath (shared with Zen 6)
/// - Optimized for cost/core, cloud-native workloads
pub fn zen6c_model() -> SchedModel {
    let machine = SchedMachineModel {
        name: "AMD Zen 6c (Morpheus Dense)",
        issue_width: 6,
        micro_op_buffer_size: 64,
        load_latency: 4,
        store_latency: 1,
        high_latency: 20,
        misfetch_penalty: 16,
        rob_size: 384,
        phys_reg_count: 256,
        out_of_order: true,
        load_buffers: 96,
        store_buffers: 64,
        l1i_cache_size: 32768,
        l1d_cache_size: 32768,
        l2_cache_size: 1048576,
        l3_cache_size: 33554432,
    };

    let resources = vec![
        ProcResource::ALU0,
        ProcResource::ALU1,
        ProcResource::ALU2,
        ProcResource::ALU3,
        ProcResource::ALU4,
        ProcResource::ALU5,
        ProcResource::AGU0,
        ProcResource::AGU1,
        ProcResource::AGU2,
        ProcResource::FPU0,
        ProcResource::FPU1,
        ProcResource::FPU2,
        ProcResource::FPU3,
        ProcResource::BranchUnit,
    ];

    let itineraries = zen6c_itineraries();

    SchedModel {
        machine,
        resources,
        itineraries,
    }
}

fn zen6c_itineraries() -> Vec<InstrItinerary> {
    vec![
        InstrItinerary {
            opcode: x86_opcodes::NOP,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::MOV,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::ADD,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SUB,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::AND,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU2,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::OR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::XOR,
            latency: 0,
            uops: 0,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::LEA,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU5,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::IMUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::MUL,
            latency: 2,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU3,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU3,
                cycles: 2,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DIV,
            latency: 12,
            uops: 12,
            write_resources: vec![WriteRes {
                resource: ProcResource::IntegerDivider,
                cycles: 12,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::IntegerDivider,
                cycles: 12,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::SHR,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU4,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::INC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU0,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::DEC,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![WriteLatency {
                resource: ProcResource::ALU1,
                cycles: 1,
            }],
        },
        InstrItinerary {
            opcode: x86_opcodes::JMP,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::JNE,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CALL,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::RET,
            latency: 1,
            uops: 1,
            write_resources: vec![WriteRes {
                resource: ProcResource::BranchUnit,
                cycles: 1,
            }],
            read_advances: vec![],
            write_latencies: vec![],
        },
        InstrItinerary {
            opcode: x86_opcodes::CPUID,
            latency: 90,
            uops: 90,
            write_resources: vec![],
            read_advances: vec![],
            write_latencies: vec![],
        },
    ]
}

/// Hybrid scheduling decision: given a hybrid architecture, decide which
/// core type to prefer for the current scheduling region.
#[derive(Debug, Clone)]
pub struct HybridSchedDecision {
    /// Preferred core type.
    pub core_type: HybridCoreType,
    /// Reason for the decision.
    pub reason: &'static str,
    /// Whether AVX-512 is available on this core.
    pub avx512_available: bool,
}

/// Make a scheduling decision for a hybrid architecture.
pub fn hybrid_sched_decision(
    has_pcores: bool,
    has_ecores: bool,
    is_single_thread_bound: bool,
    has_avx512_instructions: bool,
    is_low_power_mode: bool,
    thread_count: u32,
) -> HybridSchedDecision {
    if !has_pcores && has_ecores {
        return HybridSchedDecision {
            core_type: HybridCoreType::Ecore,
            reason: "Only E-cores available",
            avx512_available: false,
        };
    }
    if !has_ecores && has_pcores {
        return HybridSchedDecision {
            core_type: HybridCoreType::Pcore,
            reason: "Only P-cores available",
            avx512_available: true,
        };
    }

    // Hybrid architecture: both P and E cores available
    if has_avx512_instructions {
        return HybridSchedDecision {
            core_type: HybridCoreType::Pcore,
            reason: "AVX-512 requires P-core",
            avx512_available: true,
        };
    }
    if is_single_thread_bound {
        return HybridSchedDecision {
            core_type: HybridCoreType::Pcore,
            reason: "Single-thread latency prefers P-core",
            avx512_available: true,
        };
    }
    if is_low_power_mode || thread_count > 8 {
        return HybridSchedDecision {
            core_type: HybridCoreType::Ecore,
            reason: "Throughput / power efficiency prefers E-core",
            avx512_available: false,
        };
    }

    HybridSchedDecision {
        core_type: HybridCoreType::Any,
        reason: "Balanced: any core acceptable",
        avx512_available: false,
    }
}

// ============================================================================
// Scheduling model lookup & helpers
// ============================================================================

/// Available X86 scheduling models.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86SchedModelKind {
    SkylakeClient,
    IceLake,
    IceLakeClient,
    AlderLakePcore,
    AlderLakeP,
    GraniteRapids,
    Zen3,
    Zen4,
    Zen5,
    MeteorLakePcore,
    MeteorLakeEcore,
    LunarLakePcore,
    LunarLakeEcore,
    ArrowLakePcore,
    SierraForest,
    ClearwaterForest,
    Zen5c,
    Zen6,
    Zen6c,
    SandyBridge,
    IvyBridge,
    Haswell,
    Broadwell,
    Goldmont,
    GoldmontPlus,
    Generic,
}

impl X86SchedModelKind {
    /// Get the scheduling model for this CPU type.
    pub fn model(self) -> SchedModel {
        match self {
            X86SchedModelKind::SkylakeClient => skylake_client_model(),
            X86SchedModelKind::IceLake => ice_lake_model(),
            X86SchedModelKind::AlderLakePcore => alder_lake_pcore_model(),
            X86SchedModelKind::GraniteRapids => granite_rapids_model(),
            X86SchedModelKind::Zen3 => zen3_model(),
            X86SchedModelKind::Zen4 => zen4_model(),
            X86SchedModelKind::Zen5 => zen5_model(),
            X86SchedModelKind::MeteorLakePcore => meteor_lake_pcore_model(),
            X86SchedModelKind::MeteorLakeEcore => meteor_lake_ecore_model(),
            X86SchedModelKind::LunarLakePcore => lunar_lake_pcore_model(),
            X86SchedModelKind::LunarLakeEcore => lunar_lake_ecore_model(),
            X86SchedModelKind::ArrowLakePcore => arrow_lake_pcore_model(),
            X86SchedModelKind::SierraForest => sierra_forest_model(),
            X86SchedModelKind::ClearwaterForest => clearwater_forest_model(),
            X86SchedModelKind::Zen5c => zen5c_model(),
            X86SchedModelKind::Zen6 => zen6_model(),
            X86SchedModelKind::Zen6c => zen6c_model(),
            X86SchedModelKind::IceLakeClient => ice_lake_model(),
            X86SchedModelKind::AlderLakeP => alder_lake_pcore_model(),
            X86SchedModelKind::SandyBridge => skylake_client_model(),
            X86SchedModelKind::IvyBridge => skylake_client_model(),
            X86SchedModelKind::Haswell => skylake_client_model(),
            X86SchedModelKind::Broadwell => skylake_client_model(),
            X86SchedModelKind::Goldmont => skylake_client_model(),
            X86SchedModelKind::GoldmontPlus => skylake_client_model(),
            X86SchedModelKind::Generic => skylake_client_model(),
        }
    }

    /// Get a human-readable name for this model.
    pub fn name(self) -> &'static str {
        match self {
            X86SchedModelKind::SkylakeClient => "Intel Skylake Client",
            X86SchedModelKind::IceLake => "Intel Ice Lake",
            X86SchedModelKind::AlderLakePcore => "Intel Alder Lake (Golden Cove)",
            X86SchedModelKind::GraniteRapids => "Intel Granite Rapids (Redwood Cove)",
            X86SchedModelKind::Zen3 => "AMD Zen 3",
            X86SchedModelKind::Zen4 => "AMD Zen 4",
            X86SchedModelKind::Zen5 => "AMD Zen 5",
            X86SchedModelKind::MeteorLakePcore => "Intel Meteor Lake P-core (Redwood Cove)",
            X86SchedModelKind::MeteorLakeEcore => "Intel Meteor Lake E-core (Crestmont)",
            X86SchedModelKind::LunarLakePcore => "Intel Lunar Lake P-core (Lion Cove)",
            X86SchedModelKind::LunarLakeEcore => "Intel Lunar Lake E-core (Skymont)",
            X86SchedModelKind::ArrowLakePcore => "Intel Arrow Lake P-core (Lion Cove Desktop)",
            X86SchedModelKind::SierraForest => "Intel Sierra Forest (Sierra Glen)",
            X86SchedModelKind::ClearwaterForest => "Intel Clearwater Forest (Darkmont)",
            X86SchedModelKind::Zen5c => "AMD Zen 5c (Prometheus Dense)",
            X86SchedModelKind::Zen6 => "AMD Zen 6 (Morpheus)",
            X86SchedModelKind::Zen6c => "AMD Zen 6c (Morpheus Dense)",
            X86SchedModelKind::IceLakeClient => "Intel Ice Lake Client",
            X86SchedModelKind::AlderLakeP => "Intel Alder Lake P-core",
            X86SchedModelKind::SandyBridge => "Intel Sandy Bridge",
            X86SchedModelKind::IvyBridge => "Intel Ivy Bridge",
            X86SchedModelKind::Haswell => "Intel Haswell",
            X86SchedModelKind::Broadwell => "Intel Broadwell",
            X86SchedModelKind::Goldmont => "Intel Goldmont",
            X86SchedModelKind::GoldmontPlus => "Intel Goldmont Plus",
            X86SchedModelKind::Generic => "Generic X86",
        }
    }

    /// Returns true if this model is a P-core (performance core).
    pub fn is_pcore(self) -> bool {
        matches!(
            self,
            X86SchedModelKind::SkylakeClient
                | X86SchedModelKind::IceLake
                | X86SchedModelKind::AlderLakePcore
                | X86SchedModelKind::GraniteRapids
                | X86SchedModelKind::Zen3
                | X86SchedModelKind::Zen4
                | X86SchedModelKind::Zen5
                | X86SchedModelKind::MeteorLakePcore
                | X86SchedModelKind::LunarLakePcore
                | X86SchedModelKind::ArrowLakePcore
                | X86SchedModelKind::Zen6
                | X86SchedModelKind::IceLakeClient
                | X86SchedModelKind::AlderLakeP
                | X86SchedModelKind::SandyBridge
                | X86SchedModelKind::IvyBridge
                | X86SchedModelKind::Haswell
                | X86SchedModelKind::Broadwell
                | X86SchedModelKind::Generic
        )
    }

    /// Returns true if this model is an E-core (efficiency core).
    pub fn is_ecore(self) -> bool {
        matches!(
            self,
            X86SchedModelKind::MeteorLakeEcore
                | X86SchedModelKind::LunarLakeEcore
                | X86SchedModelKind::SierraForest
                | X86SchedModelKind::ClearwaterForest
        )
    }

    /// Returns true if this is a dense/compact core variant.
    pub fn is_dense(self) -> bool {
        matches!(self, X86SchedModelKind::Zen5c | X86SchedModelKind::Zen6c)
    }

    /// Returns true if this model supports AVX-512 instructions.
    pub fn has_avx512(self) -> bool {
        matches!(
            self,
            X86SchedModelKind::SkylakeClient
                | X86SchedModelKind::IceLake
                | X86SchedModelKind::AlderLakePcore
                | X86SchedModelKind::GraniteRapids
                | X86SchedModelKind::Zen4
                | X86SchedModelKind::Zen5
                | X86SchedModelKind::Zen5c
                | X86SchedModelKind::Zen6
                | X86SchedModelKind::Zen6c
                | X86SchedModelKind::MeteorLakePcore
                | X86SchedModelKind::LunarLakePcore
                | X86SchedModelKind::ArrowLakePcore
                | X86SchedModelKind::IceLakeClient
                | X86SchedModelKind::AlderLakeP
        )
    }
}

/// Look up the itinerary for a specific opcode in a given model.
pub fn lookup_itinerary(model: &SchedModel, opcode: u32) -> Option<&InstrItinerary> {
    model.itineraries.iter().find(|i| i.opcode == opcode)
}

/// Get the total latency for an opcode in a given model.
pub fn instruction_latency(model: &SchedModel, opcode: u32) -> Option<u32> {
    lookup_itinerary(model, opcode).map(|i| i.latency)
}

/// Get the uop count for an opcode in a given model.
pub fn instruction_uops(model: &SchedModel, opcode: u32) -> Option<u32> {
    lookup_itinerary(model, opcode).map(|i| i.uops)
}

/// Get the resources used by an instruction in a given model.
pub fn instruction_resources(model: &SchedModel, opcode: u32) -> Vec<ProcResource> {
    lookup_itinerary(model, opcode)
        .map(|i| i.write_resources.iter().map(|wr| wr.resource).collect())
        .unwrap_or_default()
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_skylake_model_exists() {
        let model = skylake_client_model();
        assert_eq!(model.machine.name, "Intel Skylake Client");
        assert_eq!(model.machine.issue_width, 8);
        assert_eq!(model.machine.rob_size, 224);
        assert!(!model.itineraries.is_empty());
    }

    #[test]
    fn test_icelake_model_exists() {
        let model = ice_lake_model();
        assert_eq!(model.machine.name, "Intel Ice Lake Client");
        assert_eq!(model.machine.issue_width, 10);
        assert_eq!(model.machine.rob_size, 352);
    }

    #[test]
    fn test_alderlake_model_exists() {
        let model = alder_lake_pcore_model();
        assert_eq!(model.machine.rob_size, 512);
    }

    #[test]
    fn test_granite_rapids_model_exists() {
        let model = granite_rapids_model();
        assert_eq!(model.machine.name, "Intel Granite Rapids (Redwood Cove)");
    }

    #[test]
    fn test_zen3_model_exists() {
        let model = zen3_model();
        assert_eq!(model.machine.name, "AMD Zen 3");
        assert_eq!(model.machine.rob_size, 256);
    }

    #[test]
    fn test_zen4_model_exists() {
        let model = zen4_model();
        assert_eq!(model.machine.name, "AMD Zen 4");
        assert_eq!(model.machine.rob_size, 320);
    }

    #[test]
    fn test_zen5_model_exists() {
        let model = zen5_model();
        assert_eq!(model.machine.name, "AMD Zen 5");
        assert_eq!(model.machine.rob_size, 448);
    }

    #[test]
    fn test_lookup_itinerary_add() {
        let model = skylake_client_model();
        let itinerary = lookup_itinerary(&model, x86_opcodes::ADD);
        assert!(itinerary.is_some());
        assert_eq!(itinerary.unwrap().latency, 1);
    }

    #[test]
    fn test_lookup_itinerary_mov() {
        let model = skylake_client_model();
        let itinerary = lookup_itinerary(&model, x86_opcodes::MOV);
        assert!(itinerary.is_some());
    }

    #[test]
    fn test_lookup_itinerary_div() {
        let model = skylake_client_model();
        let itinerary = lookup_itinerary(&model, x86_opcodes::DIV);
        assert!(itinerary.is_some());
        assert!(itinerary.unwrap().latency > 10); // DIV is always slow
    }

    #[test]
    fn test_lookup_missing_opcode() {
        let model = skylake_client_model();
        // SYSRET (98) is not in the itinerary — should return None
        let itinerary = lookup_itinerary(&model, 9999);
        assert!(itinerary.is_none());
    }

    #[test]
    fn test_xor_zero_latency() {
        // XOR same-register is eliminated at rename
        let model = skylake_client_model();
        let itinerary = lookup_itinerary(&model, x86_opcodes::XOR).unwrap();
        assert_eq!(itinerary.latency, 0);
        assert_eq!(itinerary.uops, 0);
    }

    #[test]
    fn test_model_kind_enum() {
        let kinds = vec![
            X86SchedModelKind::SkylakeClient,
            X86SchedModelKind::IceLake,
            X86SchedModelKind::AlderLakePcore,
            X86SchedModelKind::GraniteRapids,
            X86SchedModelKind::Zen3,
            X86SchedModelKind::Zen4,
            X86SchedModelKind::Zen5,
        ];
        for kind in kinds {
            let model = kind.model();
            assert!(!model.itineraries.is_empty());
            assert!(!kind.name().is_empty());
        }
    }

    #[test]
    fn test_instruction_latency_helper() {
        let model = skylake_client_model();
        assert_eq!(instruction_latency(&model, x86_opcodes::ADD), Some(1));
        assert_eq!(instruction_latency(&model, x86_opcodes::MOV), Some(1));
        assert_eq!(instruction_latency(&model, x86_opcodes::XOR), Some(0));
        assert_eq!(instruction_latency(&model, 99999), None);
    }

    #[test]
    fn test_instruction_uops_helper() {
        let model = skylake_client_model();
        assert_eq!(instruction_uops(&model, x86_opcodes::ADD), Some(1));
        assert_eq!(instruction_uops(&model, x86_opcodes::XOR), Some(0));
        assert_eq!(instruction_uops(&model, x86_opcodes::DIV), Some(36));
    }

    #[test]
    fn test_instruction_resources_helper() {
        let model = skylake_client_model();
        let resources = instruction_resources(&model, x86_opcodes::DIV);
        assert!(!resources.is_empty()); // DIV uses multiple ports
    }

    #[test]
    fn test_meteor_lake_pcore_model_exists() {
        let model = meteor_lake_pcore_model();
        assert_eq!(
            model.machine.name,
            "Intel Meteor Lake P-core (Redwood Cove)"
        );
        assert_eq!(model.machine.rob_size, 512);
        assert_eq!(model.machine.issue_width, 8);
    }

    #[test]
    fn test_meteor_lake_ecore_model_exists() {
        let model = meteor_lake_ecore_model();
        assert_eq!(model.machine.name, "Intel Meteor Lake E-core (Crestmont)");
        assert_eq!(model.machine.rob_size, 128);
        assert_eq!(model.machine.issue_width, 6);
    }

    #[test]
    fn test_lunar_lake_pcore_model_exists() {
        let model = lunar_lake_pcore_model();
        assert_eq!(model.machine.rob_size, 576);
        assert_eq!(model.machine.issue_width, 8);
    }

    #[test]
    fn test_lunar_lake_ecore_model_exists() {
        let model = lunar_lake_ecore_model();
        assert_eq!(model.machine.rob_size, 192);
        assert_eq!(model.machine.issue_width, 9);
    }

    #[test]
    fn test_sierra_forest_model_exists() {
        let model = sierra_forest_model();
        assert_eq!(model.machine.name, "Intel Sierra Forest (Sierra Glen)");
        assert_eq!(model.machine.rob_size, 128);
    }

    #[test]
    fn test_clearwater_forest_model_exists() {
        let model = clearwater_forest_model();
        assert_eq!(model.machine.rob_size, 224);
        assert_eq!(model.machine.issue_width, 9);
    }

    #[test]
    fn test_zen5c_model_exists() {
        let model = zen5c_model();
        assert_eq!(model.machine.name, "AMD Zen 5c (Prometheus Dense)");
        assert_eq!(model.machine.issue_width, 6);
    }

    #[test]
    fn test_zen6_model_exists() {
        let model = zen6_model();
        assert_eq!(model.machine.name, "AMD Zen 6 (Morpheus)");
        assert_eq!(model.machine.rob_size, 640);
        assert_eq!(model.machine.issue_width, 8);
    }

    #[test]
    fn test_zen6c_model_exists() {
        let model = zen6c_model();
        assert_eq!(model.machine.rob_size, 384);
        assert_eq!(model.machine.issue_width, 6);
    }

    #[test]
    fn test_model_kind_enum_all() {
        let kinds = vec![
            X86SchedModelKind::SkylakeClient,
            X86SchedModelKind::IceLake,
            X86SchedModelKind::AlderLakePcore,
            X86SchedModelKind::GraniteRapids,
            X86SchedModelKind::Zen3,
            X86SchedModelKind::Zen4,
            X86SchedModelKind::Zen5,
            X86SchedModelKind::MeteorLakePcore,
            X86SchedModelKind::MeteorLakeEcore,
            X86SchedModelKind::LunarLakePcore,
            X86SchedModelKind::LunarLakeEcore,
            X86SchedModelKind::ArrowLakePcore,
            X86SchedModelKind::SierraForest,
            X86SchedModelKind::ClearwaterForest,
            X86SchedModelKind::Zen5c,
            X86SchedModelKind::Zen6,
            X86SchedModelKind::Zen6c,
        ];
        for kind in kinds {
            let model = kind.model();
            assert!(!model.itineraries.is_empty());
            assert!(!kind.name().is_empty());
        }
    }

    #[test]
    fn test_is_pcore_ecore_dense() {
        assert!(X86SchedModelKind::MeteorLakePcore.is_pcore());
        assert!(!X86SchedModelKind::MeteorLakePcore.is_ecore());
        assert!(X86SchedModelKind::MeteorLakeEcore.is_ecore());
        assert!(!X86SchedModelKind::MeteorLakeEcore.is_pcore());
        assert!(X86SchedModelKind::Zen5c.is_dense());
        assert!(!X86SchedModelKind::Zen5.is_dense());
        assert!(X86SchedModelKind::Zen6c.is_dense());
    }

    #[test]
    fn test_has_avx512() {
        assert!(X86SchedModelKind::Zen5.has_avx512());
        assert!(X86SchedModelKind::Zen6.has_avx512());
        assert!(!X86SchedModelKind::Zen3.has_avx512());
        assert!(!X86SchedModelKind::SierraForest.has_avx512());
        assert!(X86SchedModelKind::LunarLakePcore.has_avx512());
        assert!(!X86SchedModelKind::LunarLakeEcore.has_avx512());
    }

    #[test]
    fn test_thread_director_hint_avx512() {
        let hint = thread_director_hint(true, false, false, false);
        assert_eq!(hint.preferred_core, HybridCoreType::Pcore);
        assert_eq!(hint.class, ThreadDirectorClass::Peak);
        assert_eq!(hint.perf_score, 255);
    }

    #[test]
    fn test_thread_director_hint_latency() {
        let hint = thread_director_hint(false, false, true, false);
        assert_eq!(hint.preferred_core, HybridCoreType::Pcore);
    }

    #[test]
    fn test_thread_director_hint_throughput() {
        let hint = thread_director_hint(false, false, false, true);
        assert_eq!(hint.preferred_core, HybridCoreType::Ecore);
        assert_eq!(hint.class, ThreadDirectorClass::Efficient);
    }

    #[test]
    fn test_thread_director_hint_balanced() {
        let hint = thread_director_hint(false, false, false, false);
        assert_eq!(hint.preferred_core, HybridCoreType::Any);
        assert_eq!(hint.class, ThreadDirectorClass::Balanced);
    }

    #[test]
    fn test_hybrid_sched_decision_pcores_only() {
        let dec = hybrid_sched_decision(true, false, false, false, false, 1);
        assert_eq!(dec.core_type, HybridCoreType::Pcore);
        assert_eq!(dec.reason, "Only P-cores available");
    }

    #[test]
    fn test_hybrid_sched_decision_ecores_only() {
        let dec = hybrid_sched_decision(false, true, false, false, false, 1);
        assert_eq!(dec.core_type, HybridCoreType::Ecore);
    }

    #[test]
    fn test_hybrid_sched_decision_avx512() {
        let dec = hybrid_sched_decision(true, true, false, true, false, 4);
        assert_eq!(dec.core_type, HybridCoreType::Pcore);
        assert_eq!(dec.reason, "AVX-512 requires P-core");
    }

    #[test]
    fn test_hybrid_sched_decision_single_thread() {
        let dec = hybrid_sched_decision(true, true, true, false, false, 1);
        assert_eq!(dec.core_type, HybridCoreType::Pcore);
    }

    #[test]
    fn test_hybrid_sched_decision_low_power() {
        let dec = hybrid_sched_decision(true, true, false, false, true, 4);
        assert_eq!(dec.core_type, HybridCoreType::Ecore);
    }

    #[test]
    fn test_avx512_freq_info_meteor_lake() {
        let info = Avx512FreqInfo::meteor_lake();
        assert_eq!(info.base_freq_mhz, 3700);
        let eff = info.effective_freq_mhz(2, true);
        assert!(eff >= info.all_core_avx512_max_mhz);
        assert!(eff <= info.avx512_heavy_freq_mhz);
    }

    #[test]
    fn test_avx512_freq_info_lunar_lake() {
        let info = Avx512FreqInfo::lunar_lake();
        assert_eq!(info.base_freq_mhz, 4000);
        assert!(info.avx512_penalty_ratio() > 0.0 && info.avx512_penalty_ratio() <= 1.0);
    }

    #[test]
    fn test_avx512_freq_info_zen5() {
        let info = Avx512FreqInfo::zen5();
        assert_eq!(info.base_freq_mhz, 4700);
        let eff = info.effective_freq_mhz(4, false);
        assert!(eff >= info.all_core_avx512_max_mhz);
    }

    #[test]
    fn test_avx512_freq_info_zen6() {
        let info = Avx512FreqInfo::zen6();
        assert_eq!(info.base_freq_mhz, 5000);
        assert!(info.avx512_penalty_ratio() > 0.8);
    }

    #[test]
    fn test_arrow_lake_pcore_model() {
        let model = arrow_lake_pcore_model();
        assert_eq!(
            model.machine.name,
            "Intel Arrow Lake P-core (Lion Cove Desktop)"
        );
        assert_eq!(model.machine.rob_size, 576);
    }

    #[test]
    fn test_all_models_have_itineraries() {
        let models = vec![
            meteor_lake_pcore_model(),
            meteor_lake_ecore_model(),
            lunar_lake_pcore_model(),
            lunar_lake_ecore_model(),
            arrow_lake_pcore_model(),
            sierra_forest_model(),
            clearwater_forest_model(),
            zen5c_model(),
            zen6_model(),
            zen6c_model(),
        ];
        for model in models {
            assert!(
                !model.itineraries.is_empty(),
                "Model {} has empty itineraries",
                model.machine.name
            );
            assert!(model.machine.issue_width > 0);
            assert!(model.machine.rob_size > 0);
        }
    }

    #[test]
    fn test_all_models_have_valid_cache_sizes() {
        let models = vec![
            meteor_lake_pcore_model(),
            lunar_lake_pcore_model(),
            zen6_model(),
            zen5c_model(),
        ];
        for model in models {
            assert!(model.machine.l1i_cache_size > 0);
            assert!(model.machine.l1d_cache_size > 0);
            assert!(model.machine.l2_cache_size > 0);
            assert!(model.machine.l3_cache_size > 0);
        }
    }

    #[test]
    fn test_hybrid_sched_decision_balanced() {
        let dec = hybrid_sched_decision(true, true, false, false, false, 2);
        assert_eq!(dec.core_type, HybridCoreType::Any);
    }

    #[test]
    fn test_thread_director_hint_branch_density() {
        let hint = thread_director_hint(false, true, false, false);
        assert_eq!(hint.preferred_core, HybridCoreType::Pcore);
        assert_eq!(hint.class, ThreadDirectorClass::Performance);
    }

    #[test]
    fn test_avx512_freq_info_effective_freq() {
        let info = Avx512FreqInfo::meteor_lake();
        // No AVX-512 cores active: same as light
        let eff = info.effective_freq_mhz(0, false);
        assert_eq!(eff, 3200);
        // Multiple heavy AVX-512 cores: drops
        let heavy = info.effective_freq_mhz(8, true);
        assert_eq!(heavy, 2800 - 700); // base - 7 * 100
    }

    #[test]
    fn test_has_avx512_all_models() {
        assert!(!X86SchedModelKind::MeteorLakeEcore.has_avx512());
        assert!(!X86SchedModelKind::ClearwaterForest.has_avx512());
        assert!(X86SchedModelKind::Zen5c.has_avx512());
        assert!(X86SchedModelKind::Zen6c.has_avx512());
    }
}