llvm-native-core 0.1.4

//! X86 Machine Code Encoder — encodes MachineInstrs into binary X86 instruction
//! bytes per Intel SDM Volume 2.
//!
//! Clean-room behavioral reconstruction from:
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2
//! - AMD64 Architecture Programmer's Manual, Volume 3
//!
//! The encoder walks through MachineInstr objects (which use virtual or physical
//! register operands) and emits the corresponding X86 binary byte sequences,
//! including legacy prefixes, REX/VEX/EVEX prefixes, opcode bytes, ModR/M,
//! SIB, displacement, and immediate.

use crate::codegen::{MachineFunction, MachineInstr, MachineOperand};
use crate::mc_streamer::x86_opcodes;
use crate::x86::x86_instr_info::X86Opcode;
use crate::x86::x86_subtarget::X86Subtarget;

// ============================================================================
// X86Mode — operating mode
// ============================================================================

/// X86 operating mode determines default operand and address sizes.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86Mode {
    /// 16-bit mode (real mode, 8086/80286)
    Mode16,
    /// 32-bit mode (protected mode, IA-32)
    Mode32,
    /// 64-bit mode (long mode, x86-64)
    Mode64,
}

impl X86Mode {
    /// Returns true if in 64-bit mode.
    pub fn is_64bit(self) -> bool {
        matches!(self, X86Mode::Mode64)
    }

    /// Returns the default operand size in bytes for this mode.
    pub fn default_operand_size(self) -> u8 {
        match self {
            X86Mode::Mode16 => 2,
            X86Mode::Mode32 => 4,
            X86Mode::Mode64 => 4, // 64-bit mode defaults to 32-bit operands
        }
    }

    /// Returns the default address size in bytes for this mode.
    pub fn default_address_size(self) -> u8 {
        match self {
            X86Mode::Mode16 => 2,
            X86Mode::Mode32 => 4,
            X86Mode::Mode64 => 8,
        }
    }
}

// ============================================================================
// Prefix byte constants
// ============================================================================

/// Legacy prefix bytes.
pub mod prefixes {
    pub const LOCK: u8 = 0xF0;
    pub const REPNE: u8 = 0xF2;
    pub const REP: u8 = 0xF3;
    pub const CS_OVERRIDE: u8 = 0x2E;
    pub const SS_OVERRIDE: u8 = 0x36;
    pub const DS_OVERRIDE: u8 = 0x3E;
    pub const ES_OVERRIDE: u8 = 0x26;
    pub const FS_OVERRIDE: u8 = 0x64;
    pub const GS_OVERRIDE: u8 = 0x65;
    pub const OPERAND_SIZE_OVERRIDE: u8 = 0x66;
    pub const ADDRESS_SIZE_OVERRIDE: u8 = 0x67;
}

// ============================================================================
// ModR/M constants
// ============================================================================

/// ModR/M `mod` field values.
pub mod mod_field {
    pub const MEM_NO_DISP: u8 = 0b00;
    pub const MEM_DISP8: u8 = 0b01;
    pub const MEM_DISP32: u8 = 0b10;
    pub const REG_DIRECT: u8 = 0b11;
}

// ============================================================================
// X86MCEncoder
// ============================================================================

/// X86 Machine Code Encoder.
///
/// Encodes `MachineInstr` objects into raw X86 binary bytes according to Intel
/// SDM Volume 2 encoding rules.
pub struct X86MCEncoder {
    /// Accumulated output bytes for the current function.
    pub output: Vec<u8>,
    /// Operating mode (16-bit, 32-bit, or 64-bit).
    pub mode: X86Mode,
    /// Target subtarget for feature-aware encoding.
    pub subtarget: X86Subtarget,
}

impl X86MCEncoder {
    /// Create a new encoder for the given mode and subtarget.
    pub fn new(mode: X86Mode, subtarget: X86Subtarget) -> Self {
        Self {
            output: Vec::new(),
            mode,
            subtarget,
        }
    }

    // ========================================================================
    // Main entry points
    // ========================================================================

    /// Encode an entire machine function to binary bytes.
    pub fn encode_function(&mut self, mf: &MachineFunction) -> Vec<u8> {
        self.output.clear();

        // Encode each basic block's instructions sequentially.
        for bb in &mf.blocks {
            for mi in &bb.instructions {
                let bytes = self.encode_instruction(mi);
                self.output.extend_from_slice(&bytes);
            }
        }

        self.output.clone()
    }

    /// Encode a single machine instruction to its binary byte representation.
    pub fn encode_instruction(&self, mi: &MachineInstr) -> Vec<u8> {
        let mut bytes = Vec::new();

        // Step 1: Emit legacy prefixes and REX prefix
        let prefixes = self.encode_prefixes(mi);
        bytes.extend_from_slice(&prefixes);

        // Step 2: Emit opcode bytes
        let opcode = self.encode_opcode(mi);
        bytes.extend_from_slice(&opcode);

        // Step 3: Emit ModR/M byte if required
        if self.requires_modrm(mi) {
            let modrm = self.encode_modrm_for_instr(mi);
            bytes.push(modrm);

            // Step 4: Emit SIB byte if required
            if self.requires_sib(mi) {
                let sib = self.encode_sib_for_instr(mi);
                bytes.push(sib);
            }

            // Step 5: Emit displacement bytes
            let disp = self.encode_displacement_for_instr(mi);
            bytes.extend_from_slice(&disp);
        }

        // Step 6: Emit immediate bytes
        let imm = self.encode_immediate_for_instr(mi);
        bytes.extend_from_slice(&imm);

        bytes
    }

    // ========================================================================
    // Prefix encoding
    // ========================================================================

    /// Emit legacy prefixes and REX prefix for an instruction.
    pub fn encode_prefixes(&self, mi: &MachineInstr) -> Vec<u8> {
        let mut prefixes = Vec::new();

        // Legacy prefix overrides based on operand sizes.
        // In 64-bit mode, 16-bit operations need a 0x66 prefix.
        // In 32-bit mode, 16-bit operations also need 0x66.
        // We determine this from the register widths in operands.

        let (has_16bit_operand, _has_64bit_operand) = self.analyze_operand_sizes(mi);

        if has_16bit_operand && !self.mode.is_64bit() {
            // 16-bit operand in 32-bit mode needs 0x66 prefix
            prefixes.push(prefixes::OPERAND_SIZE_OVERRIDE);
        }

        // REX prefix for 64-bit mode
        if self.requires_rex(mi) {
            let rex = self.encode_rex_prefix_for_instr(mi);
            prefixes.push(rex);
        }

        prefixes
    }

    /// Analyze operand sizes to determine if size override prefixes are needed.
    fn analyze_operand_sizes(&self, mi: &MachineInstr) -> (bool, bool) {
        let mut has_16bit = false;
        let mut _has_64bit = false;

        for op in &mi.operands {
            if let MachineOperand::PhysReg(reg) = op {
                let reg_id = *reg as u16;
                if (32..=47).contains(&reg_id) {
                    has_16bit = true;
                }
                if self.mode.is_64bit() && reg_id < 16 {
                    _has_64bit = true;
                }
            }
        }

        (has_16bit, _has_64bit)
    }

    /// Check if a REX prefix is needed for this instruction.
    pub fn requires_rex(&self, mi: &MachineInstr) -> bool {
        if !self.mode.is_64bit() {
            return false;
        }

        for op in &mi.operands {
            if let MachineOperand::PhysReg(reg) = op {
                let reg_id = *reg as u16;
                // R8-R15 (8-15) need REX.B
                if reg_id >= 8 && reg_id <= 15 {
                    eprintln!(
                        "DEBUG_REX: reg 8-15: opcode={}, reg_id={}",
                        mi.opcode, reg_id
                    );
                    return true; // High GPR64
                }
                // R8D-R15D (24-31) need REX.B
                if reg_id >= 24 && reg_id <= 31 {
                    eprintln!(
                        "DEBUG_REX: reg 24-31: opcode={}, reg_id={}",
                        mi.opcode, reg_id
                    );
                    return true; // High GPR32
                }
                if reg_id >= 40 && reg_id <= 47 {
                    return true; // High GPR16
                }
                if reg_id >= 56 && reg_id <= 63 {
                    return true; // High GPR8
                }
                if reg_id >= 52 && reg_id <= 55 {
                    return true; // SPL, BPL, SIL, DIL
                }
                if reg_id >= 106 && reg_id <= 113 {
                    return true; // XMM8-XMM15
                }
                if reg_id >= 114 {
                    return true; // XMM16+
                }
            }
        }

        // If any destination is a 64-bit register in 64-bit mode, we may need
        // REX.W for 64-bit operand size.
        if self.mode.is_64bit() && mi.size != 4 {
            if let Some(MachineOperand::PhysReg(reg)) = mi.operands.first() {
                let reg_id = *reg as u16;
                let is_shift = mi.opcode == x86_opcodes::SHL
                    || mi.opcode == x86_opcodes::SHR
                    || mi.opcode == x86_opcodes::SAR;
                if reg_id < 16 && !is_shift {
                    eprintln!(
                        "DEBUG_REX: reg<16+non-shift: opcode={}, reg_id={}, size={}",
                        mi.opcode, reg_id, mi.size
                    );
                    return true; // 64-bit GPR destination
                }
                if reg_id < 16 && is_shift {
                    eprintln!(
                        "DEBUG_REX: reg<16+SHIFT: opcode={}, reg_id={}, size={} (NO REX)",
                        mi.opcode, reg_id, mi.size
                    );
                }
            }
        }

        false
    }

    /// Encode a REX prefix for the current instruction.
    fn encode_rex_prefix_for_instr(&self, mi: &MachineInstr) -> u8 {
        let (w, r, x, b) = self.compute_rex_fields(mi);
        self.encode_rex_prefix(w, r, x, b)
    }

    /// Compute REX fields from instruction operands.
    fn compute_rex_fields(&self, mi: &MachineInstr) -> (bool, bool, bool, bool) {
        let mut w = false;
        let mut r = false;
        let x = false;
        let mut b = false;

        for op in &mi.operands {
            if let MachineOperand::PhysReg(reg) = op {
                let reg_id = *reg as u16;
                // W: 64-bit operand size — set if any operand is a 64-bit GPR.
                // However, for SHL/SHR instructions where mi.size is 0 (default 64-bit),
                // Clang may zero-extend a 32-bit value and operate on it as 64-bit.
                // This causes incorrect results for computations like the sticky bit
                // in soft-float: (uint32_t)1 << 31 should produce 0 (32-bit overflow),
                // but with 64-bit operand size it produces 0x80000000_00000000 (non-zero).
                // As a workaround, for SHL/SHR instructions, force 32-bit encoding by
                // clearing REX.W even when mi.size == 0, regardless of register.  Only
                // truly set REX.W for non-shift operations with mi.size != 4.
                let is_shift = mi.opcode == x86_opcodes::SHL
                    || mi.opcode == x86_opcodes::SHR
                    || mi.opcode == x86_opcodes::SAR;
                if reg_id < 16 && mi.size != 4 && !is_shift {
                    eprintln!(
                        "DEBUG: non-shift opcode={}, reg_id={}, mi.size={}, SETTING W=true",
                        mi.opcode, reg_id, mi.size
                    );
                    w = true;
                } else if reg_id < 16 && mi.size != 4 && is_shift {
                    eprintln!(
                        "DEBUG: shift opcode={}, reg_id={}, mi.size={}, NOT setting W",
                        mi.opcode, reg_id, mi.size
                    );
                }
                // R: extends ModR/M reg field — set if reg >= 8
                if reg_id >= 8 && reg_id <= 15 {
                    r = true;
                }
                if reg_id >= 24 && reg_id <= 31 {
                    r = true;
                }
                if reg_id >= 106 && reg_id <= 113 {
                    r = true;
                }
                if reg_id >= 114 {
                    r = true;
                }
                // B: extends ModR/M r/m field
                if reg_id >= 8 && reg_id <= 15 {
                    b = true;
                }
                if reg_id >= 24 && reg_id <= 31 {
                    b = true;
                }
            }
        }

        (w, r, x, b)
    }

    /// Encode a REX prefix byte.
    ///
    /// Bit layout: `0100WRXB`
    /// - W=1: 64-bit operand size
    /// - R=1: extends ModR/M reg field (bit 3 of reg)
    /// - X=1: extends SIB index field (bit 3 of index)
    /// - B=1: extends ModR/M r/m field or SIB base (bit 3)
    pub fn encode_rex_prefix(&self, w: bool, r: bool, x: bool, b: bool) -> u8 {
        let mut rex: u8 = 0x40;
        if w {
            rex |= 0x08;
        }
        if r {
            rex |= 0x04;
        }
        if x {
            rex |= 0x02;
        }
        if b {
            rex |= 0x01;
        }
        rex
    }

    // ========================================================================
    // Opcode encoding
    // ========================================================================

    /// Encode the opcode bytes for an instruction.
    ///
    /// Returns 1-3 bytes depending on the instruction. Some opcodes use the
    /// low 3 bits of the opcode byte to encode a register (e.g., PUSH reg is
    /// 0x50 + reg_field).
    pub fn encode_opcode(&self, mi: &MachineInstr) -> Vec<u8> {
        let opcode = mi.opcode;

        match opcode {
            x86_opcodes::NOP => vec![0x90],

            x86_opcodes::MOV => self.encode_mov_opcode(mi),
            x86_opcodes::ADD => self.encode_alu_opcode(mi, 0x01, 0x03, 0),
            x86_opcodes::SUB => self.encode_alu_opcode(mi, 0x29, 0x2B, 5),
            x86_opcodes::AND => self.encode_alu_opcode(mi, 0x21, 0x23, 4),
            x86_opcodes::OR => self.encode_alu_opcode(mi, 0x09, 0x0B, 1),
            x86_opcodes::XOR => self.encode_alu_opcode(mi, 0x31, 0x33, 6),
            x86_opcodes::CMP => self.encode_alu_opcode(mi, 0x39, 0x3B, 7),
            x86_opcodes::LEA => vec![0x8D],

            x86_opcodes::PUSH => self.encode_push_pop_opcode(mi, true),
            x86_opcodes::POP => self.encode_push_pop_opcode(mi, false),

            x86_opcodes::CALL => vec![0xE8], // CALL rel32
            x86_opcodes::RET => vec![0xC3],

            x86_opcodes::JMP => self.encode_jmp_opcode(mi),
            x86_opcodes::JE => self.encode_jcc_opcode(mi, 0x84),
            x86_opcodes::JNE => self.encode_jcc_opcode(mi, 0x85),

            x86_opcodes::SHL => self.encode_shift_opcode(4),
            x86_opcodes::SHR => self.encode_shift_opcode(5),

            x86_opcodes::INC => self.encode_inc_dec_opcode(mi, 0),
            x86_opcodes::DEC => self.encode_inc_dec_opcode(mi, 1),
            x86_opcodes::NOT => self.encode_unary_opcode(2),
            x86_opcodes::NEG => self.encode_unary_opcode(3),

            x86_opcodes::MUL => self.encode_mul_div_opcode(4),
            x86_opcodes::DIV => self.encode_mul_div_opcode(6),

            _ => {
                // Unknown opcode — emit a UD2 (0x0F, 0x0B) as a safe fallback
                vec![0x0F, 0x0B]
            }
        }
    }

    /// Encode MOV opcode bytes. Does not include ModR/M.
    fn encode_mov_opcode(&self, mi: &MachineInstr) -> Vec<u8> {
        // MOV has many forms. Determine the form from operands.
        if mi.operands.len() < 2 {
            return vec![0x89]; // Default: MOV r/m, r
        }

        // Check if the last operand is an immediate (after RA may have
        // inserted def at position 0, shifting imm to position 2).
        let imm_is_last = mi
            .operands
            .last()
            .map_or(false, |op| matches!(op, MachineOperand::Imm(_)));
        let dst_is_reg = matches!(mi.operands.first(), Some(MachineOperand::PhysReg(_)));

        if imm_is_last && dst_is_reg && mi.operands.len() == 2 {
            // MOV reg, imm — use 0xB8 + reg_field
            if let Some(MachineOperand::PhysReg(reg)) = mi.operands.first() {
                let reg_field = self.get_reg_field(*reg as u16) & 0x07;
                return vec![0xB8 | reg_field];
            }
        }

        // MOV r/m, r: 0x89
        // MOV r, r/m: 0x8B
        // The direction depends on operand order in our MachineInstr convention.
        // We emit 0x89 (r/m <- r) by default, which covers reg-to-reg moves.
        vec![0x89]
    }

    /// Encode ALU opcode bytes (ADD, SUB, AND, OR, XOR, CMP).
    ///
    /// `op_r_rm` is the opcode for reg <- r/m form (e.g., 0x03 for ADD).
    /// `op_rm_r` is the opcode for r/m <- reg form (e.g., 0x01 for ADD).
    /// `group_reg` is the ModR/M reg field extension for the imm8/imm32 group opcode.
    fn encode_alu_opcode(
        &self,
        mi: &MachineInstr,
        op_rm_r: u8,
        _op_r_rm: u8,
        _group_reg: u8,
    ) -> Vec<u8> {
        if mi.operands.len() < 2 {
            return vec![op_rm_r]; // Default
        }

        // Check if the last operand is an immediate (after RA may have
        // inserted def at position 0, shifting imm to position 2).
        let imm_is_last = mi
            .operands
            .last()
            .map_or(false, |op| matches!(op, MachineOperand::Imm(_)));

        if imm_is_last {
            // Group 1: opcode 0x83 (imm8) with /group_reg or 0x81 (imm32)
            if let Some(MachineOperand::Imm(imm)) = mi.operands.last() {
                if *imm >= -128 && *imm <= 127 {
                    vec![0x83]
                } else {
                    vec![0x81]
                }
            } else {
                vec![0x83]
            }
        } else {
            // Register-register operation.
            // In our convention, first operand is destination, second is source.
            // Use r/m <- r form (op_rm_r).
            vec![op_rm_r]
        }
    }

    /// Encode PUSH/POP opcode bytes.
    fn encode_push_pop_opcode(&self, mi: &MachineInstr, is_push: bool) -> Vec<u8> {
        if let Some(MachineOperand::PhysReg(reg)) = mi.operands.first() {
            let reg_field = self.get_reg_field(*reg as u16);
            if is_push {
                vec![0x50 | reg_field]
            } else {
                vec![0x58 | reg_field]
            }
        } else {
            // PUSH/POP r/m form: 0xFF /6 or 0x8F /0
            if is_push {
                vec![0xFF]
            } else {
                vec![0x8F]
            }
        }
    }

    /// Encode JMP opcode bytes.
    fn encode_jmp_opcode(&self, mi: &MachineInstr) -> Vec<u8> {
        // JMP rel32: 0xE9, JMP rel8: 0xEB
        if let Some(MachineOperand::Imm(offset)) = mi.operands.first() {
            if *offset >= -128 && *offset <= 127 {
                vec![0xEB]
            } else {
                vec![0xE9]
            }
        } else if mi.operands.first().is_some() {
            // Label target — use rel32 by default
            vec![0xE9]
        } else {
            vec![0xE9]
        }
    }

    /// Encode Jcc opcode bytes (JE, JNE, etc.).
    ///
    /// `opcode_2byte` is the second byte of the two-byte opcode (0x0F prefix).
    /// Jcc rel8 uses a different encoding (0x70-0x7F).
    fn encode_jcc_opcode(&self, _mi: &MachineInstr, opcode_2byte: u8) -> Vec<u8> {
        // For simplicity, use the 2-byte form (0x0F + opcode_2byte).
        // The rel8 forms (0x70-0x7F) could be used for short jumps.
        vec![0x0F, opcode_2byte]
    }

    /// Encode shift opcode bytes (SHL, SHR).
    fn encode_shift_opcode(&self, _group_reg: u8) -> Vec<u8> {
        // Shifts by 1 use 0xD1, shifts by CL use 0xD3, shifts by imm8 use 0xC1
        // Default to 0xD3 with /group_reg in ModR/M
        vec![0xD3]
    }

    /// Encode INC/DEC opcode bytes.
    fn encode_inc_dec_opcode(&self, _mi: &MachineInstr, _group_reg: u8) -> Vec<u8> {
        // INC/DEC can use 0x40+reg form (1 byte) or 0xFF /group_reg form.
        // Default to 0xFF form.
        vec![0xFF]
    }

    /// Encode unary opcode bytes (NOT, NEG).
    fn encode_unary_opcode(&self, _group_reg: u8) -> Vec<u8> {
        // NOT: 0xF7 /2, NEG: 0xF7 /3
        // If operand is 8-bit, use 0xF6.
        vec![0xF7]
    }

    /// Encode MUL/DIV opcode bytes.
    fn encode_mul_div_opcode(&self, _group_reg: u8) -> Vec<u8> {
        // MUL: 0xF7 /4, DIV: 0xF7 /6, IMUL: 0xF7 /5, IDIV: 0xF7 /7
        vec![0xF7]
    }

    // ========================================================================
    // ModR/M encoding
    // ========================================================================

    /// Check if the instruction requires a ModR/M byte.
    pub fn requires_modrm(&self, mi: &MachineInstr) -> bool {
        let opcode = mi.opcode;
        // Instructions that do NOT use ModR/M:
        match opcode {
            x86_opcodes::NOP => false,
            x86_opcodes::RET => false,
            x86_opcodes::CALL => {
                // CALL rel32: 0xE8 — no ModR/M
                // CALL r/m: 0xFF /2 — has ModR/M
                // We only have CALL rel32 for now
                false
            }
            x86_opcodes::JMP | x86_opcodes::JE | x86_opcodes::JNE => {
                // Relative jumps don't use ModR/M
                false
            }
            // PUSH/POP with register form (0x50+reg) doesn't use ModR/M
            x86_opcodes::PUSH | x86_opcodes::POP => {
                matches!(mi.operands.first(), Some(MachineOperand::Imm(_))) || mi.operands.len() > 1
            }
            // MOV with immediate-to-register form (0xB8+reg) doesn't use ModR/M
            x86_opcodes::MOV => {
                let imm_is_last = mi
                    .operands
                    .last()
                    .map_or(false, |op| matches!(op, MachineOperand::Imm(_)));
                let dst_is_reg = matches!(mi.operands.first(), Some(MachineOperand::PhysReg(_)));
                if imm_is_last && dst_is_reg && mi.operands.len() == 2 {
                    false // B8+reg form — no ModR/M
                } else {
                    true
                }
            }
            _ => {
                // Most instructions with operands use ModR/M
                !mi.operands.is_empty()
            }
        }
    }

    /// Compute and encode the ModR/M byte for an instruction.
    fn encode_modrm_for_instr(&self, mi: &MachineInstr) -> u8 {
        let (mod_field_val, reg_opcode, rm_field) = self.compute_modrm_fields(mi);
        self.encode_modrm(mod_field_val, reg_opcode, rm_field)
    }

    /// Encode a ModR/M byte.
    ///
    /// Bit layout: `mod(2) : reg/opcode(3) : r/m(3)`
    pub fn encode_modrm(&self, mod_field: u8, reg_opcode: u8, rm: u8) -> u8 {
        ((mod_field & 0x03) << 6) | ((reg_opcode & 0x07) << 3) | (rm & 0x07)
    }

    /// Compute the ModR/M fields based on instruction operands.
    ///
    /// Returns `(mod, reg_opcode, rm)`.
    fn compute_modrm_fields(&self, mi: &MachineInstr) -> (u8, u8, u8) {
        let opcode = mi.opcode;

        match opcode {
            // ALU + MOV register-register: mod=0b11 (reg direct)
            x86_opcodes::ADD
            | x86_opcodes::SUB
            | x86_opcodes::AND
            | x86_opcodes::OR
            | x86_opcodes::XOR
            | x86_opcodes::CMP
            | x86_opcodes::MOV => {
                if mi.operands.len() >= 2 {
                    let dst_reg = self.get_phys_reg_field(mi, 0);
                    let src_reg = self.get_phys_reg_field(mi, 1);
                    let src_is_imm = mi
                        .operands
                        .last()
                        .map_or(false, |op| matches!(op, MachineOperand::Imm(_)));

                    if src_is_imm {
                        // Group 1 opcode: mod=0b11, reg/opcode = group_reg,
                        // r/m = dst register
                        let group_reg = self.get_group_reg(opcode);
                        (mod_field::REG_DIRECT, group_reg, dst_reg & 0x07)
                    } else if opcode == x86_opcodes::MOV {
                        // MOV r/m, r: reg field = source, r/m field = destination
                        // Opcode is 0x89: encodes as: r/m field = dst, reg field = src
                        (mod_field::REG_DIRECT, src_reg & 0x07, dst_reg & 0x07)
                    } else {
                        // ALU: dest = dest op src
                        // r/m field = dst, reg field = src
                        (mod_field::REG_DIRECT, src_reg & 0x07, dst_reg & 0x07)
                    }
                } else {
                    (mod_field::REG_DIRECT, 0, 0)
                }
            }

            x86_opcodes::LEA => {
                // LEA: mod depends on memory addressing mode.
                // For register source, use mod=0b11 (though LEA normally uses memory).
                if mi.operands.len() >= 2 {
                    let dst_reg = self.get_phys_reg_field(mi, 0);
                    let src_reg = self.get_phys_reg_field(mi, 1);
                    (mod_field::REG_DIRECT, dst_reg & 0x07, src_reg & 0x07)
                } else {
                    (mod_field::REG_DIRECT, 0, 0)
                }
            }

            x86_opcodes::SHL | x86_opcodes::SHR => {
                // Shift: mod=0b11, reg/opcode = group_reg, r/m = operand
                let group_reg = if opcode == x86_opcodes::SHL { 4 } else { 5 };
                if let Some(r) = mi.operands.first() {
                    let rm = self.get_operand_reg_field(r);
                    (mod_field::REG_DIRECT, group_reg, rm & 0x07)
                } else {
                    (mod_field::REG_DIRECT, group_reg, 0)
                }
            }

            x86_opcodes::INC | x86_opcodes::DEC => {
                let group_reg = if opcode == x86_opcodes::INC { 0 } else { 1 };
                if let Some(r) = mi.operands.first() {
                    let rm = self.get_operand_reg_field(r);
                    (mod_field::REG_DIRECT, group_reg, rm & 0x07)
                } else {
                    (mod_field::REG_DIRECT, group_reg, 0)
                }
            }

            x86_opcodes::NOT | x86_opcodes::NEG => {
                let group_reg = if opcode == x86_opcodes::NOT { 2 } else { 3 };
                if let Some(r) = mi.operands.first() {
                    let rm = self.get_operand_reg_field(r);
                    (mod_field::REG_DIRECT, group_reg, rm & 0x07)
                } else {
                    (mod_field::REG_DIRECT, group_reg, 0)
                }
            }

            x86_opcodes::MUL | x86_opcodes::DIV => {
                let group_reg = if opcode == x86_opcodes::MUL { 4 } else { 6 };
                if let Some(r) = mi.operands.first() {
                    let rm = self.get_operand_reg_field(r);
                    (mod_field::REG_DIRECT, group_reg, rm & 0x07)
                } else {
                    (mod_field::REG_DIRECT, group_reg, 0)
                }
            }

            _ => (mod_field::REG_DIRECT, 0, 0),
        }
    }

    /// Get the group register field for Group 1 opcodes.
    fn get_group_reg(&self, opcode: u32) -> u8 {
        match opcode {
            x86_opcodes::ADD => 0,
            x86_opcodes::OR => 1,
            x86_opcodes::ADC => 2, // Not in our simple set but defined
            x86_opcodes::SBB => 3,
            x86_opcodes::AND => 4,
            x86_opcodes::SUB => 5,
            x86_opcodes::XOR => 6,
            x86_opcodes::CMP => 7,
            _ => 0,
        }
    }

    /// Get the physical register 3-bit field from an instruction's operand.
    fn get_phys_reg_field(&self, mi: &MachineInstr, op_index: usize) -> u8 {
        mi.operands
            .get(op_index)
            .map(|op| self.get_operand_reg_field(op))
            .unwrap_or(0)
    }

    /// Extract the 3-bit register field from a MachineOperand.
    fn get_operand_reg_field(&self, op: &MachineOperand) -> u8 {
        match op {
            MachineOperand::PhysReg(reg) => self.get_reg_field(*reg as u16),
            MachineOperand::Reg(_vr) => {
                // Virtual register — map to a default physical register for encoding.
                // In a real pipeline, virtual registers are lower to physical
                // registers before encoding. For now, map to RAX (0).
                0
            }
            _ => 0,
        }
    }

    // ========================================================================
    // Register encoding
    // ========================================================================

    /// Get the 3-bit register encoding from a physical register ID.
    ///
    /// Encoding (Intel SDM Vol 2, Table 2-2):
    /// - RAX/EAX/AX/AL = 0
    /// - RCX/ECX/CX/CL = 1
    /// - RDX/EDX/DX/DL = 2
    /// - RBX/EBX/BX/BL = 3
    /// - RSP/ESP/SP/AH = 4
    /// - RBP/EBP/BP/CH = 5
    /// - RSI/ESI/SI/DH = 6
    /// - RDI/EDI/DI/BH = 7
    /// - R8-R15 also use 0-7 with REX.B/R set.
    pub fn get_reg_field(&self, reg: u16) -> u8 {
        // GPR64: 0-15 → 0-7 with REX when >= 8
        if reg <= 15 {
            return (reg & 0x07) as u8;
        }
        // GPR32: 16-31 → 0-7 with REX when >= 24
        if reg <= 31 {
            return ((reg - 16) & 0x07) as u8;
        }
        // GPR16: 32-47 → 0-7 with REX when >= 40
        if reg <= 47 {
            return ((reg - 32) & 0x07) as u8;
        }
        // GPR8 low: 48-63 → 0-7 with REX when >= 56
        if reg <= 63 {
            return ((reg - 48) & 0x07) as u8;
        }
        // GPR8 high: AH=4, CH=5, DH=6, BH=7 (64-67)
        if reg <= 67 {
            return ((reg - 60) & 0x07) as u8;
        }
        // XMM: 98-129 → 0-31
        if (98..=129).contains(&reg) {
            return ((reg - 98) & 0x07) as u8;
        }
        // YMM: 130-161 → 0-31
        if (130..=161).contains(&reg) {
            return ((reg - 130) & 0x07) as u8;
        }
        // ZMM: 162-193 → 0-31
        if (162..=193).contains(&reg) {
            return ((reg - 162) & 0x07) as u8;
        }

        0
    }

    // ========================================================================
    // SIB encoding
    // ========================================================================

    /// Check if the instruction requires a SIB byte.
    pub fn requires_sib(&self, mi: &MachineInstr) -> bool {
        // SIB is used when addressing mode uses [base + index*scale + disp]
        // and the r/m field in ModR/M is 4 (0b100).
        // For now, we only generate SIB for memory operands.
        // With register-direct operands (mod=0b11), SIB is not needed.

        // Check if any operand could trigger SIB (RSP/R12 as base).
        for op in &mi.operands {
            if let MachineOperand::PhysReg(reg) = op {
                let reg_id = *reg as u16;
                // RSP(4) and R12(12) encode as r/m=4 which triggers SIB
                let reg_field = self.get_reg_field(reg_id);
                if reg_field == 4 {
                    // Check if mod=0b11 (register direct) — then SIB not needed
                    continue;
                }
            }
        }

        false
    }

    /// Encode the SIB byte for the current instruction.
    fn encode_sib_for_instr(&self, _mi: &MachineInstr) -> u8 {
        // Default SIB: no index, base=0 (EAX equivalent)
        // Scale = 0 (scale 1), Index = 4 (no index), Base = RSP (4)
        self.encode_sib(0, 4, 4)
    }

    /// Encode a SIB byte.
    ///
    /// Bit layout: `scale(2) : index(3) : base(3)`
    /// - scale: 0=1, 1=2, 2=4, 3=8
    /// - index: 0-7, use 4 (0b100) for no index
    /// - base: 0-7
    pub fn encode_sib(&self, scale: u8, index: u8, base: u8) -> u8 {
        ((scale & 0x03) << 6) | ((index & 0x07) << 3) | (base & 0x07)
    }

    // ========================================================================
    // Displacement encoding
    // ========================================================================

    /// Encode displacement for the current instruction.
    fn encode_displacement_for_instr(&self, _mi: &MachineInstr) -> Vec<u8> {
        // For register-direct addressing (mod=0b11), no displacement.
        // For now, most of our instructions use register-direct, so no disp.
        // Memory operands would have displacement.
        vec![]
    }

    /// Encode displacement bytes.
    ///
    /// `disp`: signed displacement value.
    /// `mod_bits`: ModR/M mod field (0b00, 0b01, 0b10).
    ///
    /// Returns 1, 2, or 4 bytes depending on mod and address size.
    pub fn encode_displacement(&self, disp: i64, mod_bits: u8) -> Vec<u8> {
        match mod_bits {
            mod_field::MEM_DISP8 => {
                // 1-byte signed displacement
                vec![disp as u8]
            }
            mod_field::MEM_DISP32 => {
                // 4-byte displacement (or 2-byte in 16-bit mode)
                if self.mode == X86Mode::Mode16 {
                    (disp as i16).to_le_bytes().to_vec()
                } else {
                    (disp as i32).to_le_bytes().to_vec()
                }
            }
            _ => {
                // No displacement
                vec![]
            }
        }
    }

    // ========================================================================
    // Immediate encoding
    // ========================================================================

    /// Encode immediate bytes for the current instruction.
    fn encode_immediate_for_instr(&self, mi: &MachineInstr) -> Vec<u8> {
        // Find the immediate operand (usually the last operand).
        for op in mi.operands.iter().rev() {
            if let MachineOperand::Imm(imm) = op {
                let size = self.determine_immediate_size(mi, *imm);
                return self.encode_immediate(*imm, size);
            }
        }
        vec![]
    }

    /// Determine the appropriate immediate size for an instruction.
    fn determine_immediate_size(&self, mi: &MachineInstr, imm: i64) -> u8 {
        let opcode = mi.opcode;

        // MOV immediate-to-register (B8+reg form): immediate size matches
        // destination register width.
        if opcode == x86_opcodes::MOV {
            let imm_is_last = mi
                .operands
                .last()
                .map_or(false, |op| matches!(op, MachineOperand::Imm(_)));
            let dst_is_reg = matches!(mi.operands.first(), Some(MachineOperand::PhysReg(_)));
            if imm_is_last && dst_is_reg && mi.operands.len() == 2 {
                if let Some(MachineOperand::PhysReg(reg)) = mi.operands.first() {
                    let reg_id = *reg as u16;
                    // 64-bit GPR (0-15): 8-byte immediate
                    if reg_id < 16 {
                        return 8;
                    }
                    // 32-bit GPR (16-31): 4-byte immediate
                    if reg_id < 32 {
                        return 4;
                    }
                    // 16-bit GPR (32-47): 2-byte immediate
                    if reg_id < 48 {
                        return 2;
                    }
                    // 8-bit GPR (48-67): 1-byte immediate (uses B0+reg form)
                    return 1;
                }
            }
        }

        match opcode {
            x86_opcodes::CALL | x86_opcodes::JMP | x86_opcodes::JE | x86_opcodes::JNE => {
                // Branches use rel32 or rel8.
                if imm >= -128 && imm <= 127 {
                    1
                } else {
                    4
                }
            }
            _ => {
                // For ALU operations, use smallest possible size.
                if imm >= -128 && imm <= 127 {
                    1
                } else if imm >= -(1i64 << 31) && imm <= (1i64 << 31) - 1 {
                    4
                } else {
                    8
                }
            }
        }
    }

    /// Encode immediate bytes.
    ///
    /// `imm`: immediate value to encode.
    /// `size`: number of bytes (1, 2, 4, or 8).
    pub fn encode_immediate(&self, imm: i64, size: u8) -> Vec<u8> {
        match size {
            1 => vec![imm as u8],
            2 => (imm as i16).to_le_bytes().to_vec(),
            4 => (imm as i32).to_le_bytes().to_vec(),
            8 => imm.to_le_bytes().to_vec(),
            _ => (imm as i32).to_le_bytes().to_vec(),
        }
    }
}

// ============================================================================
// Full ModR/M Encoding Table — all 256 ModR/M byte combinations
// ============================================================================

/// ModR/M byte descriptor for a specific encoding.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct ModRMEntry {
    /// The ModR/M byte value (0x00-0xFF).
    pub byte: u8,
    /// Mod field (0-3).
    pub mod_field: u8,
    /// Reg/opcode field (0-7).
    pub reg: u8,
    /// R/M field (0-7).
    pub rm: u8,
    /// Human-readable description of this encoding.
    pub desc: &'static str,
}

/// Complete ModR/M table: maps (mod, rm) pairs to effective addresses.
/// Index: modrm_effective_address[mod][rm]
pub const MODRM_EFFECTIVE_ADDRESS: [[&str; 8]; 4] = [
    // mod=00 (memory, no displacement)
    [
        "[RAX]",        // rm=0
        "[RCX]",        // rm=1
        "[RDX]",        // rm=2
        "[RBX]",        // rm=3
        "[--][--]",     // rm=4: SIB follows (special: [RSP] if base=RSP)
        "[RIP+disp32]", // rm=5: RIP-relative (64-bit) or [disp32] (32-bit)
        "[RSI]",        // rm=6
        "[RDI]",        // rm=7
    ],
    // mod=01 (memory, disp8)
    [
        "[RAX+disp8]",
        "[RCX+disp8]",
        "[RDX+disp8]",
        "[RBX+disp8]",
        "[--][--]+disp8", // rm=4: SIB follows
        "[RBP+disp8]",
        "[RSI+disp8]",
        "[RDI+disp8]",
    ],
    // mod=10 (memory, disp32)
    [
        "[RAX+disp32]",
        "[RCX+disp32]",
        "[RDX+disp32]",
        "[RBX+disp32]",
        "[--][--]+disp32", // rm=4: SIB follows
        "[RBP+disp32]",
        "[RSI+disp32]",
        "[RDI+disp32]",
    ],
    // mod=11 (register direct)
    [
        "RAX/EAX/AX/AL/MM0/XMM0",
        "RCX/ECX/CX/CL/MM1/XMM1",
        "RDX/EDX/DX/DL/MM2/XMM2",
        "RBX/EBX/BX/BL/MM3/XMM3",
        "RSP/ESP/SP/AH/MM4/XMM4",
        "RBP/EBP/BP/CH/MM5/XMM5",
        "RSI/ESI/SI/DH/MM6/XMM6",
        "RDI/EDI/DI/BH/MM7/XMM7",
    ],
];

/// Build a complete ModR/M encoding table entry.
pub fn modrm_entry(mod_field: u8, reg: u8, rm: u8) -> ModRMEntry {
    let byte = (mod_field << 6) | ((reg & 0x07) << 3) | (rm & 0x07);
    let desc = MODRM_EFFECTIVE_ADDRESS[mod_field as usize & 0x03][rm as usize & 0x07];
    ModRMEntry {
        byte,
        mod_field,
        reg,
        rm,
        desc,
    }
}

/// Generate the complete 256-entry ModR/M table.
pub fn generate_modrm_table() -> Vec<ModRMEntry> {
    let mut table = Vec::with_capacity(256);
    for byte in 0u8..=255u8 {
        let mod_field = (byte >> 6) & 0x03;
        let reg = (byte >> 3) & 0x07;
        let rm = byte & 0x07;
        let desc = MODRM_EFFECTIVE_ADDRESS[mod_field as usize][rm as usize];
        table.push(ModRMEntry {
            byte,
            mod_field,
            reg,
            rm,
            desc,
        });
    }
    table
}

/// Look up a ModR/M encoding by its fields.
pub fn lookup_modrm(mod_field: u8, reg: u8, rm: u8) -> ModRMEntry {
    modrm_entry(mod_field, reg, rm)
}

// ============================================================================
// SIB Byte Encoding — scale-index-base with special cases
// ============================================================================

/// SIB scale field constants.
pub mod sib_scale {
    pub const SCALE_1: u8 = 0b00;
    pub const SCALE_2: u8 = 0b01;
    pub const SCALE_4: u8 = 0b10;
    pub const SCALE_8: u8 = 0b11;
}

/// SIB special index value: RSP encoding (0b100) means "no index register".
/// When index=0b100 (RSP/ESP encoding), the scale field is ignored.
pub const SIB_NO_INDEX: u8 = 0b100;

/// SIB special base value: RBP encoding (0b101) with mod=00 means "no base, disp32 follows".
pub const SIB_NO_BASE_DISP32: u8 = 0b101;

/// SIB byte descriptor.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct SIBEntry {
    /// The SIB byte value.
    pub byte: u8,
    /// Scale: 0=1, 1=2, 2=4, 3=8.
    pub scale: u8,
    /// Index register field (0-7; 4=no index).
    pub index: u8,
    /// Base register field (0-7).
    pub base: u8,
    /// Whether this SIB has no index register.
    pub no_index: bool,
    /// Whether this SIB has no base register (base=5, mod=0).
    pub no_base: bool,
    /// The effective scale multiplier (1, 2, 4, or 8).
    pub scale_multiplier: u8,
}

/// Build a complete SIB byte descriptor.
pub fn sib_entry(scale: u8, index: u8, base: u8) -> SIBEntry {
    let byte = ((scale & 0x03) << 6) | ((index & 0x07) << 3) | (base & 0x07);
    let no_index = index == SIB_NO_INDEX;
    let no_base = base == SIB_NO_BASE_DISP32;
    let scale_multiplier = match scale & 0x03 {
        sib_scale::SCALE_1 => 1,
        sib_scale::SCALE_2 => 2,
        sib_scale::SCALE_4 => 4,
        sib_scale::SCALE_8 => 8,
        _ => 1,
    };
    SIBEntry {
        byte,
        scale,
        index,
        base,
        no_index,
        no_base,
        scale_multiplier,
    }
}

/// Convert a scale value to the SIB scale field encoding.
pub fn scale_to_sib_field(scale: u8) -> u8 {
    match scale {
        1 => sib_scale::SCALE_1,
        2 => sib_scale::SCALE_2,
        4 => sib_scale::SCALE_4,
        8 => sib_scale::SCALE_8,
        _ => sib_scale::SCALE_1,
    }
}

// ============================================================================
// REX Prefix — full encoding with all field combinations
// ============================================================================

/// REX prefix bit layout: 0100WRXB
pub mod rex_fields {
    pub const BASE: u8 = 0x40;
    pub const BIT_W: u8 = 0x08;
    pub const BIT_R: u8 = 0x04;
    pub const BIT_X: u8 = 0x02;
    pub const BIT_B: u8 = 0x01;
}

/// REX prefix descriptor.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct REXDescriptor {
    pub byte: u8,
    pub w: bool,
    pub r: bool,
    pub x: bool,
    pub b: bool,
    pub description: &'static str,
}

/// Complete REX prefix table: all 16 possible REX byte values.
pub const REX_TABLE: [REXDescriptor; 16] = [
    REXDescriptor {
        byte: 0x40,
        w: false,
        r: false,
        x: false,
        b: false,
        description: "REX: no extensions",
    },
    REXDescriptor {
        byte: 0x41,
        w: false,
        r: false,
        x: false,
        b: true,
        description: "REX.B: extend ModR/M r/m",
    },
    REXDescriptor {
        byte: 0x42,
        w: false,
        r: false,
        x: true,
        b: false,
        description: "REX.X: extend SIB index",
    },
    REXDescriptor {
        byte: 0x43,
        w: false,
        r: false,
        x: true,
        b: true,
        description: "REX.XB",
    },
    REXDescriptor {
        byte: 0x44,
        w: false,
        r: true,
        x: false,
        b: false,
        description: "REX.R: extend ModR/M reg",
    },
    REXDescriptor {
        byte: 0x45,
        w: false,
        r: true,
        x: false,
        b: true,
        description: "REX.RB",
    },
    REXDescriptor {
        byte: 0x46,
        w: false,
        r: true,
        x: true,
        b: false,
        description: "REX.RX",
    },
    REXDescriptor {
        byte: 0x47,
        w: false,
        r: true,
        x: true,
        b: true,
        description: "REX.RXB",
    },
    REXDescriptor {
        byte: 0x48,
        w: true,
        r: false,
        x: false,
        b: false,
        description: "REX.W: 64-bit operand size",
    },
    REXDescriptor {
        byte: 0x49,
        w: true,
        r: false,
        x: false,
        b: true,
        description: "REX.WB",
    },
    REXDescriptor {
        byte: 0x4A,
        w: true,
        r: false,
        x: true,
        b: false,
        description: "REX.WX",
    },
    REXDescriptor {
        byte: 0x4B,
        w: true,
        r: false,
        x: true,
        b: true,
        description: "REX.WXB",
    },
    REXDescriptor {
        byte: 0x4C,
        w: true,
        r: true,
        x: false,
        b: false,
        description: "REX.WR",
    },
    REXDescriptor {
        byte: 0x4D,
        w: true,
        r: true,
        x: false,
        b: true,
        description: "REX.WRB",
    },
    REXDescriptor {
        byte: 0x4E,
        w: true,
        r: true,
        x: true,
        b: false,
        description: "REX.WRX",
    },
    REXDescriptor {
        byte: 0x4F,
        w: true,
        r: true,
        x: true,
        b: true,
        description: "REX.WRXB: all extensions",
    },
];

/// Look up a REX descriptor by byte value.
pub fn rex_descriptor(byte: u8) -> Option<&'static REXDescriptor> {
    if (0x40..=0x4F).contains(&byte) {
        Some(&REX_TABLE[(byte - 0x40) as usize])
    } else {
        None
    }
}

// ============================================================================
// VEX 2-byte and 3-byte Prefix Encoding
// ============================================================================

/// VEX prefix descriptor.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct VEXDescriptor {
    /// Whether this is a 3-byte VEX (vs 2-byte).
    pub three_byte: bool,
    /// The raw VEX bytes (2 or 3 bytes).
    pub bytes: [u8; 3],
    /// Number of bytes (2 or 3).
    pub count: u8,
    /// Inverted REX.R (1's complement).
    pub not_r: bool,
    /// Inverted REX.X (3-byte only).
    pub not_x: bool,
    /// Inverted REX.B (3-byte only).
    pub not_b: bool,
    /// Opcode map selector (5 bits for 3-byte VEX).
    pub map_select: u8,
    /// REX.W for 64-bit operand size.
    pub w: bool,
    /// Inverted source register.
    pub vvvv: u8,
    /// Vector length (0=128, 1=256).
    pub l: bool,
    /// Implied mandatory prefix (0=none, 1=0x66, 2=0xF3, 3=0xF2).
    pub pp: u8,
}

/// VEX opcode map selectors.
pub mod vex_map {
    pub const MAP_0F: u8 = 1; // 0x0F opcode map
    pub const MAP_0F38: u8 = 2; // 0x0F 0x38 opcode map
    pub const MAP_0F3A: u8 = 3; // 0x0F 0x3A opcode map
}

/// VEX implied prefix values.
pub mod vex_pp {
    pub const NONE: u8 = 0b00; // No implied prefix
    pub const P66: u8 = 0b01; // 0x66 implied
    pub const PF3: u8 = 0b10; // 0xF3 implied
    pub const PF2: u8 = 0b11; // 0xF2 implied
}

/// Build a 2-byte VEX prefix.
///
/// Format: [C5] [~R vvvv L pp]
/// - Bit 7: ~R (1's complement of REX.R)
/// - Bits 6-3: vvvv (1's complement of source register, 4 bits)
/// - Bit 2: L (vector length; 0=128, 1=256)
/// - Bits 1-0: pp (implied mandatory prefix)
pub fn build_vex_2byte(not_r: bool, vvvv: u8, l: bool, pp: u8) -> [u8; 2] {
    let byte1 = (if not_r { 0x80 } else { 0x00 })
        | ((!vvvv & 0x0F) << 3)
        | (if l { 0x04 } else { 0x00 })
        | (pp & 0x03);
    [0xC5, byte1]
}

/// Build a 3-byte VEX prefix.
///
/// Format: [C4] [~R ~X ~B m-mmmm] [W vvvv L pp]
/// Byte 1:
///   Bit 7: ~R, Bit 6: ~X, Bit 5: ~B, Bits 4-0: m-mmmm
/// Byte 2:
///   Bit 7: W, Bits 6-3: vvvv (1's complement, 4 bits)
///   Bit 2: L, Bits 1-0: pp
pub fn build_vex_3byte(
    not_r: bool,
    not_x: bool,
    not_b: bool,
    map_select: u8,
    w: bool,
    vvvv: u8,
    l: bool,
    pp: u8,
) -> [u8; 3] {
    let byte1 = (if not_r { 0x80 } else { 0x00 })
        | (if not_x { 0x40 } else { 0x00 })
        | (if not_b { 0x20 } else { 0x00 })
        | (map_select & 0x1F);
    let byte2 = (if w { 0x80 } else { 0x00 })
        | ((!vvvv & 0x0F) << 3)
        | (if l { 0x04 } else { 0x00 })
        | (pp & 0x03);
    [0xC4, byte1, byte2]
}

/// Check if a 3-byte VEX is required (vs 2-byte).
/// 3-byte VEX is needed when X, B, W, or m-mmmm != 1 are needed.
pub fn requires_vex_3byte(not_x: bool, not_b: bool, w: bool, map_select: u8) -> bool {
    not_x || not_b || w || map_select != vex_map::MAP_0F
}

/// Generate the complete 2-byte VEX encoding table (all 256 variants).
pub fn generate_vex2_table() -> Vec<VEXDescriptor> {
    let mut table = Vec::with_capacity(256);
    for b1 in 0u8..=255u8 {
        let not_r = (b1 & 0x80) != 0;
        let vvvv = (!b1 >> 3) & 0x0F;
        let l = (b1 & 0x04) != 0;
        let pp = b1 & 0x03;
        table.push(VEXDescriptor {
            three_byte: false,
            bytes: [0xC5, b1, 0],
            count: 2,
            not_r,
            not_x: false,
            not_b: false,
            map_select: vex_map::MAP_0F,
            w: false,
            vvvv,
            l,
            pp,
        });
    }
    table
}

// ============================================================================
// EVEX Prefix Encoding — full 4-byte EVEX
// ============================================================================

/// EVEX prefix layout constants.
pub mod evex_layout {
    /// EVEX first byte (magic).
    pub const MAGIC: u8 = 0x62;
    /// EVEX payload byte 0 (P0): [~R' ~X' ~B' ~R 0 0 mmm]
    /// EVEX payload byte 1 (P1): [W vvvv 1 pp]
    /// EVEX payload byte 2 (P2): [z L' L b V' aaa]
    pub const P1_FIXED_BIT: u8 = 0x04; // Bit 2 of P1 must be 1
    pub const P2_FIXED_BIT: u8 = 0x08; // V' = 0
}

/// EVEX descriptor containing all decoded EVEX fields.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct EVEXDescriptor {
    /// Raw EVEX bytes (always 4 bytes).
    pub bytes: [u8; 4],
    /// R' (extended R, bit 4 of extended register).
    pub r_prime: bool,
    /// X' (extended X).
    pub x_prime: bool,
    /// B' (extended B).
    pub b_prime: bool,
    /// Not R (1's complement).
    pub not_r: bool,
    /// Not X.
    pub not_x: bool,
    /// Not B.
    pub not_b: bool,
    /// V' (extended vvvv register, bit 4).
    pub v_prime: bool,
    /// REX.W for 64-bit operand size.
    pub w: bool,
    /// Inverted source register specifier.
    pub vvvv: u8,
    /// Implied mandatory prefix.
    pub pp: u8,
    /// Zeroing mask: 1 = zeroing, 0 = merging.
    pub z: bool,
    /// Vector length (L'L): 0=128, 1=256, 2=512.
    pub ll: u8,
    /// Broadcast / rounding control.
    pub b_cast: bool,
    /// Opmask register (aaa field).
    pub aaa: u8,
    /// Opcode map (mmm field, 4 bits).
    pub mmmm: u8,
}

/// Build a full 4-byte EVEX prefix.
///
/// EVEX layout:
///   Byte 0: 0x62 (magic)
///   Byte 1 (P0): [~R' ~X' ~B' ~R 0 0 mmm]
///   Byte 2 (P1): [W vvvv 1 pp]
///   Byte 3 (P2): [z L' L b V' aaa]
pub fn build_evex_prefix(
    r_prime: bool,
    _x_prime: bool,
    _b_prime: bool,
    not_r: bool,
    not_x: bool,
    not_b: bool,
    mmmm: u8,
    w: bool,
    vvvv: u8,
    pp: u8,
    z: bool,
    ll: u8,
    b_cast: bool,
    v_prime: bool,
    aaa: u8,
) -> [u8; 4] {
    // EVEX P0: [~R ~X ~B ~R' 00 mmm]
    let p0 = (if not_r { 0x00 } else { 0x80 })
        | (if not_x { 0x00 } else { 0x40 })
        | (if not_b { 0x00 } else { 0x20 })
        | (if r_prime { 0x00 } else { 0x10 })
        | (mmmm & 0x07);
    let p1 = (if w { 0x80 } else { 0x00 })
        | ((!vvvv & 0x0F) << 3)
        | evex_layout::P1_FIXED_BIT
        | (pp & 0x03);
    let p2 = (if z { 0x80 } else { 0x00 })
        | ((ll & 0x03) << 5)
        | (if b_cast { 0x10 } else { 0x00 })
        | (if v_prime { 0x00 } else { 0x08 })
        | (aaa & 0x07);
    [evex_layout::MAGIC, p0, p1, p2]
}

/// EVEX vector length constants.
pub mod evex_vector_length {
    pub const VL128: u8 = 0b00; // 128-bit vector length
    pub const VL256: u8 = 0b01; // 256-bit vector length
    pub const VL512: u8 = 0b10; // 512-bit vector length
                                // 0b11 is reserved
}

/// EVEX tuple type table for compressed displacement (NCD8).
/// Maps (tuple_type, vector_length) to multiplication factor.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum EVEXTupleType {
    /// Full tuple: each element occupies its natural size.
    Full,
    /// Half tuple: compressed by factor of 2.
    Half,
    /// Quarter tuple: compressed by factor of 4.
    Quarter,
    /// Eighth tuple: compressed by factor of 8.
    Eighth,
    /// Mem128: 128-bit memory access, disp8*16.
    Mem128,
    /// MOVDDUP: special case.
    Movddup,
}

impl EVEXTupleType {
    /// Get the NCD8 multiplier given the tuple type and vector length.
    pub fn ncd8_multiplier(self, vl: u8) -> u8 {
        use evex_vector_length::*;
        use EVEXTupleType::*;
        match (self, vl) {
            (Full, VL128) | (Full, VL256) | (Full, VL512) => 1,
            (Half, VL128) => 1,
            (Half, VL256) => 2,
            (Half, VL512) => 4,
            (Quarter, VL128) => 1,
            (Quarter, VL256) => 2,
            (Quarter, VL512) => 4,
            (Eighth, VL128) => 1,
            (Eighth, VL256) => 2,
            (Eighth, VL512) => 4,
            (Mem128, _) => 16,
            (Movddup, VL128) => 8,
            (Movddup, VL256) => 32,
            (Movddup, VL512) => 64,
            _ => 1, // Unknown tuple type or VL combination — default to 1
        }
    }
}

// ============================================================================
// XOP Prefix Encoding (AMD)
// ============================================================================

/// XOP (eXtended Operations) prefix: AMD-specific 3-byte prefix.
///
/// XOP layout: [8F] [~R ~X ~B m-mmmm] [W vvvv L pp]
/// This is structurally identical to 3-byte VEX with 0x8F prefix instead of 0xC4.
pub mod xop_layout {
    pub const XOP_MAGIC: u8 = 0x8F;
}

/// Build a 3-byte XOP prefix.
pub fn build_xop_prefix(
    not_r: bool,
    not_x: bool,
    not_b: bool,
    map_select: u8,
    w: bool,
    vvvv: u8,
    l: bool,
    pp: u8,
) -> [u8; 3] {
    let byte1 = (if not_r { 0x80 } else { 0x00 })
        | (if not_x { 0x40 } else { 0x00 })
        | (if not_b { 0x20 } else { 0x00 })
        | (map_select & 0x1F);
    let byte2 = (if w { 0x80 } else { 0x00 })
        | ((!vvvv & 0x0F) << 3)
        | (if l { 0x04 } else { 0x00 })
        | (pp & 0x03);
    [xop_layout::XOP_MAGIC, byte1, byte2]
}

// ============================================================================
// Compressed Displacement (NCD8 — disp8*N)
// ============================================================================

/// NCD8 (New Compact Displacement, 8-bit) table.
/// Maps instruction types to their disp8 multiplier for EVEX encoding.
/// The effective displacement = disp8_byte * multiplier.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct NCD8Entry {
    /// The multiplier N (1, 2, 4, 8, 16, 32, 64).
    pub multiplier: u8,
    /// The tuple type name for this multiplier.
    pub tuple: &'static str,
}

/// NCD8 lookup table: maps (broadcast, vector_length, tuple_type) to multiplier.
pub const NCD8_TABLE: [NCD8Entry; 7] = [
    NCD8Entry {
        multiplier: 1,
        tuple: "Full",
    },
    NCD8Entry {
        multiplier: 2,
        tuple: "Half",
    },
    NCD8Entry {
        multiplier: 4,
        tuple: "Quarter",
    },
    NCD8Entry {
        multiplier: 8,
        tuple: "Eighth",
    },
    NCD8Entry {
        multiplier: 16,
        tuple: "Mem128",
    },
    NCD8Entry {
        multiplier: 32,
        tuple: "HalfMem",
    },
    NCD8Entry {
        multiplier: 64,
        tuple: "QuarterMem",
    },
];

/// Compute the NCD8 multiplier for a given configuration.
pub fn ncd8_multiplier(broadcast: bool, vector_length: u8, tuple_type: &str) -> u8 {
    // For EVEX compressed displacement (disp8*N)
    match (broadcast, vector_length, tuple_type) {
        (false, 0, "Full") => 1,
        (false, 1, "Full") => 1,
        (false, 2, "Full") => 1,
        (false, 0, "Half") => 1,
        (false, 1, "Half") => 2,
        (false, 2, "Half") => 4,
        (false, 0, "Quarter") => 1,
        (false, 1, "Quarter") => 2,
        (false, 2, "Quarter") => 4,
        (false, 0, "Eighth") => 1,
        (false, 1, "Eighth") => 2,
        (false, 2, "Eighth") => 4,
        (false, _, "Mem128") => 16,
        (true, 0, "Full") => 1,
        (true, 1, "Full") => 8,    // broadcast {1to8}
        (true, 2, "Full") => 16,   // broadcast {1to16}
        (true, 1, "Half") => 4,    // broadcast {1to4}
        (true, 2, "Half") => 8,    // broadcast {1to8}
        (true, 1, "Quarter") => 2, // broadcast {1to2}
        (true, 2, "Quarter") => 4, // broadcast {1to4}
        _ => 1,
    }
}

/// Encode a displacement as compressed disp8*N for EVEX.
/// Returns the disp8 byte if the displacement is a multiple of N and fits in 8 bits,
/// otherwise returns None (fall back to disp32).
pub fn encode_ncd8_displacement(disp: i64, multiplier: u8) -> Option<u8> {
    let m = multiplier as i64;
    if disp % m == 0 {
        let compressed = disp / m;
        if (-128i64..=127i64).contains(&compressed) {
            return Some(compressed as u8);
        }
    }
    None
}

// ============================================================================
// Branch Displacement Encoding with Automatic Relaxation
// ============================================================================

/// Branch displacement type.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum BranchDisplacement {
    /// Short branch: 1-byte signed offset (rel8), range [-128, 127].
    Short(i8),
    /// Near branch: 4-byte signed offset (rel32), range [-2^31, 2^31-1].
    Near(i32),
}

impl BranchDisplacement {
    /// Encode the branch displacement into bytes.
    pub fn to_bytes(self) -> Vec<u8> {
        match self {
            BranchDisplacement::Short(disp) => vec![disp as u8],
            BranchDisplacement::Near(disp) => disp.to_le_bytes().to_vec(),
        }
    }

    /// Number of bytes for this displacement.
    pub fn byte_count(self) -> usize {
        match self {
            BranchDisplacement::Short(_) => 1,
            BranchDisplacement::Near(_) => 4,
        }
    }

    /// Whether this is a short (rel8) displacement.
    pub fn is_short(self) -> bool {
        matches!(self, BranchDisplacement::Short(_))
    }

    /// Whether this is a near (rel32) displacement.
    pub fn is_near(self) -> bool {
        matches!(self, BranchDisplacement::Near(_))
    }
}

/// Automatic branch displacement relaxation.
///
/// Given a target offset and current PC, determines the optimal encoding.
/// Tries rel8 first; falls back to rel32 if the offset doesn't fit in 8 bits.
pub fn relax_branch_displacement(target_offset: i64, current_pc: i64) -> BranchDisplacement {
    let rel = target_offset - current_pc;
    if (-128i64..=127i64).contains(&rel) {
        BranchDisplacement::Short(rel as i8)
    } else {
        BranchDisplacement::Near(rel as i32)
    }
}

/// Compute the size of a branch instruction given its displacement.
pub fn branch_instruction_size(_opcode: u8, disp: BranchDisplacement) -> usize {
    1 + disp.byte_count() // 1 byte opcode + displacement
}

// ============================================================================
// Full instruction encoding tables
// ============================================================================

/// Complete encoding descriptor for an X86 instruction.
#[derive(Debug, Clone)]
pub struct InstructionEncoding {
    /// Primary opcode byte(s) (1-3 bytes).
    pub opcode_bytes: Vec<u8>,
    /// Whether the instruction uses a ModR/M byte.
    pub has_modrm: bool,
    /// Whether the instruction uses a SIB byte.
    pub has_sib: bool,
    /// Whether REX prefix is required.
    pub requires_rex: bool,
    /// Whether VEX prefix is required.
    pub requires_vex: bool,
    /// Whether EVEX prefix is required.
    pub requires_evex: bool,
    /// Immediate size in bytes (0 if no immediate).
    pub immediate_size: u8,
    /// Implied mandatory prefix for SSE/AVX (0=none, 0x66/0xF3/0xF2).
    pub implied_prefix: u8,
    /// Opcode map for VEX/EVEX (0=0F, 1=0F38, 2=0F3A).
    pub opcode_map: u8,
    /// Displacement size (0, 1, or 4).
    pub displacement_size: u8,
}

impl Default for InstructionEncoding {
    fn default() -> Self {
        InstructionEncoding {
            opcode_bytes: Vec::new(),
            has_modrm: true,
            has_sib: false,
            requires_rex: false,
            requires_vex: false,
            requires_evex: false,
            immediate_size: 0,
            implied_prefix: 0,
            opcode_map: 0,
            displacement_size: 0,
        }
    }
}

/// Lookup table entry: maps opcode to its encoding descriptor.
#[derive(Debug, Clone)]
pub struct EncodingLookupEntry {
    /// The opcode byte pattern (up to 3 bytes).
    pub bytes: Vec<u8>,
    /// The encoding descriptor.
    pub encoding: InstructionEncoding,
}

/// Build a complete encoding descriptor for a standard ALU instruction (ADD, SUB, etc.).
pub fn alu_encoding(op_rm_r: u8, _op_r_rm: u8, _group_reg: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_rm_r],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// Build an encoding descriptor for SSE instructions (0x66 prefix implied).
pub fn sse_encoding(_op_0f: u8, op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0x66,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// Build an encoding descriptor for VEX instructions.
pub fn vex_encoding(map: u8, op_suffix: u8, pp: u8, _is_256bit: bool) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: true,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: pp,
        opcode_map: map,
        displacement_size: 0,
    }
}

/// Build an encoding descriptor for EVEX instructions.
pub fn evex_encoding(map: u8, op_suffix: u8, pp: u8, _is_512bit: bool) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: true,
        immediate_size: 0,
        implied_prefix: pp,
        opcode_map: map,
        displacement_size: 0,
    }
}

// ============================================================================
// Common encoding tables for top 100+ X86 instructions
// ============================================================================

/// Encoding table entry for a named instruction.
#[derive(Debug, Clone)]
pub struct NamedEncoding {
    /// The X86 opcode constant.
    pub opcode: u32,
    /// Instruction mnemonic.
    pub mnemonic: &'static str,
    /// Encoding descriptor.
    pub encoding: InstructionEncoding,
}

/// Complete encoding table for common X86 instructions.
pub fn common_encoding_table() -> Vec<NamedEncoding> {
    vec![
        // Data movement
        NamedEncoding {
            opcode: 1,
            mnemonic: "mov",
            encoding: mov_encoding(),
        },
        NamedEncoding {
            opcode: 35,
            mnemonic: "movsx",
            encoding: sse_encoding(0xBE, 0),
        },
        NamedEncoding {
            opcode: 36,
            mnemonic: "movzx",
            encoding: sse_encoding(0xB6, 0),
        },
        // Arithmetic
        NamedEncoding {
            opcode: 2,
            mnemonic: "add",
            encoding: alu_encoding(0x01, 0x03, 0),
        },
        NamedEncoding {
            opcode: 3,
            mnemonic: "sub",
            encoding: alu_encoding(0x29, 0x2B, 5),
        },
        NamedEncoding {
            opcode: 6,
            mnemonic: "and",
            encoding: alu_encoding(0x21, 0x23, 4),
        },
        NamedEncoding {
            opcode: 7,
            mnemonic: "or",
            encoding: alu_encoding(0x09, 0x0B, 1),
        },
        NamedEncoding {
            opcode: 8,
            mnemonic: "xor",
            encoding: alu_encoding(0x31, 0x33, 6),
        },
        NamedEncoding {
            opcode: 18,
            mnemonic: "cmp",
            encoding: alu_encoding(0x39, 0x3B, 7),
        },
        NamedEncoding {
            opcode: 24,
            mnemonic: "adc",
            encoding: alu_encoding(0x11, 0x13, 2),
        },
        NamedEncoding {
            opcode: 25,
            mnemonic: "sbb",
            encoding: alu_encoding(0x19, 0x1B, 3),
        },
        NamedEncoding {
            opcode: 27,
            mnemonic: "imul",
            encoding: sse_encoding(0xAF, 0),
        },
        NamedEncoding {
            opcode: 19,
            mnemonic: "lea",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x8D],
                has_modrm: true,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Shifts
        NamedEncoding {
            opcode: 9,
            mnemonic: "shl",
            encoding: shift_encoding(),
        },
        NamedEncoding {
            opcode: 10,
            mnemonic: "shr",
            encoding: shift_encoding(),
        },
        NamedEncoding {
            opcode: 29,
            mnemonic: "sar",
            encoding: shift_encoding(),
        },
        // Control flow
        NamedEncoding {
            opcode: 13,
            mnemonic: "call",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0xE8],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 4,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 14,
            mnemonic: "ret",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0xC3],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 15,
            mnemonic: "jmp",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0xE9],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 4,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Stack
        NamedEncoding {
            opcode: 11,
            mnemonic: "push",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0xFF],
                has_modrm: true,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 12,
            mnemonic: "pop",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x8F],
                has_modrm: true,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 26,
            mnemonic: "test",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x85],
                has_modrm: true,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Bit operations
        NamedEncoding {
            opcode: 72,
            mnemonic: "bt",
            encoding: sse_encoding(0xA3, 0),
        },
        NamedEncoding {
            opcode: 73,
            mnemonic: "bts",
            encoding: sse_encoding(0xAB, 0),
        },
        NamedEncoding {
            opcode: 74,
            mnemonic: "btr",
            encoding: sse_encoding(0xB3, 0),
        },
        NamedEncoding {
            opcode: 75,
            mnemonic: "btc",
            encoding: sse_encoding(0xBB, 0),
        },
        NamedEncoding {
            opcode: 76,
            mnemonic: "bsf",
            encoding: sse_encoding(0xBC, 0),
        },
        NamedEncoding {
            opcode: 77,
            mnemonic: "bsr",
            encoding: sse_encoding(0xBD, 0),
        },
        // Byte swap / exchange
        NamedEncoding {
            opcode: 70,
            mnemonic: "bswap",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x0F, 0xC8],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 71,
            mnemonic: "xchg",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x87],
                has_modrm: true,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Sign extension
        NamedEncoding {
            opcode: 78,
            mnemonic: "cbw",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x98],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 79,
            mnemonic: "cwde",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x98],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 80,
            mnemonic: "cdqe",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x48, 0x98],
                has_modrm: false,
                has_sib: false,
                requires_rex: true,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Flags
        NamedEncoding {
            opcode: 84,
            mnemonic: "lahf",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x9F],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 85,
            mnemonic: "sahf",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x9E],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // System
        NamedEncoding {
            opcode: 97,
            mnemonic: "syscall",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x0F, 0x05],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 99,
            mnemonic: "hlt",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0xF4],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 100,
            mnemonic: "rdtsc",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x0F, 0x31],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        NamedEncoding {
            opcode: 101,
            mnemonic: "cpuid",
            encoding: InstructionEncoding {
                opcode_bytes: vec![0x0F, 0xA2],
                has_modrm: false,
                has_sib: false,
                requires_rex: false,
                requires_vex: false,
                requires_evex: false,
                immediate_size: 0,
                implied_prefix: 0,
                opcode_map: 0,
                displacement_size: 0,
            },
        },
        // Conditional moves
        NamedEncoding {
            opcode: 42,
            mnemonic: "cmove",
            encoding: sse_encoding(0x44, 0),
        },
        NamedEncoding {
            opcode: 43,
            mnemonic: "cmovne",
            encoding: sse_encoding(0x45, 0),
        },
        NamedEncoding {
            opcode: 50,
            mnemonic: "cmovl",
            encoding: sse_encoding(0x4C, 0),
        },
        NamedEncoding {
            opcode: 53,
            mnemonic: "cmovg",
            encoding: sse_encoding(0x4F, 0),
        },
        // === SSE Scalar ===
        NamedEncoding {
            opcode: 117,
            mnemonic: "addss",
            encoding: sse33_encoding(0x58),
        },
        NamedEncoding {
            opcode: 118,
            mnemonic: "addsd",
            encoding: ssef2_encoding(0x58),
        },
        NamedEncoding {
            opcode: 119,
            mnemonic: "subss",
            encoding: sse33_encoding(0x5C),
        },
        NamedEncoding {
            opcode: 120,
            mnemonic: "subsd",
            encoding: ssef2_encoding(0x5C),
        },
        NamedEncoding {
            opcode: 121,
            mnemonic: "mulss",
            encoding: sse33_encoding(0x59),
        },
        NamedEncoding {
            opcode: 122,
            mnemonic: "mulsd",
            encoding: ssef2_encoding(0x59),
        },
        NamedEncoding {
            opcode: 123,
            mnemonic: "divss",
            encoding: sse33_encoding(0x5E),
        },
        NamedEncoding {
            opcode: 124,
            mnemonic: "divsd",
            encoding: ssef2_encoding(0x5E),
        },
        NamedEncoding {
            opcode: 125,
            mnemonic: "sqrtss",
            encoding: sse33_encoding(0x51),
        },
        NamedEncoding {
            opcode: 126,
            mnemonic: "sqrtsd",
            encoding: ssef2_encoding(0x51),
        },
        NamedEncoding {
            opcode: 127,
            mnemonic: "minss",
            encoding: sse33_encoding(0x5D),
        },
        NamedEncoding {
            opcode: 128,
            mnemonic: "minsd",
            encoding: ssef2_encoding(0x5D),
        },
        NamedEncoding {
            opcode: 129,
            mnemonic: "maxss",
            encoding: sse33_encoding(0x5F),
        },
        NamedEncoding {
            opcode: 130,
            mnemonic: "maxsd",
            encoding: ssef2_encoding(0x5F),
        },
        NamedEncoding {
            opcode: 131,
            mnemonic: "cmpss",
            encoding: sse33_imm8_encoding(0xC2),
        },
        NamedEncoding {
            opcode: 132,
            mnemonic: "cmpsd",
            encoding: ssef2_imm8_encoding(0xC2),
        },
        NamedEncoding {
            opcode: 133,
            mnemonic: "cvtsi2ss",
            encoding: sse33_encoding(0x2A),
        },
        NamedEncoding {
            opcode: 134,
            mnemonic: "cvtsi2sd",
            encoding: ssef2_encoding(0x2A),
        },
        NamedEncoding {
            opcode: 135,
            mnemonic: "cvtss2si",
            encoding: sse33_encoding(0x2D),
        },
        NamedEncoding {
            opcode: 136,
            mnemonic: "cvtsd2si",
            encoding: ssef2_encoding(0x2D),
        },
        NamedEncoding {
            opcode: 137,
            mnemonic: "cvttss2si",
            encoding: sse33_encoding(0x2C),
        },
        NamedEncoding {
            opcode: 138,
            mnemonic: "cvttsd2si",
            encoding: ssef2_encoding(0x2C),
        },
        // === SSE Packed Arithmetic ===
        NamedEncoding {
            opcode: 244,
            mnemonic: "addps",
            encoding: sse0f_encoding(0x58),
        },
        NamedEncoding {
            opcode: 245,
            mnemonic: "addpd",
            encoding: sse66_encoding(0x58),
        },
        NamedEncoding {
            opcode: 246,
            mnemonic: "subps",
            encoding: sse0f_encoding(0x5C),
        },
        NamedEncoding {
            opcode: 247,
            mnemonic: "subpd",
            encoding: sse66_encoding(0x5C),
        },
        NamedEncoding {
            opcode: 248,
            mnemonic: "mulps",
            encoding: sse0f_encoding(0x59),
        },
        NamedEncoding {
            opcode: 249,
            mnemonic: "mulpd",
            encoding: sse66_encoding(0x59),
        },
        NamedEncoding {
            opcode: 250,
            mnemonic: "divps",
            encoding: sse0f_encoding(0x5E),
        },
        NamedEncoding {
            opcode: 251,
            mnemonic: "divpd",
            encoding: sse66_encoding(0x5E),
        },
        // === SSE Packed Logical ===
        NamedEncoding {
            opcode: 139,
            mnemonic: "andps",
            encoding: sse0f_encoding(0x54),
        },
        NamedEncoding {
            opcode: 140,
            mnemonic: "andnps",
            encoding: sse0f_encoding(0x55),
        },
        NamedEncoding {
            opcode: 141,
            mnemonic: "orps",
            encoding: sse0f_encoding(0x56),
        },
        NamedEncoding {
            opcode: 142,
            mnemonic: "xorps",
            encoding: sse0f_encoding(0x57),
        },
        NamedEncoding {
            opcode: X86Opcode::ANDPD as u32,
            mnemonic: "andpd",
            encoding: sse66_encoding(0x54),
        },
        NamedEncoding {
            opcode: X86Opcode::ORPD as u32,
            mnemonic: "orpd",
            encoding: sse66_encoding(0x56),
        },
        NamedEncoding {
            opcode: X86Opcode::XORPD as u32,
            mnemonic: "xorpd",
            encoding: sse66_encoding(0x57),
        },
        NamedEncoding {
            opcode: X86Opcode::ANDNPD as u32,
            mnemonic: "andnpd",
            encoding: sse66_encoding(0x55),
        },
        // === SSE Shuffle ===
        NamedEncoding {
            opcode: 143,
            mnemonic: "shufps",
            encoding: sse0f_imm8_encoding(0xC6),
        },
        NamedEncoding {
            opcode: 144,
            mnemonic: "shufpd",
            encoding: sse66_imm8_encoding(0xC6),
        },
        NamedEncoding {
            opcode: 148,
            mnemonic: "unpcklps",
            encoding: sse0f_encoding(0x14),
        },
        NamedEncoding {
            opcode: 149,
            mnemonic: "unpckhps",
            encoding: sse0f_encoding(0x15),
        },
        NamedEncoding {
            opcode: 150,
            mnemonic: "unpcklpd",
            encoding: sse66_encoding(0x14),
        },
        NamedEncoding {
            opcode: 151,
            mnemonic: "unpckhpd",
            encoding: sse66_encoding(0x15),
        },
        NamedEncoding {
            opcode: 152,
            mnemonic: "movhlps",
            encoding: sse0f_encoding(0x12),
        },
        NamedEncoding {
            opcode: 153,
            mnemonic: "movlhps",
            encoding: sse0f_encoding(0x16),
        },
        // === SSE Conversion ===
        NamedEncoding {
            opcode: 238,
            mnemonic: "cvtss2sd",
            encoding: sse33_encoding(0x5A),
        },
        NamedEncoding {
            opcode: 239,
            mnemonic: "cvtsd2ss",
            encoding: ssef2_encoding(0x5A),
        },
        NamedEncoding {
            opcode: X86Opcode::CVTDQ2PS as u32,
            mnemonic: "cvtdq2ps",
            encoding: sse0f_encoding(0x5B),
        },
        NamedEncoding {
            opcode: X86Opcode::CVTPS2DQ as u32,
            mnemonic: "cvtps2dq",
            encoding: sse66_encoding(0x5B),
        },
        NamedEncoding {
            opcode: X86Opcode::CVTTPS2DQ as u32,
            mnemonic: "cvttps2dq",
            encoding: sse33_encoding(0x5B),
        },
        // === SSE3/SSSE3 ===
        NamedEncoding {
            opcode: 263,
            mnemonic: "movsldup",
            encoding: sse33_encoding(0x12),
        },
        NamedEncoding {
            opcode: 264,
            mnemonic: "movshdup",
            encoding: sse33_encoding(0x16),
        },
        NamedEncoding {
            opcode: 265,
            mnemonic: "movddup",
            encoding: ssef2_encoding(0x12),
        },
        // === SSE4.1 ===
        NamedEncoding {
            opcode: 285,
            mnemonic: "dpps",
            encoding: sse38_imm8_encoding(0x40, 0x66),
        },
        NamedEncoding {
            opcode: 286,
            mnemonic: "dppd",
            encoding: sse38_imm8_encoding(0x41, 0x66),
        },
        NamedEncoding {
            opcode: 281,
            mnemonic: "blendps",
            encoding: sse3a_imm8_encoding(0x0C, 0x66),
        },
        NamedEncoding {
            opcode: 282,
            mnemonic: "blendpd",
            encoding: sse3a_imm8_encoding(0x0D, 0x66),
        },
        NamedEncoding {
            opcode: 283,
            mnemonic: "blendvps",
            encoding: sse38_encoding(0x14, 0x66),
        },
        NamedEncoding {
            opcode: 284,
            mnemonic: "blendvpd",
            encoding: sse38_encoding(0x15, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::ROUNDPS as u32,
            mnemonic: "roundps",
            encoding: sse3a_imm8_encoding(0x08, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::ROUNDPD as u32,
            mnemonic: "roundpd",
            encoding: sse3a_imm8_encoding(0x09, 0x66),
        },
        NamedEncoding {
            opcode: 287,
            mnemonic: "extractps",
            encoding: sse3a_imm8_encoding(0x17, 0x66),
        },
        NamedEncoding {
            opcode: 288,
            mnemonic: "insertps",
            encoding: sse3a_imm8_encoding(0x21, 0x66),
        },
        NamedEncoding {
            opcode: 289,
            mnemonic: "pmulld",
            encoding: sse38_encoding(0x40, 0x66),
        },
        NamedEncoding {
            opcode: 290,
            mnemonic: "pmuldq",
            encoding: sse38_encoding(0x28, 0x66),
        },
        NamedEncoding {
            opcode: 291,
            mnemonic: "pminsb",
            encoding: sse38_encoding(0x38, 0x66),
        },
        NamedEncoding {
            opcode: 292,
            mnemonic: "pminsd",
            encoding: sse38_encoding(0x39, 0x66),
        },
        NamedEncoding {
            opcode: 293,
            mnemonic: "pminuw",
            encoding: sse38_encoding(0x3A, 0x66),
        },
        NamedEncoding {
            opcode: 294,
            mnemonic: "pminud",
            encoding: sse38_encoding(0x3B, 0x66),
        },
        NamedEncoding {
            opcode: 295,
            mnemonic: "pmaxsb",
            encoding: sse38_encoding(0x3C, 0x66),
        },
        NamedEncoding {
            opcode: 296,
            mnemonic: "pmaxsd",
            encoding: sse38_encoding(0x3D, 0x66),
        },
        NamedEncoding {
            opcode: 297,
            mnemonic: "pmaxuw",
            encoding: sse38_encoding(0x3E, 0x66),
        },
        NamedEncoding {
            opcode: 298,
            mnemonic: "pmaxud",
            encoding: sse38_encoding(0x3F, 0x66),
        },
        NamedEncoding {
            opcode: 299,
            mnemonic: "packusdw",
            encoding: sse38_encoding(0x2B, 0x66),
        },
        NamedEncoding {
            opcode: 300,
            mnemonic: "pcmpeqq",
            encoding: sse38_encoding(0x29, 0x66),
        },
        NamedEncoding {
            opcode: 154,
            mnemonic: "pextrb",
            encoding: sse3a_imm8_encoding(0x14, 0x66),
        },
        NamedEncoding {
            opcode: 155,
            mnemonic: "pextrw",
            encoding: sse3a_imm8_encoding(0x15, 0x66),
        },
        NamedEncoding {
            opcode: 156,
            mnemonic: "pextrd",
            encoding: sse3a_imm8_encoding(0x16, 0x66),
        },
        NamedEncoding {
            opcode: 157,
            mnemonic: "pextrq",
            encoding: sse3a_imm8_encoding_rexw(0x16, 0x66),
        },
        NamedEncoding {
            opcode: 158,
            mnemonic: "pinsrb",
            encoding: sse3a_imm8_encoding(0x20, 0x66),
        },
        NamedEncoding {
            opcode: 159,
            mnemonic: "pinsrw",
            encoding: sse3a_imm8_encoding(0xC4, 0x66),
        },
        NamedEncoding {
            opcode: 160,
            mnemonic: "pinsrd",
            encoding: sse3a_imm8_encoding(0x22, 0x66),
        },
        NamedEncoding {
            opcode: 161,
            mnemonic: "pinsrq",
            encoding: sse3a_imm8_encoding_rexw(0x22, 0x66),
        },
        // === SSE4.2 ===
        NamedEncoding {
            opcode: 301,
            mnemonic: "crc32",
            encoding: crc32_encoding(),
        },
        // === AES-NI ===
        NamedEncoding {
            opcode: X86Opcode::AESENC as u32,
            mnemonic: "aesenc",
            encoding: aes_encoding(0xDC),
        },
        NamedEncoding {
            opcode: X86Opcode::AESENCLAST as u32,
            mnemonic: "aesenclast",
            encoding: aes_encoding(0xDD),
        },
        NamedEncoding {
            opcode: X86Opcode::AESDEC as u32,
            mnemonic: "aesdec",
            encoding: aes_encoding(0xDE),
        },
        NamedEncoding {
            opcode: X86Opcode::AESDECLAST as u32,
            mnemonic: "aesdeclast",
            encoding: aes_encoding(0xDF),
        },
        NamedEncoding {
            opcode: X86Opcode::AESIMC as u32,
            mnemonic: "aesimc",
            encoding: aes_encoding(0xDB),
        },
        NamedEncoding {
            opcode: X86Opcode::AESKEYGENASSIST as u32,
            mnemonic: "aeskeygenassist",
            encoding: aes_keygen_encoding(),
        },
        // === PCLMULQDQ ===
        NamedEncoding {
            opcode: X86Opcode::PCLMULQDQ as u32,
            mnemonic: "pclmulqdq",
            encoding: pclmul_encoding(),
        },
        // === SHA ===
        NamedEncoding {
            opcode: X86Opcode::SHA1RNDS4 as u32,
            mnemonic: "sha1rnds4",
            encoding: sha_imm8_encoding(0xCC),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA1NEXTE as u32,
            mnemonic: "sha1nexte",
            encoding: sha_encoding(0xC8),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA1MSG1 as u32,
            mnemonic: "sha1msg1",
            encoding: sha_encoding(0xC9),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA1MSG2 as u32,
            mnemonic: "sha1msg2",
            encoding: sha_encoding(0xCA),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA256RNDS2 as u32,
            mnemonic: "sha256rnds2",
            encoding: sha_encoding(0xCB),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA256MSG1 as u32,
            mnemonic: "sha256msg1",
            encoding: sha_encoding(0xCC),
        },
        NamedEncoding {
            opcode: X86Opcode::SHA256MSG2 as u32,
            mnemonic: "sha256msg2",
            encoding: sha_encoding(0xCD),
        },
        // === AVX 128-bit scalar ===
        NamedEncoding {
            opcode: 306,
            mnemonic: "vaddss",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x58, 0xF3),
        },
        NamedEncoding {
            opcode: 307,
            mnemonic: "vaddsd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x58, 0xF2),
        },
        NamedEncoding {
            opcode: X86Opcode::VSUBSS as u32,
            mnemonic: "vsubss",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5C, 0xF3),
        },
        NamedEncoding {
            opcode: X86Opcode::VSUBSD as u32,
            mnemonic: "vsubsd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5C, 0xF2),
        },
        NamedEncoding {
            opcode: X86Opcode::VMULSS as u32,
            mnemonic: "vmulss",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x59, 0xF3),
        },
        NamedEncoding {
            opcode: X86Opcode::VMULSD as u32,
            mnemonic: "vmulsd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x59, 0xF2),
        },
        NamedEncoding {
            opcode: X86Opcode::VDIVSS as u32,
            mnemonic: "vdivss",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5E, 0xF3),
        },
        NamedEncoding {
            opcode: X86Opcode::VDIVSD as u32,
            mnemonic: "vdivsd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5E, 0xF2),
        },
        // === AVX 128-bit packed ===
        NamedEncoding {
            opcode: 304,
            mnemonic: "vaddps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x58, 0x00),
        },
        NamedEncoding {
            opcode: 305,
            mnemonic: "vaddpd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x58, 0x66),
        },
        NamedEncoding {
            opcode: 308,
            mnemonic: "vsubps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5C, 0x00),
        },
        NamedEncoding {
            opcode: 309,
            mnemonic: "vsubpd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5C, 0x66),
        },
        NamedEncoding {
            opcode: 310,
            mnemonic: "vmulps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x59, 0x00),
        },
        NamedEncoding {
            opcode: 311,
            mnemonic: "vmulpd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x59, 0x66),
        },
        NamedEncoding {
            opcode: 312,
            mnemonic: "vdivps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5E, 0x00),
        },
        NamedEncoding {
            opcode: 313,
            mnemonic: "vdivpd",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x5E, 0x66),
        },
        NamedEncoding {
            opcode: 314,
            mnemonic: "vandps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x54, 0x00),
        },
        NamedEncoding {
            opcode: 315,
            mnemonic: "vandnps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x55, 0x00),
        },
        NamedEncoding {
            opcode: 316,
            mnemonic: "vorps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x56, 0x00),
        },
        NamedEncoding {
            opcode: 317,
            mnemonic: "vxorps",
            encoding: vex_128_encoding(vex_map::MAP_0F, 0x57, 0x00),
        },
        // === FMA ===
        NamedEncoding {
            opcode: 350,
            mnemonic: "vfmadd132ps",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0x98, 0x66),
        },
        NamedEncoding {
            opcode: 351,
            mnemonic: "vfmadd213ps",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xA8, 0x66),
        },
        NamedEncoding {
            opcode: 352,
            mnemonic: "vfmadd231ps",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xB8, 0x66),
        },
        NamedEncoding {
            opcode: 338,
            mnemonic: "vfmadd132pd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0x98, 0x66),
        },
        NamedEncoding {
            opcode: 339,
            mnemonic: "vfmadd213pd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xA8, 0x66),
        },
        NamedEncoding {
            opcode: 340,
            mnemonic: "vfmadd231pd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xB8, 0x66),
        },
        NamedEncoding {
            opcode: 353,
            mnemonic: "vfmadd132ss",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0x99, 0x66),
        },
        NamedEncoding {
            opcode: 354,
            mnemonic: "vfmadd213ss",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xA9, 0x66),
        },
        NamedEncoding {
            opcode: 355,
            mnemonic: "vfmadd231ss",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xB9, 0x66),
        },
        NamedEncoding {
            opcode: 356,
            mnemonic: "vfmadd132sd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0x99, 0xF2),
        },
        NamedEncoding {
            opcode: 357,
            mnemonic: "vfmadd213sd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xA9, 0xF2),
        },
        NamedEncoding {
            opcode: 358,
            mnemonic: "vfmadd231sd",
            encoding: vex_128_encoding(vex_map::MAP_0F38, 0xB9, 0xF2),
        },
        // === AVX2 Integer ===
        NamedEncoding {
            opcode: X86Opcode::VPADDB as u32,
            mnemonic: "vpaddb",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xFC, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPADDW as u32,
            mnemonic: "vpaddw",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xFD, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPADDD as u32,
            mnemonic: "vpaddd",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xFE, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPADDQ as u32,
            mnemonic: "vpaddq",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xD4, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPSUBB as u32,
            mnemonic: "vpsubb",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xF8, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPSUBW as u32,
            mnemonic: "vpsubw",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xF9, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPSUBD as u32,
            mnemonic: "vpsubd",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xFA, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPSUBQ as u32,
            mnemonic: "vpsubq",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xFB, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPMULLD as u32,
            mnemonic: "vpmulld",
            encoding: vex_256_encoding(vex_map::MAP_0F38, 0x40, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPMULUDQ as u32,
            mnemonic: "vpmuludq",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xF4, 0x66),
        },
        NamedEncoding {
            opcode: X86Opcode::VPMADDWD as u32,
            mnemonic: "vpmaddwd",
            encoding: vex_256_encoding(vex_map::MAP_0F, 0xF5, 0x66),
        },
    ]
}

// === SSE/AVX encoding helper functions ===

/// SSE with 0F prefix, no mandatory prefix (used for PS ops)
fn sse0f_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with 0F + imm8, no mandatory prefix
fn sse0f_imm8_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with 66 prefix
fn sse66_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0x66,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with 66 prefix + imm8
fn sse66_imm8_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0x66,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with F3 prefix (SS ops)
fn sse33_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0xF3,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with F3 prefix + imm8
fn sse33_imm8_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0xF3,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with F2 prefix (SD ops)
fn ssef2_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0xF2,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// SSE with F2 prefix + imm8
fn ssef2_imm8_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x0F, op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0xF2,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// 0F38 map encoding with prefix
fn sse38_encoding(op_suffix: u8, prefix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: prefix,
        opcode_map: 2,
        displacement_size: 0,
    }
}

/// 0F38 map encoding with prefix + imm8
fn sse38_imm8_encoding(op_suffix: u8, prefix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: prefix,
        opcode_map: 2,
        displacement_size: 0,
    }
}

/// 0F3A map encoding with prefix + imm8
fn sse3a_imm8_encoding(op_suffix: u8, prefix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: prefix,
        opcode_map: 3,
        displacement_size: 0,
    }
}

/// 0F3A with REX.W required (PEXTRQ, PINSRQ)
fn sse3a_imm8_encoding_rexw(op_suffix: u8, prefix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: true,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: prefix,
        opcode_map: 3,
        displacement_size: 0,
    }
}

/// VEX.128 encoding
fn vex_128_encoding(map: u8, op_suffix: u8, pp: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: true,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: pp,
        opcode_map: map,
        displacement_size: 0,
    }
}

/// VEX.256 encoding
fn vex_256_encoding(map: u8, op_suffix: u8, pp: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: true,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: pp,
        opcode_map: map,
        displacement_size: 0,
    }
}

/// CRC32 encoding (F2 0F 38 F0 + /r)
fn crc32_encoding() -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0xF0],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0xF2,
        opcode_map: 2,
        displacement_size: 0,
    }
}

/// AES encoding (66 0F 38 XX /r)
fn aes_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0x66,
        opcode_map: 2,
        displacement_size: 0,
    }
}

/// AESKEYGENASSIST encoding (66 0F 3A DF /r imm8)
fn aes_keygen_encoding() -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0xDF],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0x66,
        opcode_map: 3,
        displacement_size: 0,
    }
}

/// PCLMULQDQ encoding (66 0F 3A 44 /r imm8)
fn pclmul_encoding() -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x44],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0x66,
        opcode_map: 3,
        displacement_size: 0,
    }
}

/// SHA encoding (0F 38 XX /r)
fn sha_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0,
        opcode_map: 2,
        displacement_size: 0,
    }
}

/// SHA with imm8 (0F 3A CC /r imm8)
fn sha_imm8_encoding(op_suffix: u8) -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![op_suffix],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 1,
        implied_prefix: 0,
        opcode_map: 3,
        displacement_size: 0,
    }
}

/// Build a default MOV encoding.
// === Build default MOV encoding ===
fn mov_encoding() -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0x89],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0,
        opcode_map: 0,
        displacement_size: 0,
    }
}

/// Build a default shift encoding (SHL, SHR, SAR).
fn shift_encoding() -> InstructionEncoding {
    InstructionEncoding {
        opcode_bytes: vec![0xD3],
        has_modrm: true,
        has_sib: false,
        requires_rex: false,
        requires_vex: false,
        requires_evex: false,
        immediate_size: 0,
        implied_prefix: 0,
        opcode_map: 0,
        displacement_size: 0,
    }
}

// ============================================================================
// Immediate Encoding Helpers
// ============================================================================

/// Encode an immediate value as imm8 bytes.
pub fn encode_imm8(value: i64) -> [u8; 1] {
    [(value & 0xFF) as u8]
}

/// Encode an immediate value as imm16 bytes (little-endian).
pub fn encode_imm16(value: i64) -> [u8; 2] {
    (value as i16).to_le_bytes()
}

/// Encode an immediate value as imm32 bytes (little-endian).
pub fn encode_imm32(value: i64) -> [u8; 4] {
    (value as i32).to_le_bytes()
}

/// Encode an immediate value as imm64 bytes (little-endian).
pub fn encode_imm64(value: i64) -> [u8; 8] {
    value.to_le_bytes()
}

/// Determine the smallest immediate encoding size that can hold the given value.
pub fn min_immediate_size(value: i64) -> u8 {
    if (-128i64..=127i64).contains(&value) {
        1
    } else if (-32768i64..=32767i64).contains(&value) {
        2
    } else if (-2147483648i64..=2147483647i64).contains(&value) {
        4
    } else {
        8
    }
}

/// Check if an immediate value fits in an 8-bit signed integer.
pub fn imm_fits_imm8(value: i64) -> bool {
    (-128i64..=127i64).contains(&value)
}

/// Check if an immediate value fits in a 32-bit signed integer.
pub fn imm_fits_imm32(value: i64) -> bool {
    (-2147483648i64..=2147483647i64).contains(&value)
}

/// Check if the immediate can use the sign-extended imm8 form (e.g., 0x83 for ADD).
pub fn can_use_sign_extended_imm8(value: i64) -> bool {
    (-128i64..=127i64).contains(&value)
}

// ============================================================================
// Instruction Length Computation
// ============================================================================

/// Compute the total length of an encoded instruction in bytes.
pub fn instruction_length(encoding: &InstructionEncoding) -> usize {
    let mut len = 0usize;
    // Prefixes
    if encoding.implied_prefix != 0 {
        len += 1;
    }
    if encoding.requires_rex {
        len += 1;
    }
    if encoding.requires_vex {
        len += if encoding.opcode_map == vex_map::MAP_0F {
            2
        } else {
            3
        };
    }
    if encoding.requires_evex {
        len += 4;
    }
    // Opcode
    len += encoding.opcode_bytes.len();
    // ModR/M
    if encoding.has_modrm {
        len += 1;
    }
    // SIB
    if encoding.has_sib {
        len += 1;
    }
    // Displacement
    len += encoding.displacement_size as usize;
    // Immediate
    len += encoding.immediate_size as usize;
    len
}

// ============================================================================
// Misc encoding helpers
// ============================================================================

/// Check if an 8-bit register is a high-byte register (AH, BH, CH, DH).
/// These require special handling because they conflict with REX encoding.
pub fn is_high_byte_reg(reg_field: u8) -> bool {
    // AH=4, CH=5, DH=6, BH=7 in the ModR/M r/m field
    matches!(reg_field, 4 | 5 | 6 | 7)
}

/// Get the one-byte opcode for an INC/DEC register instruction.
/// INC r64: 0x40+reg (uses the REX prefix range in 64-bit mode with REX.W).
pub fn inc_reg_opcode(reg_field: u8) -> u8 {
    0x40 | (reg_field & 0x07)
}

/// Get the one-byte opcode for a PUSH register instruction (0x50+reg).
pub fn push_reg_opcode(reg_field: u8) -> u8 {
    0x50 | (reg_field & 0x07)
}

/// Get the one-byte opcode for a POP register instruction (0x58+reg).
pub fn pop_reg_opcode(reg_field: u8) -> u8 {
    0x58 | (reg_field & 0x07)
}

/// Get the one-byte XCHG RAX,reg opcode (0x90+reg). NOP is 0x90 (XCHG EAX,EAX).
pub fn xchg_rax_opcode(reg_field: u8) -> u8 {
    0x90 | (reg_field & 0x07)
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;
    use crate::codegen::{MachineBasicBlock, MachineFunction};
    use crate::x86::x86_register_info::*;

    fn make_subtarget(mode: X86Mode) -> X86Subtarget {
        let triple = if mode.is_64bit() {
            "x86_64-unknown-none"
        } else {
            "i686-unknown-none"
        };
        let mut st = X86Subtarget::new(triple, "generic", "");
        st.is_64_bit = mode.is_64bit();
        st
    }

    fn make_instr(opcode: u32, operands: Vec<MachineOperand>) -> MachineInstr {
        MachineInstr {
            opcode,
            operands,
            def: None,
        }
    }

    fn phys_reg(id: u16) -> MachineOperand {
        MachineOperand::PhysReg(id as u32)
    }

    fn imm(val: i64) -> MachineOperand {
        MachineOperand::Imm(val)
    }

    // ========================================================================
    // REX prefix tests
    // ========================================================================

    #[test]
    fn test_encode_rex_prefix_no_flags() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(false, false, false, false);
        assert_eq!(rex, 0x40);
    }

    #[test]
    fn test_encode_rex_prefix_w() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(true, false, false, false);
        assert_eq!(rex, 0x48);
    }

    #[test]
    fn test_encode_rex_prefix_r() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(false, true, false, false);
        assert_eq!(rex, 0x44);
    }

    #[test]
    fn test_encode_rex_prefix_x() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(false, false, true, false);
        assert_eq!(rex, 0x42);
    }

    #[test]
    fn test_encode_rex_prefix_b() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(false, false, false, true);
        assert_eq!(rex, 0x41);
    }

    #[test]
    fn test_encode_rex_prefix_all() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let rex = enc.encode_rex_prefix(true, true, true, true);
        assert_eq!(rex, 0x4F);
    }

    // ========================================================================
    // Register field tests
    // ========================================================================

    #[test]
    fn test_get_reg_field_gpr64() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // RAX=0 -> field 0
        assert_eq!(enc.get_reg_field(RAX), 0);
        // RCX=1 -> field 1
        assert_eq!(enc.get_reg_field(RCX), 1);
        // RDX=2 -> field 2
        assert_eq!(enc.get_reg_field(RDX), 2);
        // RBX=3 -> field 3
        assert_eq!(enc.get_reg_field(RBX), 3);
        // RSP=4 -> field 4
        assert_eq!(enc.get_reg_field(RSP), 4);
        // RBP=5 -> field 5
        assert_eq!(enc.get_reg_field(RBP), 5);
        // RSI=6 -> field 6
        assert_eq!(enc.get_reg_field(RSI), 6);
        // RDI=7 -> field 7
        assert_eq!(enc.get_reg_field(RDI), 7);
        // R8=8 -> field 0 (with REX.B)
        assert_eq!(enc.get_reg_field(R8), 0);
        // R9=9 -> field 1 (with REX.B)
        assert_eq!(enc.get_reg_field(R9), 1);
        // R15=15 -> field 7 (with REX.B)
        assert_eq!(enc.get_reg_field(R15), 7);
    }

    #[test]
    fn test_get_reg_field_gpr32() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        assert_eq!(enc.get_reg_field(EAX), 0); // EAX=16 -> 0
        assert_eq!(enc.get_reg_field(ECX), 1); // ECX=17 -> 1
        assert_eq!(enc.get_reg_field(EDX), 2); // EDX=18 -> 2
        assert_eq!(enc.get_reg_field(R15D), 7); // R15D=31 -> (31-16)&7 = 15&7 = 7
    }

    #[test]
    fn test_get_reg_field_gpr16() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        assert_eq!(enc.get_reg_field(AX), 0); // AX=32 -> 0
        assert_eq!(enc.get_reg_field(BP), 5); // BP=37 -> (37-32)=5
    }

    #[test]
    fn test_get_reg_field_gpr8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        assert_eq!(enc.get_reg_field(AL), 0); // AL=48 -> 0
        assert_eq!(enc.get_reg_field(CL), 1); // CL=49 -> 1
        assert_eq!(enc.get_reg_field(AH), 4); // AH=64 -> (64-60)=4
        assert_eq!(enc.get_reg_field(BH), 7); // BH=67 -> (67-60)=7
    }

    #[test]
    fn test_get_reg_field_xmm() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        assert_eq!(enc.get_reg_field(XMM0), 0);
        assert_eq!(enc.get_reg_field(XMM7), 7);
        assert_eq!(enc.get_reg_field(XMM8), 0); // Rolls over to 0 in low 3 bits
        assert_eq!(enc.get_reg_field(XMM15), 7);
    }

    // ========================================================================
    // ModR/M encoding tests
    // ========================================================================

    #[test]
    fn test_encode_modrm_reg_direct() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // mod=0b11, reg=0, rm=0 -> RAX, RAX
        let b = enc.encode_modrm(mod_field::REG_DIRECT, 0, 0);
        assert_eq!(b, 0xC0); // 0b11000000
    }

    #[test]
    fn test_encode_modrm_mem_no_disp() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // mod=0b00, reg=0, rm=5 -> [RBP] (no disp)
        let b = enc.encode_modrm(mod_field::MEM_NO_DISP, 0, 5);
        assert_eq!(b, 0x05); // 0b00000101
    }

    #[test]
    fn test_encode_modrm_mem_disp8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // mod=0b01, reg=3, rm=7
        let b = enc.encode_modrm(mod_field::MEM_DISP8, 3, 7);
        assert_eq!(b, 0x5F); // 0b01011111
    }

    #[test]
    fn test_encode_modrm_mem_disp32() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // mod=0b10, reg=7, rm=0
        let b = enc.encode_modrm(mod_field::MEM_DISP32, 7, 0);
        assert_eq!(b, 0xB8); // 0b10111000
    }

    // ========================================================================
    // SIB encoding tests
    // ========================================================================

    #[test]
    fn test_encode_sib() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // scale=0 (1), index=0 (RAX), base=4 (RSP)
        let sib = enc.encode_sib(0, 0, 4);
        assert_eq!(sib, 0x04); // 0b00_000_100
    }

    #[test]
    fn test_encode_sib_scale_4_index_rcx_base_rbx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // scale=2 (4), index=1 (RCX), base=3 (RBX)
        let sib = enc.encode_sib(2, 1, 3);
        assert_eq!(sib, 0x8B); // 0b10_001_011
    }

    #[test]
    fn test_encode_sib_no_index() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // scale=0, index=4 (none), base=5 (RBP)
        let sib = enc.encode_sib(0, 4, 5);
        assert_eq!(sib, 0x25); // 0b00_100_101
    }

    // ========================================================================
    // Displacement encoding tests
    // ========================================================================

    #[test]
    fn test_encode_displacement_disp8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_displacement(0x42, mod_field::MEM_DISP8);
        assert_eq!(bytes, vec![0x42]);
    }

    #[test]
    fn test_encode_displacement_disp8_negative() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_displacement(-8, mod_field::MEM_DISP8);
        assert_eq!(bytes, vec![0xF8]);
    }

    #[test]
    fn test_encode_displacement_disp32() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_displacement(0x12345678, mod_field::MEM_DISP32);
        assert_eq!(bytes, vec![0x78, 0x56, 0x34, 0x12]);
    }

    #[test]
    fn test_encode_displacement_no_disp() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_displacement(0, mod_field::MEM_NO_DISP);
        assert!(bytes.is_empty());
    }

    // ========================================================================
    // Immediate encoding tests
    // ========================================================================

    #[test]
    fn test_encode_immediate_imm8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_immediate(42, 1);
        assert_eq!(bytes, vec![42]);
    }

    #[test]
    fn test_encode_immediate_imm8_negative() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_immediate(-1, 1);
        assert_eq!(bytes, vec![0xFF]);
    }

    #[test]
    fn test_encode_immediate_imm32() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_immediate(0xDEADBEEF, 4);
        assert_eq!(bytes, vec![0xEF, 0xBE, 0xAD, 0xDE]);
    }

    #[test]
    fn test_encode_immediate_imm64() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let bytes = enc.encode_immediate(0x0102030405060708, 8);
        assert_eq!(bytes, vec![0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01]);
    }

    // ========================================================================
    // Instruction opcode tests
    // ========================================================================

    #[test]
    fn test_encode_nop() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::NOP, vec![]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0x90]);
    }

    #[test]
    fn test_encode_ret() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::RET, vec![]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0xC3]);
    }

    #[test]
    fn test_encode_push_rax() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::PUSH, vec![phys_reg(RAX)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0x50]);
    }

    #[test]
    fn test_encode_pop_rax() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::POP, vec![phys_reg(RAX)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0x58]);
    }

    #[test]
    fn test_encode_push_rbp() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::PUSH, vec![phys_reg(RBP)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0x55]);
    }

    #[test]
    fn test_encode_call() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::CALL, vec![imm(0)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0xE8]);
    }

    #[test]
    fn test_encode_jmp_rel8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::JMP, vec![imm(10)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0xEB]);
    }

    #[test]
    fn test_encode_jmp_rel32() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::JMP, vec![imm(1000)]);
        let bytes = enc.encode_opcode(&mi);
        assert_eq!(bytes, vec![0xE9]);
    }

    #[test]
    fn test_encode_mov_reg_reg() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // MOV EAX, ECX → 0x89 with ModR/M: reg=ECX(1), r/m=EAX(0)
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(EAX), phys_reg(ECX)]);
        let opcode = enc.encode_opcode(&mi);
        assert_eq!(opcode, vec![0x89]);
    }

    #[test]
    fn test_encode_mov_imm_to_reg() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // MOV RAX, imm → 0xB8 + 0 (reg field for RAX)
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), imm(42)]);
        let opcode = enc.encode_opcode(&mi);
        assert_eq!(opcode, vec![0xB8]);
    }

    #[test]
    fn test_encode_add_reg_reg() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(RAX), phys_reg(RCX)]);
        let opcode = enc.encode_opcode(&mi);
        assert_eq!(opcode, vec![0x01]);
    }

    #[test]
    fn test_encode_add_imm() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(RAX), imm(5)]);
        let opcode = enc.encode_opcode(&mi);
        assert_eq!(opcode, vec![0x83]);
    }

    #[test]
    fn test_encode_sub_reg_reg() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::SUB, vec![phys_reg(RAX), phys_reg(RDX)]);
        let opcode = enc.encode_opcode(&mi);
        assert_eq!(opcode, vec![0x29]);
    }

    // ========================================================================
    // Full instruction encoding tests
    // ========================================================================

    #[test]
    fn test_encode_full_nop() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::NOP, vec![]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x90]);
    }

    #[test]
    fn test_encode_full_ret() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::RET, vec![]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0xC3]);
    }

    #[test]
    fn test_encode_full_push_rax() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::PUSH, vec![phys_reg(RAX)]);
        let bytes = enc.encode_instruction(&mi);
        // PUSH r64: 0x48 (REX.W) + 0x50 (PUSH RAX)
        // REX.W is technically unnecessary but included for consistency in 64-bit mode
        assert_eq!(bytes, vec![0x48, 0x50]);
    }

    #[test]
    fn test_encode_full_add_rax_rcx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // ADD RAX, RCX
        // Opcode: 0x01, ModR/M: mod=0b11, reg=RCX(1), r/m=RAX(0)
        // REX.W for 64-bit: 0x48
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(RAX), phys_reg(RCX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x01, 0xC8]);
        // 0x48 = REX.W, 0x01 = ADD r/m,r, 0xC8 = mod=11 reg=001 rm=000
    }

    #[test]
    fn test_encode_full_add_eax_ecx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // ADD EAX, ECX — 32-bit operands, no REX.W
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(EAX), phys_reg(ECX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x01, 0xC8]);
    }

    #[test]
    fn test_encode_full_add_rax_imm5() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // ADD RAX, 5 — Group 1 with REX.W
        // Opcode: 0x83, ModR/M: mod=0b11, reg/opcode=0 (/0), r/m=RAX(0)
        // REX.W: 0x48, Immediate: 0x05
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(RAX), imm(5)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x83, 0xC0, 0x05]);
    }

    #[test]
    fn test_encode_full_mov_rax_rcx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // MOV RAX, RCX
        // Opcode: 0x89, ModR/M: mod=0b11, reg=RCX(1), r/m=RAX(0)
        // REX.W: 0x48
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), phys_reg(RCX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x89, 0xC8]);
    }

    #[test]
    fn test_encode_full_mov_rax_imm42() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // MOV RAX, 42 — B8+reg form
        // Opcode: 0xB8, REX.W: 0x48, Immediate: 0x2A (42)
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), imm(42)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(
            bytes,
            vec![0x48, 0xB8, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]
        );
    }

    #[test]
    fn test_encode_full_sub_rax_rdx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // SUB RAX, RDX
        // Opcode: 0x29, ModR/M: mod=0b11, reg=RDX(2), r/m=RAX(0)
        // REX.W: 0x48
        let mi = make_instr(x86_opcodes::SUB, vec![phys_reg(RAX), phys_reg(RDX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x29, 0xD0]);
    }

    #[test]
    fn test_encode_full_and_rax_rbx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::AND, vec![phys_reg(RAX), phys_reg(RBX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x21, 0xD8]);
    }

    #[test]
    fn test_encode_full_or_rax_rcx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::OR, vec![phys_reg(RAX), phys_reg(RCX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x09, 0xC8]);
    }

    #[test]
    fn test_encode_full_xor_rax_rax() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        // XOR RAX, RAX (common zeroing idiom)
        let mi = make_instr(x86_opcodes::XOR, vec![phys_reg(RAX), phys_reg(RAX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x31, 0xC0]);
    }

    #[test]
    fn test_encode_full_cmp_rax_rcx() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::CMP, vec![phys_reg(RAX), phys_reg(RCX)]);
        let bytes = enc.encode_instruction(&mi);
        assert_eq!(bytes, vec![0x48, 0x39, 0xC8]);
    }

    // ========================================================================
    // requires_rex tests
    // ========================================================================

    #[test]
    fn test_requires_rex_64bit_gpr() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), phys_reg(RCX)]);
        assert!(enc.requires_rex(&mi));
    }

    #[test]
    fn test_requires_rex_32bit() {
        let enc = X86MCEncoder::new(X86Mode::Mode32, make_subtarget(X86Mode::Mode32));
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), phys_reg(RCX)]);
        assert!(!enc.requires_rex(&mi));
    }

    #[test]
    fn test_requires_rex_r8() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::MOV, vec![phys_reg(R8), phys_reg(R9)]);
        assert!(enc.requires_rex(&mi));
    }

    // ========================================================================
    // requires_modrm tests
    // ========================================================================

    #[test]
    fn test_requires_modrm_nop() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::NOP, vec![]);
        assert!(!enc.requires_modrm(&mi));
    }

    #[test]
    fn test_requires_modrm_ret() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::RET, vec![]);
        assert!(!enc.requires_modrm(&mi));
    }

    #[test]
    fn test_requires_modrm_add() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::ADD, vec![phys_reg(RAX), phys_reg(RCX)]);
        assert!(enc.requires_modrm(&mi));
    }

    #[test]
    fn test_requires_modrm_push_reg() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(x86_opcodes::PUSH, vec![phys_reg(RAX)]);
        assert!(!enc.requires_modrm(&mi));
    }

    // ========================================================================
    // X86Mode tests
    // ========================================================================

    #[test]
    fn test_x86_mode_is_64bit() {
        assert!(X86Mode::Mode64.is_64bit());
        assert!(!X86Mode::Mode32.is_64bit());
        assert!(!X86Mode::Mode16.is_64bit());
    }

    #[test]
    fn test_x86_mode_default_operand_size() {
        assert_eq!(X86Mode::Mode16.default_operand_size(), 2);
        assert_eq!(X86Mode::Mode32.default_operand_size(), 4);
        assert_eq!(X86Mode::Mode64.default_operand_size(), 4);
    }

    #[test]
    fn test_x86_mode_default_address_size() {
        assert_eq!(X86Mode::Mode16.default_address_size(), 2);
        assert_eq!(X86Mode::Mode32.default_address_size(), 4);
        assert_eq!(X86Mode::Mode64.default_address_size(), 8);
    }

    // ========================================================================
    // Unknown opcode fallback test
    // ========================================================================

    #[test]
    fn test_encode_unknown_opcode() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = make_instr(999, vec![]);
        let bytes = enc.encode_opcode(&mi);
        // Unknown opcodes should produce UD2 (0x0F 0x0B)
        assert_eq!(bytes, vec![0x0F, 0x0B]);
    }

    // ========================================================================
    // encode_function test
    // ========================================================================

    #[test]
    fn test_encode_function_simple() {
        let _enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));

        let mbb = MachineBasicBlock {
            name: String::new(),
            instructions: vec![
                make_instr(x86_opcodes::PUSH, vec![phys_reg(RBP)]),
                make_instr(x86_opcodes::MOV, vec![phys_reg(RBP), phys_reg(RSP)]),
                make_instr(x86_opcodes::MOV, vec![phys_reg(RAX), imm(0)]),
                make_instr(x86_opcodes::POP, vec![phys_reg(RBP)]),
                make_instr(x86_opcodes::RET, vec![]),
            ],
            successors: vec![],
        };

        let mf = MachineFunction {
            name: "test_func".into(),
            blocks: vec![mbb],
            virt_reg_counter: 0,
        };

        let bytes = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64))
            .encode_function(&mf);
        assert!(!bytes.is_empty());
        // push rbp: 0x48 (REX.W) + 0x55 (PUSH RBP)
        assert_eq!(bytes[0], 0x48);
        assert_eq!(bytes[1], 0x55);
        // ret: 0xC3 at the end
        assert_eq!(bytes[bytes.len() - 1], 0xC3);
    }

    // ========================================================================
    // Edge cases
    // ========================================================================

    #[test]
    fn test_encode_empty_instruction() {
        let enc = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64));
        let mi = MachineInstr::new(x86_opcodes::NOP);
        let bytes = enc.encode_instruction(&mi);
        assert!(!bytes.is_empty());
    }

    #[test]
    fn test_encode_function_empty() {
        let mf = MachineFunction::new("empty_func");
        let bytes = X86MCEncoder::new(X86Mode::Mode64, make_subtarget(X86Mode::Mode64))
            .encode_function(&mf);
        assert!(bytes.is_empty());
    }
}