imxrt-ral 0.6.2

#[doc = "IOMUXC_AON"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_00 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_00: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_01 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_01: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_02 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_02: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_03 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_03: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_04 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_04: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_05 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_05: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_06 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_06: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_07 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_07: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_08 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_08: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_09 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_09: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_10 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_10: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_11 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_11: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_12 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_12: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_13 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_13: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_14 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_14: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_15 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_15: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_16 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_16: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_17 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_17: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_18 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_18: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_19 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_19: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_20 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_20: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_21 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_21: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_22 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_22: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_23 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_23: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_24 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_24: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_25 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_25: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_26 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_26: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_27 SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_27: crate::RWRegister<u32>,
    #[doc = "SW_MUX_CTL_PAD_GPIO_AON_28_DUMMY SW MUX Control Register"]
    pub SW_MUX_CTL_PAD_GPIO_AON_28: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_00 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_00: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_01 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_01: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_02 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_02: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_03 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_03: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_04 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_04: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_05 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_05: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_06 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_06: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_07 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_07: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_08 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_08: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_09 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_09: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_10 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_10: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_11 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_11: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_12 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_12: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_13 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_13: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_14 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_14: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_15 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_15: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_16 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_16: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_17 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_17: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_18 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_18: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_19 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_19: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_20 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_20: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_21 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_21: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_22 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_22: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_23 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_23: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_24 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_24: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_25 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_25: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_26 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_26: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_27 SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_27: crate::RWRegister<u32>,
    #[doc = "SW_PAD_CTL_PAD_GPIO_AON_28_DUMMY SW PAD Control Register"]
    pub SW_PAD_CTL_PAD_GPIO_AON_28: crate::RWRegister<u32>,
    #[doc = "I3C1_PIN_SCL_IN_SELECT_INPUT DAISY Register"]
    pub I3C1_PIN_SCL_IN_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "I3C1_PIN_SDA_IN_SELECT_INPUT DAISY Register"]
    pub I3C1_PIN_SDA_IN_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
    pub LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
    pub LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
    pub LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
    pub LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
    pub LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0: crate::RWRegister<u32>,
    #[doc = "LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 DAISY Register"]
    pub LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_1: crate::RWRegister<u32>,
    #[doc = "LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
    pub LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
    pub LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
    pub LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_1: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_3: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
    pub LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_1 DAISY Register"]
    pub LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_1: crate::RWRegister<u32>,
    #[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_2 DAISY Register"]
    pub LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_2: crate::RWRegister<u32>,
    #[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_3 DAISY Register"]
    pub LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_3: crate::RWRegister<u32>,
    #[doc = "LPUART1_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
    pub LPUART1_IPP_IND_LPUART_CTS_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART1_IPP_IND_LPUART_DCD_N_SELECT_INPUT DAISY Register"]
    pub LPUART1_IPP_IND_LPUART_DCD_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART1_IPP_IND_LPUART_DSR_N_SELECT_INPUT DAISY Register"]
    pub LPUART1_IPP_IND_LPUART_DSR_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART12_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
    pub LPUART12_IPP_IND_LPUART_CTS_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
    pub LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
    pub LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART2_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
    pub LPUART2_IPP_IND_LPUART_CTS_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
    pub LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
    pub LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART7_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
    pub LPUART7_IPP_IND_LPUART_CTS_N_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
    pub LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
    pub LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register"]
    pub SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
    pub SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
    pub SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 DAISY Register"]
    pub SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
    pub SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
    pub SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
    #[doc = "SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
    pub SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_00 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_00 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src"]
            pub const ALT0_SRC_BOOT_MODE0: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: CAN1_TX of instance: can1"]
            pub const ALT1_CAN1_TX: u32 = 0x01;
            #[doc = "Select mux mode: ALT4 mux port: LPTMR1_ALT1 of instance: lptmr1"]
            pub const ALT4_LPTMR1_ALT1: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1"]
            pub const ALT5_GPIO1_IO0: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART2_TX of instance: lpuart2"]
            pub const ALT6_LPUART2_TX: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: TPM1_EXTCLK of instance: tpm1"]
            pub const ALT8_TPM1_EXTCLK: u32 = 0x08;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_00"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_01 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_01 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src"]
            pub const ALT0_SRC_BOOT_MODE1: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: CAN1_RX of instance: can1"]
            pub const ALT1_CAN1_RX: u32 = 0x01;
            #[doc = "Select mux mode: ALT4 mux port: LPTMR1_ALT2 of instance: lptmr1"]
            pub const ALT4_LPTMR1_ALT2: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1"]
            pub const ALT5_GPIO1_IO1: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART2_RX of instance: lpuart2"]
            pub const ALT6_LPUART2_RX: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: TPM1_CH00 of instance: tpm1"]
            pub const ALT8_TPM1_CH0: u32 = 0x08;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_01"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_02 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_02 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE02 of instance: src"]
            pub const ALT0_SRC_BOOT_MODE2: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: CAN3_TX of instance: can3"]
            pub const ALT1_CAN3_TX: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: lpspi2"]
            pub const ALT2_LPSPI2_PCS3: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPSPI2_SDO of instance: lpspi2"]
            pub const ALT3_LPSPI2_SDO: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPTMR1_ALT3 of instance: lptmr1"]
            pub const ALT4_LPTMR1_ALT3: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1"]
            pub const ALT5_GPIO1_IO2: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART2_RTS_B of instance: lpuart2"]
            pub const ALT6_LPUART2_RTS_B: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: TPM1_CH01 of instance: tpm1"]
            pub const ALT8_TPM1_CH1: u32 = 0x08;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_CLK_ECAT_CLK25 of instance: ecat"]
            pub const ALT12_ECAT_CLK_ECAT_CLK25: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_02"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_03 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_03 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT1 mux port: CAN3_RX of instance: can3"]
            pub const ALT1_CAN3_RX: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPSPI1_PCS1 of instance: lpspi1"]
            pub const ALT2_LPSPI1_PCS1: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPSPI2_SDI of instance: lpspi2"]
            pub const ALT3_LPSPI2_SDI: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPSPI1_PCS3 of instance: lpspi1"]
            pub const ALT4_LPSPI1_PCS3: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1"]
            pub const ALT5_GPIO1_IO3: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART2_CTS_B of instance: lpuart2"]
            pub const ALT6_LPUART2_CTS_B: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: TPM1_CH02 of instance: tpm1"]
            pub const ALT8_TPM1_CH2: u32 = 0x08;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_LED_STATE_RUN of instance: ecat"]
            pub const ALT12_ECAT_LED_STATE_RUN: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_03"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_04 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_04 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: lpspi1"]
            pub const ALT0_LPSPI1_SCK: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_TX_DATA00 of instance: sai1"]
            pub const ALT2_SAI1_TX_DATA0: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_DATA01 of instance: sai1"]
            pub const ALT3_SAI1_RX_DATA1: u32 = 0x03;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1"]
            pub const ALT5_GPIO1_IO4: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART7_CTS_B of instance: lpuart7"]
            pub const ALT6_LPUART7_CTS_B: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: TPM1_CH03 of instance: tpm1"]
            pub const ALT8_TPM1_CH3: u32 = 0x08;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_LED_RUN of instance: ecat"]
            pub const ALT12_ECAT_LED_RUN: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_04"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_05 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_05 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: lpspi1"]
            pub const ALT0_LPSPI1_PCS0: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_TX_SYNC of instance: sai1"]
            pub const ALT2_SAI1_TX_SYNC: u32 = 0x02;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1"]
            pub const ALT5_GPIO1_IO5: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPUART7_RTS_B of instance: lpuart7"]
            pub const ALT6_LPUART7_RTS_B: u32 = 0x06;
            #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"]
            pub const ALT7_NMI_GLUE_NMI: u32 = 0x07;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_LED_ERR of instance: ecat"]
            pub const ALT12_ECAT_LED_ERR: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_05"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_06 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_06 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SDO of instance: lpspi1"]
            pub const ALT0_LPSPI1_SDO: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: I3C1_PUR of instance: i3c1"]
            pub const ALT1_I3C1_PUR: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_TX_BCLK of instance: sai1"]
            pub const ALT2_SAI1_TX_BCLK: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1"]
            pub const ALT3_LPI2C1_SDA: u32 = 0x03;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1"]
            pub const ALT5_GPIO1_IO6: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN1_TX of instance: can1"]
            pub const ALT6_CAN1_TX: u32 = 0x06;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_SDA of instance: ecat"]
            pub const ALT12_ECAT_SDA: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_06"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_07 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_07 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPSPI1_SDI of instance: lpspi1"]
            pub const ALT0_LPSPI1_SDI: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_MCLK of instance: sai1"]
            pub const ALT2_SAI1_MCLK: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1"]
            pub const ALT3_LPI2C1_SCL: u32 = 0x03;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1"]
            pub const ALT5_GPIO1_IO7: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN1_RX of instance: can1"]
            pub const ALT6_CAN1_RX: u32 = 0x06;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_SCL of instance: ecat"]
            pub const ALT12_ECAT_SCL: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_07"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_08 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_08 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPUART1_TX of instance: lpuart1"]
            pub const ALT0_LPUART1_TX: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: S400_TX of instance: s400"]
            pub const ALT1_S400_TX: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_RX_DATA00 of instance: sai1"]
            pub const ALT2_SAI1_RX_DATA0: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1"]
            pub const ALT3_SAI1_TX_DATA1: u32 = 0x03;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1"]
            pub const ALT5_GPIO1_IO8: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPI2C1_SDA of instance: lpi2c1"]
            pub const ALT6_LPI2C1_SDA: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_PCS1 of instance: lpspi1"]
            pub const ALT8_LPSPI1_PCS1: u32 = 0x08;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_LINK_ACT00 of instance: ecat"]
            pub const ALT12_ECAT_LINK_ACT0: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_08"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_09 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_09 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: LPUART1_RX of instance: lpuart1"]
            pub const ALT0_LPUART1_RX: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: S400_RX of instance: s400"]
            pub const ALT1_S400_RX: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_RX_BCLK of instance: sai1"]
            pub const ALT2_SAI1_RX_BCLK: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPIT1_TRIGGER00 of instance: lpit1"]
            pub const ALT3_LPIT1_TRIGGER0: u32 = 0x03;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1"]
            pub const ALT5_GPIO1_IO9: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPI2C1_SCL of instance: lpi2c1"]
            pub const ALT6_LPI2C1_SCL: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_PCS2 of instance: lpspi1"]
            pub const ALT8_LPSPI1_PCS2: u32 = 0x08;
            #[doc = "Select mux mode: ALT12 mux port: ECAT_LINK_ACT01 of instance: ecat"]
            pub const ALT12_ECAT_LINK_ACT1: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_09"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_10 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_10 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x07 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: jtag_mux"]
            pub const ALT0_JTAG_MUX_TRSTB: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS0: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: SAI1_RX_SYNC of instance: sai1"]
            pub const ALT2_SAI1_RX_SYNC: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPIT1_TRIGGER01 of instance: lpit1"]
            pub const ALT3_LPIT1_TRIGGER1: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: TPM2_EXTCLK of instance: tpm2"]
            pub const ALT4_TPM2_EXTCLK: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1"]
            pub const ALT5_GPIO1_IO10: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPI2C1_SCLS of instance: lpi2c1"]
            pub const ALT6_LPI2C1_SCLS: u32 = 0x06;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_10"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_11 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_11 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x07 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TDO of instance: jtag_mux"]
            pub const ALT0_JTAG_MUX_TDO: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1"]
            pub const ALT2_LPUART1_CTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPIT1_TRIGGER02 of instance: lpit1"]
            pub const ALT3_LPIT1_TRIGGER2: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: TPM2_CH00 of instance: tpm2"]
            pub const ALT4_TPM2_CH0: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1"]
            pub const ALT5_GPIO1_IO11: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPI2C1_SDAS of instance: lpi2c1"]
            pub const ALT6_LPI2C1_SDAS: u32 = 0x06;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_11"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_12 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_12 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TDI of instance: jtag_mux"]
            pub const ALT0_JTAG_MUX_TDI: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1"]
            pub const ALT2_LPUART1_RTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPIT1_TRIGGER03 of instance: lpit1"]
            pub const ALT3_LPIT1_TRIGGER3: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: TPM2_CH01 of instance: tpm2"]
            pub const ALT4_TPM2_CH1: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1"]
            pub const ALT5_GPIO1_IO12: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: lpi2c1"]
            pub const ALT6_LPI2C1_HREQ: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: lpspi1"]
            pub const ALT8_LPSPI1_SCK: u32 = 0x08;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_12"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_13 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_13 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: jtag_mux"]
            pub const ALT0_JTAG_MUX_TCK: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: LPUART12_CTS_B of instance: lpuart12"]
            pub const ALT2_LPUART12_CTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART1_DSR_B of instance: lpuart1"]
            pub const ALT3_LPUART1_DSR_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: TPM2_CH02 of instance: tpm2"]
            pub const ALT4_TPM2_CH2: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1"]
            pub const ALT5_GPIO1_IO13: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPTMR1_ALT1 of instance: lptmr1"]
            pub const ALT6_LPTMR1_ALT1: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_PCS0 of instance: lpspi1"]
            pub const ALT8_LPSPI1_PCS0: u32 = 0x08;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_13"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_14 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_14 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: jtag_mux"]
            pub const ALT0_JTAG_MUX_TMS: u32 = 0;
            #[doc = "Select mux mode: ALT2 mux port: LPUART12_RTS_B of instance: lpuart12"]
            pub const ALT2_LPUART12_RTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART1_DCD_B of instance: lpuart1"]
            pub const ALT3_LPUART1_DCD_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: TPM2_CH03 of instance: tpm2"]
            pub const ALT4_TPM2_CH3: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1"]
            pub const ALT5_GPIO1_IO14: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPTMR1_ALT2 of instance: lptmr1"]
            pub const ALT6_LPTMR1_ALT2: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_SDO of instance: lpspi1"]
            pub const ALT8_LPSPI1_SDO: u32 = 0x08;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_14"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_15 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_15 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_DATA03 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_DATA3: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS1: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART12_TX of instance: lpuart12"]
            pub const ALT2_LPUART12_TX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART1_RI_B of instance: lpuart1"]
            pub const ALT3_LPUART1_RI_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPI2C2_SDA of instance: lpi2c2"]
            pub const ALT4_LPI2C2_SDA: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1"]
            pub const ALT5_GPIO1_IO15: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPTMR1_ALT3 of instance: lptmr1"]
            pub const ALT6_LPTMR1_ALT3: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPSPI1_SDI of instance: lpspi1"]
            pub const ALT8_LPSPI1_SDI: u32 = 0x08;
            #[doc = "Select mux mode: ALT9 mux port: I3C1_SDA of instance: i3c1"]
            pub const ALT9_I3C1_SDA: u32 = 0x09;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_15"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_16 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_16 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_DATA02 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_DATA2: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS0: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART12_RX of instance: lpuart12"]
            pub const ALT2_LPUART12_RX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART1_DTR_B of instance: lpuart1"]
            pub const ALT3_LPUART1_DTR_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPI2C2_SCL of instance: lpi2c2"]
            pub const ALT4_LPI2C2_SCL: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1"]
            pub const ALT5_GPIO1_IO16: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN1_TX of instance: can1"]
            pub const ALT6_CAN1_TX: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPUART7_CTS_B of instance: lpuart7"]
            pub const ALT8_LPUART7_CTS_B: u32 = 0x08;
            #[doc = "Select mux mode: ALT9 mux port: I3C1_SCL of instance: i3c1"]
            pub const ALT9_I3C1_SCL: u32 = 0x09;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_16"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_17 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_17 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_DATA01 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_DATA1: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SDI of instance: lpspi2"]
            pub const ALT1_LPSPI2_SDI: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7"]
            pub const ALT2_LPUART7_TX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2"]
            pub const ALT3_LPI2C2_SDA: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPUART1_DSR_B of instance: lpuart1"]
            pub const ALT4_LPUART1_DSR_B: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1"]
            pub const ALT5_GPIO1_IO17: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN1_RX of instance: can1"]
            pub const ALT6_CAN1_RX: u32 = 0x06;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_17"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_18 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_18 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_DATA00 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_DATA0: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SDO of instance: lpspi2"]
            pub const ALT1_LPSPI2_SDO: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"]
            pub const ALT2_LPUART7_RX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2"]
            pub const ALT3_LPI2C2_SCL: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPUART1_DCD_B of instance: lpuart1"]
            pub const ALT4_LPUART1_DCD_B: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1"]
            pub const ALT5_GPIO1_IO18: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN3_TX of instance: can3"]
            pub const ALT6_CAN3_TX: u32 = 0x06;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_18"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_19 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_19 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_SCLK of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_SCLK: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: lpspi2"]
            pub const ALT1_LPSPI2_SCK: u32 = 0x01;
            #[doc = "Select mux mode: ALT3 mux port: FLEXSPI2_BUS2BIT_A_SS1_B of instance: flexspi2_bus2bit"]
            pub const ALT3_FLEXSPI2_BUS2BIT_A_SS1_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPUART1_CTS_B of instance: lpuart1"]
            pub const ALT4_LPUART1_CTS_B: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1"]
            pub const ALT5_GPIO1_IO19: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: CAN3_RX of instance: can3"]
            pub const ALT6_CAN3_RX: u32 = 0x06;
            #[doc = "Select mux mode: ALT8 mux port: LPUART7_RTS_B of instance: lpuart7"]
            pub const ALT8_LPUART7_RTS_B: u32 = 0x08;
            #[doc = "Select mux mode: ALT9 mux port: LPUART12_TX of instance: lpuart12"]
            pub const ALT9_LPUART12_TX: u32 = 0x09;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D00 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D0: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_19"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_20 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_20 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_DQS of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_DQS: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: FLEXSPI2_BUS2BIT_A_SS1_B of instance: flexspi2_bus2bit"]
            pub const ALT1_FLEXSPI2_BUS2BIT_A_SS1_B: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPI2C1_SDA of instance: lpi2c1"]
            pub const ALT2_LPI2C1_SDA: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: I3C1_SDA of instance: i3c1"]
            pub const ALT3_I3C1_SDA: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: LPUART1_RTS_B of instance: lpuart1"]
            pub const ALT4_LPUART1_RTS_B: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1"]
            pub const ALT5_GPIO1_IO20: u32 = 0x05;
            #[doc = "Select mux mode: ALT9 mux port: LPUART12_RX of instance: lpuart12"]
            pub const ALT9_LPUART12_RX: u32 = 0x09;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D01 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D1: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_20"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_21 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_21 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_B_SS0_B of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_B_SS0_B: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS1 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS1: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1"]
            pub const ALT2_LPI2C1_SCL: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: I3C1_SCL of instance: i3c1"]
            pub const ALT3_I3C1_SCL: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_TX_DATA00 of instance: sai1"]
            pub const ALT4_SAI1_TX_DATA0: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1"]
            pub const ALT5_GPIO1_IO21: u32 = 0x05;
            #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_BUS2BIT_A_DQS of instance: flexspi2_bus2bit"]
            pub const ALT8_FLEXSPI2_BUS2BIT_A_DQS: u32 = 0x08;
            #[doc = "Select mux mode: ALT9 mux port: SAI1_RX_DATA01 of instance: sai1"]
            pub const ALT9_SAI1_RX_DATA1: u32 = 0x09;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D02 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D2: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_21"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_22 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_22 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_SS0_B of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_SS0_B: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPI2C2_SDA of instance: lpi2c2"]
            pub const ALT1_LPI2C2_SDA: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7"]
            pub const ALT2_LPUART7_TX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART12_CTS_B of instance: lpuart12"]
            pub const ALT3_LPUART12_CTS_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_TX_SYNC of instance: sai1"]
            pub const ALT4_SAI1_TX_SYNC: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1"]
            pub const ALT5_GPIO1_IO22: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPSPI2_SCK of instance: lpspi2"]
            pub const ALT6_LPSPI2_SCK: u32 = 0x06;
            #[doc = "Select mux mode: ALT10 mux port: CCMSRCGPC_CCMOBS1 of instance: ccmsrcgpc"]
            pub const ALT10_CCMSRCGPCMIX_CCMOBS1: u32 = 0x0a;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D03 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D3: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_22"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_23 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_23 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_SCLK of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_SCLK: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPI2C2_SCL of instance: lpi2c2"]
            pub const ALT1_LPI2C2_SCL: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"]
            pub const ALT2_LPUART7_RX: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART12_RTS_B of instance: lpuart12"]
            pub const ALT3_LPUART12_RTS_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_TX_BCLK of instance: sai1"]
            pub const ALT4_SAI1_TX_BCLK: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1"]
            pub const ALT5_GPIO1_IO23: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPSPI2_SDO of instance: lpspi2"]
            pub const ALT6_LPSPI2_SDO: u32 = 0x06;
            #[doc = "Select mux mode: ALT10 mux port: CCMSRCGPC_CCMOBS2 of instance: ccmsrcgpc"]
            pub const ALT10_CCMSRCGPCMIX_CCMOBS2: u32 = 0x0a;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D04 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D4: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_23"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_24 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_24 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_DATA00 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_DATA0: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: lpi2c1"]
            pub const ALT1_LPI2C1_SDA: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2"]
            pub const ALT2_LPUART2_RTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART7_CTS_B of instance: lpuart7"]
            pub const ALT3_LPUART7_CTS_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_MCLK of instance: sai1"]
            pub const ALT4_SAI1_MCLK: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1"]
            pub const ALT5_GPIO1_IO24: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPSPI2_SDI of instance: lpspi2"]
            pub const ALT6_LPSPI2_SDI: u32 = 0x06;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D05 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D5: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_24"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_25 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_25 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_DATA01 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_DATA1: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: lpi2c1"]
            pub const ALT1_LPI2C1_SCL: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2"]
            pub const ALT2_LPUART2_CTS_B: u32 = 0x02;
            #[doc = "Select mux mode: ALT3 mux port: LPUART7_RTS_B of instance: lpuart7"]
            pub const ALT3_LPUART7_RTS_B: u32 = 0x03;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_RX_DATA00 of instance: sai1"]
            pub const ALT4_SAI1_RX_DATA0: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1"]
            pub const ALT5_GPIO1_IO25: u32 = 0x05;
            #[doc = "Select mux mode: ALT6 mux port: LPSPI2_PCS0 of instance: lpspi2"]
            pub const ALT6_LPSPI2_PCS0: u32 = 0x06;
            #[doc = "Select mux mode: ALT7 mux port: SAI1_TX_DATA01 of instance: sai1"]
            pub const ALT7_SAI1_TX_DATA1: u32 = 0x07;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D06 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D6: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_25"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_26 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_26 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_DATA02 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_DATA2: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS2 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS2: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"]
            pub const ALT2_LPUART2_TX: u32 = 0x02;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_RX_BCLK of instance: sai1"]
            pub const ALT4_SAI1_RX_BCLK: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1"]
            pub const ALT5_GPIO1_IO26: u32 = 0x05;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_D07 of instance: adc1"]
            pub const ALT12_ADC1_CONV_D7: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_26"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_27 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_27 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_DATA03 of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_DATA3: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: LPSPI2_PCS3 of instance: lpspi2"]
            pub const ALT1_LPSPI2_PCS3: u32 = 0x01;
            #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"]
            pub const ALT2_LPUART2_RX: u32 = 0x02;
            #[doc = "Select mux mode: ALT4 mux port: SAI1_RX_SYNC of instance: sai1"]
            pub const ALT4_SAI1_RX_SYNC: u32 = 0x04;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1"]
            pub const ALT5_GPIO1_IO27: u32 = 0x05;
            #[doc = "Select mux mode: ALT7 mux port: EWM_EWM_OUT_B of instance: ewm"]
            pub const ALT7_EWM_EWM_OUT_B: u32 = 0x07;
            #[doc = "Select mux mode: ALT12 mux port: ADC1_CONV_RDY_CLK of instance: adc1"]
            pub const ALT12_ADC1_CONV_RDY_CLK: u32 = 0x0c;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_27"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_MUX_CTL_PAD_GPIO_AON_28_DUMMY SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_AON_28 {
    #[doc = "MUX Mode Select Field."]
    pub mod MUX_MODE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x07 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_BUS2BIT_A_DQS of instance: flexspi2_bus2bit"]
            pub const ALT0_FLEXSPI2_BUS2BIT_A_DQS: u32 = 0;
            #[doc = "Select mux mode: ALT1 mux port: FLEXSPI2_BUS2BIT_B_DQS of instance: flexspi2_bus2bit"]
            pub const ALT1_FLEXSPI2_BUS2BIT_B_DQS: u32 = 0x01;
            #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1"]
            pub const ALT5_GPIO1_IO28: u32 = 0x05;
        }
    }
    #[doc = "Software Input On Field."]
    pub mod SION {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Input Path is determined by functionality"]
            pub const DISABLED: u32 = 0;
            #[doc = "Force input path of pad GPIO_AON_28_DUMMY"]
            pub const ENABLED: u32 = 0x01;
        }
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_00 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_00 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_01 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_01 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_02 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_02 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_03 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_03 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_04 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_04 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_05 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_05 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_06 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_06 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_07 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_07 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_08 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_08 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_09 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_09 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_10 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_10 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_11 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_11 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_12 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_12 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_13 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_13 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_14 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_14 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_15 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_15 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_16 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_16 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_17 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_17 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_18 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_18 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_19 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_19 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_20 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_20 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_21 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_21 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_22 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_22 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_23 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_23 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_24 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_24 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_25 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_25 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_26 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_26 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_27 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_27 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "SW_PAD_CTL_PAD_GPIO_AON_28_DUMMY SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_AON_28 {
    #[doc = "Slew Rate Field"]
    pub mod SRE {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Fast Slew Rate"]
            pub const SRE_0_FAST_SLEW_RATE: u32 = 0;
            #[doc = "Slow Slew Rate"]
            pub const SRE_1_SLOW_SLEW_RATE: u32 = 0x01;
        }
    }
    #[doc = "Drive Strength Field"]
    pub mod DSE {
        pub const offset: u32 = 1;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "normal driver"]
            pub const DSE_0_NORMAL_DRIVER: u32 = 0;
            #[doc = "high driver"]
            pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
        }
    }
    #[doc = "Pull / Keep Select Field"]
    pub mod PUE {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Pull Disable, Highz"]
            pub const PUE_0_PULL_DISABLE__HIGHZ: u32 = 0;
            #[doc = "Pull Enable"]
            pub const PUE_1_PULL_ENABLE: u32 = 0x01;
        }
    }
    #[doc = "Pull Up / Down Config. Field"]
    pub mod PUS {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Weak pull down"]
            pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
            #[doc = "Weak pull up"]
            pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
        }
    }
    #[doc = "Open Drain Field"]
    pub mod ODE {
        pub const offset: u32 = 4;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Disabled"]
            pub const ODE_0_DISABLED: u32 = 0;
            #[doc = "Enabled"]
            pub const ODE_1_ENABLED: u32 = 0x01;
        }
    }
    #[doc = "Domain write protection"]
    pub mod DWP {
        pub const offset: u32 = 24;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
    #[doc = "Domain write protection lock"]
    pub mod DWP_LOCK {
        pub const offset: u32 = 28;
        pub const mask: u32 = 0x0f << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "I3C1_PIN_SCL_IN_SELECT_INPUT DAISY Register"]
pub mod I3C1_PIN_SCL_IN_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_16 for Mode: ALT9"]
            pub const SELECT_GPIO_AON_16_ALT9: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_21 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_21_ALT3: u32 = 0x01;
        }
    }
}
#[doc = "I3C1_PIN_SDA_IN_SELECT_INPUT DAISY Register"]
pub mod I3C1_PIN_SDA_IN_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT9"]
            pub const SELECT_GPIO_AON_15_ALT9: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_20 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_20_ALT3: u32 = 0x01;
        }
    }
}
#[doc = "LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub mod LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_07 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_07_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_09 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_09_ALT6: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_21 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_21_ALT2: u32 = 0x02;
            #[doc = "Selecting Pad: GPIO_AON_25 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_25_ALT1: u32 = 0x03;
        }
    }
}
#[doc = "LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub mod LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_06 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_06_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_08 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_08_ALT6: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_20 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_20_ALT2: u32 = 0x02;
            #[doc = "Selecting Pad: GPIO_AON_24 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_24_ALT1: u32 = 0x03;
        }
    }
}
#[doc = "LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub mod LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_16 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_16_ALT4: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_18 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_18_ALT3: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_23 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_23_ALT1: u32 = 0x02;
        }
    }
}
#[doc = "LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub mod LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_15_ALT4: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_17 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_17_ALT3: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_22 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_22_ALT1: u32 = 0x02;
        }
    }
}
#[doc = "LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
pub mod LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_05 for Mode: ALT0"]
            pub const SELECT_GPIO_AON_05_ALT0: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_13 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_13_ALT8: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 DAISY Register"]
pub mod LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_03 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_03_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_08 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_08_ALT8: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
pub mod LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_04 for Mode: ALT0"]
            pub const SELECT_GPIO_AON_04_ALT0: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_12 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_12_ALT8: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
pub mod LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_07 for Mode: ALT0"]
            pub const SELECT_GPIO_AON_07_ALT0: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_15_ALT8: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
pub mod LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_06 for Mode: ALT0"]
            pub const SELECT_GPIO_AON_06_ALT0: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_14 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_14_ALT8: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_10 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_10_ALT1: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_16 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_16_ALT1: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_25 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_25_ALT6: u32 = 0x02;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_15_ALT1: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_21 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_21_ALT1: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_3 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_02 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_02_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_27 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_27_ALT1: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_19 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_19_ALT1: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_22 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_22_ALT6: u32 = 0x01;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_03 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_03_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_17 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_17_ALT1: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_24 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_24_ALT6: u32 = 0x02;
        }
    }
}
#[doc = "LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
pub mod LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_02 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_02_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_18 for Mode: ALT1"]
            pub const SELECT_GPIO_AON_18_ALT1: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_23 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_23_ALT6: u32 = 0x02;
        }
    }
}
#[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_1 DAISY Register"]
pub mod LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_1 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_00 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_00_ALT4: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_13 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_13_ALT6: u32 = 0x01;
        }
    }
}
#[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_2 DAISY Register"]
pub mod LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_2 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_01 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_01_ALT4: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_14 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_14_ALT6: u32 = 0x01;
        }
    }
}
#[doc = "LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_3 DAISY Register"]
pub mod LPTMR1_IPP_IND_LPTIMER_SELECT_INPUT_3 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_02 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_02_ALT4: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_15_ALT6: u32 = 0x01;
        }
    }
}
#[doc = "LPUART1_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
pub mod LPUART1_IPP_IND_LPUART_CTS_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_11 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_11_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_19 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_19_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "LPUART1_IPP_IND_LPUART_DCD_N_SELECT_INPUT DAISY Register"]
pub mod LPUART1_IPP_IND_LPUART_DCD_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_14 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_14_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_18 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_18_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "LPUART1_IPP_IND_LPUART_DSR_N_SELECT_INPUT DAISY Register"]
pub mod LPUART1_IPP_IND_LPUART_DSR_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_13 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_13_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_17 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_17_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "LPUART12_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
pub mod LPUART12_IPP_IND_LPUART_CTS_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_13 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_13_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_22 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_22_ALT3: u32 = 0x01;
        }
    }
}
#[doc = "LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub mod LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_16 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_16_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_20 for Mode: ALT9"]
            pub const SELECT_GPIO_AON_20_ALT9: u32 = 0x01;
        }
    }
}
#[doc = "LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub mod LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_15 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_15_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_19 for Mode: ALT9"]
            pub const SELECT_GPIO_AON_19_ALT9: u32 = 0x01;
        }
    }
}
#[doc = "LPUART2_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
pub mod LPUART2_IPP_IND_LPUART_CTS_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_03 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_03_ALT6: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_25 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_25_ALT2: u32 = 0x01;
        }
    }
}
#[doc = "LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub mod LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_01 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_01_ALT6: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_27 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_27_ALT2: u32 = 0x01;
        }
    }
}
#[doc = "LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub mod LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_00 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_00_ALT6: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_26 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_26_ALT2: u32 = 0x01;
        }
    }
}
#[doc = "LPUART7_IPP_IND_LPUART_CTS_N_SELECT_INPUT DAISY Register"]
pub mod LPUART7_IPP_IND_LPUART_CTS_N_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x03 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_04 for Mode: ALT6"]
            pub const SELECT_GPIO_AON_04_ALT6: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_16 for Mode: ALT8"]
            pub const SELECT_GPIO_AON_16_ALT8: u32 = 0x01;
            #[doc = "Selecting Pad: GPIO_AON_24 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_24_ALT3: u32 = 0x02;
        }
    }
}
#[doc = "LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub mod LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_18 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_18_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_23 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_23_ALT2: u32 = 0x01;
        }
    }
}
#[doc = "LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub mod LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_17 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_17_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_22 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_22_ALT2: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register"]
pub mod SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_07 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_07_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_24 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_24_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
pub mod SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_09 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_09_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_26 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_26_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
pub mod SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_08 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_08_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_25 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_25_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 DAISY Register"]
pub mod SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_04 for Mode: ALT3"]
            pub const SELECT_GPIO_AON_04_ALT3: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_21 for Mode: ALT9"]
            pub const SELECT_GPIO_AON_21_ALT9: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
pub mod SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_10 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_10_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_27 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_27_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
pub mod SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_06 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_06_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_23 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_23_ALT4: u32 = 0x01;
        }
    }
}
#[doc = "SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
pub mod SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT {
    #[doc = "Selecting Pads Involved in Daisy Chain."]
    pub mod DAISY {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "Selecting Pad: GPIO_AON_05 for Mode: ALT2"]
            pub const SELECT_GPIO_AON_05_ALT2: u32 = 0;
            #[doc = "Selecting Pad: GPIO_AON_22 for Mode: ALT4"]
            pub const SELECT_GPIO_AON_22_ALT4: u32 = 0x01;
        }
    }
}