imxrt-ral 0.6.2

Register access layer for all NXP i.MX RT microcontrollers
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108

#[doc = "SRAM Registers"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "no description available"]
    pub DESC: [desc::RegisterBlock; 1024usize],
}
pub mod desc {
    #[doc = "no description available"]
    #[repr(C)]
    pub struct RegisterBlock {
        #[doc = "Description Address Register"]
        pub SRAM0_: crate::RWRegister<u32>,
        #[doc = "Description Data Register"]
        pub SRAM1_: crate::RWRegister<u32>,
        #[doc = "Description Control Register"]
        pub SRAM2_: crate::RWRegister<u32>,
        _reserved0: [u8; 0x04],
    }
    #[doc = "Description Address Register"]
    pub mod SRAM0_ {
        #[doc = "Address field"]
        pub mod ADDR {
            pub const offset: u32 = 0;
            pub const mask: u32 = 0xffff_ffff << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {}
        }
    }
    #[doc = "Description Data Register"]
    pub mod SRAM1_ {
        #[doc = "Data field"]
        pub mod DATA {
            pub const offset: u32 = 0;
            pub const mask: u32 = 0xffff_ffff << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {}
        }
    }
    #[doc = "Description Control Register"]
    pub mod SRAM2_ {
        #[doc = "Type field"]
        pub mod TYPE {
            pub const offset: u32 = 0;
            pub const mask: u32 = 0x07 << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {
                #[doc = "SR"]
                pub const SR: u32 = 0;
                #[doc = "WO"]
                pub const WO: u32 = 0x01;
                #[doc = "RMW_OR"]
                pub const RMW_OR: u32 = 0x02;
                #[doc = "RMW_AND"]
                pub const RMW_AND: u32 = 0x03;
                #[doc = "DELAY"]
                pub const DELAY: u32 = 0x04;
                #[doc = "POLLING_0"]
                pub const POLLING_0: u32 = 0x05;
                #[doc = "POLLING_1"]
                pub const POLLING_1: u32 = 0x06;
            }
        }
        #[doc = "Save Enable"]
        pub mod SV_EN {
            pub const offset: u32 = 4;
            pub const mask: u32 = 0x01 << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {
                #[doc = "Do not use this descriptor in the save operation"]
                pub const SV_EN_0: u32 = 0;
                #[doc = "Use this descriptor in the save operation"]
                pub const SV_EN_1: u32 = 0x01;
            }
        }
        #[doc = "Restore Enable"]
        pub mod RT_EN {
            pub const offset: u32 = 5;
            pub const mask: u32 = 0x01 << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {
                #[doc = "Do not use this descriptor for the restore operation"]
                pub const RT_EN_0: u32 = 0;
                #[doc = "Use this descriptor for the restore operation"]
                pub const RT_EN_1: u32 = 0x01;
            }
        }
        #[doc = "Size field"]
        pub mod SIZE {
            pub const offset: u32 = 6;
            pub const mask: u32 = 0x03 << offset;
            pub mod R {}
            pub mod W {}
            pub mod RW {
                #[doc = "8-bit"]
                pub const SIZE_0: u32 = 0;
                #[doc = "16-bit"]
                pub const SIZE_1: u32 = 0x01;
                #[doc = "32-bit"]
                pub const SIZE_2: u32 = 0x02;
            }
        }
    }
}