#[doc = "IOMUXC LPSR"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_00: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_01 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_01: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_02 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_02: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_03 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_03: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_04 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_04: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_05 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_05: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_06 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_06: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_07 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_07: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_08 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_08: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_09 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_09: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_10 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_10: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_11 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_11: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_12 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_12: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_13 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_13: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_14 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_14: crate::RWRegister<u32>,
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register"]
pub SW_MUX_CTL_PAD_GPIO_LPSR_15: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_00: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_01 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_01: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_02 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_02: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_03 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_03: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_04 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_04: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_05 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_05: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_06 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_06: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_07 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_07: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_08 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_08: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_09 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_09: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_10 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_10: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_11 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_11: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_12 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_12: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_13 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_13: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_14 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_14: crate::RWRegister<u32>,
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register"]
pub SW_PAD_CTL_PAD_GPIO_LPSR_15: crate::RWRegister<u32>,
#[doc = "CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register"]
pub CAN3_IPP_IND_CANRX_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
pub LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0: crate::RWRegister<u32>,
#[doc = "LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
pub LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
pub LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
pub LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register"]
pub MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0: crate::RWRegister<u32>,
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 DAISY Register"]
pub MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1: crate::RWRegister<u32>,
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 DAISY Register"]
pub MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2: crate::RWRegister<u32>,
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 DAISY Register"]
pub MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3: crate::RWRegister<u32>,
#[doc = "NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register"]
pub NMI_GLUE_IPP_IND_NMI_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register"]
pub SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
pub SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
pub SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0: crate::RWRegister<u32>,
#[doc = "SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
pub SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
pub SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
#[doc = "SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
pub SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_00 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: FLEXCAN3_TX of instance: FLEXCAN3"]
pub const ALT0_CAN3_TX: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: MIC_CLK of instance: MIC"]
pub const ALT1_MIC_CLK: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS"]
pub const ALT2_MQS_RIGHT: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: ARM_CM4_EVENTO of instance: CM4"]
pub const ALT3_ARM_CM4_EVENTO: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO00 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO0: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPUART12_TXD of instance: LPUART12"]
pub const ALT6_LPUART12_TX: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: SAI4_MCLK of instance: SAI4"]
pub const ALT7_SAI4_MCLK: u32 = 0x07;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO00 of instance: GPIO12"]
pub const ALT10_GPIO12_IO0: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_00"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_01 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_01 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: FLEXCAN3_RX of instance: FLEXCAN3"]
pub const ALT0_CAN3_RX: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: MIC_BITSTREAM0 of instance: MIC"]
pub const ALT1_MIC_BITSTREAM0: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS"]
pub const ALT2_MQS_LEFT: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: ARM_CM4_EVENTI of instance: CM4"]
pub const ALT3_ARM_CM4_EVENTI: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO01 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO1: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPUART12_RXD of instance: LPUART12"]
pub const ALT6_LPUART12_RX: u32 = 0x06;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO01 of instance: GPIO12"]
pub const ALT10_GPIO12_IO1: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_01"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_02 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_02 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: SRC"]
pub const ALT0_SRC_BOOT_MODE0: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPSPI5_SCK of instance: LPSPI5"]
pub const ALT1_LPSPI5_SCK: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: SAI4_TX_DATA of instance: SAI4"]
pub const ALT2_SAI4_TX_DATA: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MQS_RIGHT of instance: MQS"]
pub const ALT3_MQS_RIGHT: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO02 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO2: u32 = 0x05;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO02 of instance: GPIO12"]
pub const ALT10_GPIO12_IO2: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_02"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_03 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_03 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: SRC"]
pub const ALT0_SRC_BOOT_MODE1: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPSPI5_PCS0 of instance: LPSPI5"]
pub const ALT1_LPSPI5_PCS0: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: SAI4_TX_SYNC of instance: SAI4"]
pub const ALT2_SAI4_TX_SYNC: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MQS_LEFT of instance: MQS"]
pub const ALT3_MQS_LEFT: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO03 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO3: u32 = 0x05;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO03 of instance: GPIO12"]
pub const ALT10_GPIO12_IO3: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_03"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_04 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_04 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPI2C5_SDA of instance: LPI2C5"]
pub const ALT0_LPI2C5_SDA: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPSPI5_SOUT of instance: LPSPI5"]
pub const ALT1_LPSPI5_SDO: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: SAI4_TX_BCLK of instance: SAI4"]
pub const ALT2_SAI4_TX_BCLK: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: LPUART12_RTS_B of instance: LPUART12"]
pub const ALT3_LPUART12_RTS_B: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO04 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO4: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPUART11_TXD of instance: LPUART11"]
pub const ALT6_LPUART11_TX: u32 = 0x06;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO04 of instance: GPIO12"]
pub const ALT10_GPIO12_IO4: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_04"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_05 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_05 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPI2C5_SCL of instance: LPI2C5"]
pub const ALT0_LPI2C5_SCL: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPSPI5_SIN of instance: LPSPI5"]
pub const ALT1_LPSPI5_SDI: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: SAI4_MCLK of instance: SAI4"]
pub const ALT2_SAI4_MCLK: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: LPUART12_CTS_B of instance: LPUART12"]
pub const ALT3_LPUART12_CTS_B: u32 = 0x03;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO05 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO5: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPUART11_RXD of instance: LPUART11"]
pub const ALT6_LPUART11_RX: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"]
pub const ALT7_NMI_GLUE_NMI: u32 = 0x07;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO05 of instance: GPIO12"]
pub const ALT10_GPIO12_IO5: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_05"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_06 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_06 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPI2C6_SDA of instance: LPI2C6"]
pub const ALT0_LPI2C6_SDA: u32 = 0;
#[doc = "Select mux mode: ALT2 mux port: SAI4_RX_DATA of instance: SAI4"]
pub const ALT2_SAI4_RX_DATA: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: LPUART12_TXD of instance: LPUART12"]
pub const ALT3_LPUART12_TX: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_PCS3 of instance: LPSPI6"]
pub const ALT4_LPSPI6_PCS3: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO06 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO6: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: FLEXCAN3_TX of instance: FLEXCAN3"]
pub const ALT6_CAN3_TX: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: PIT2_TRIGGER3 of instance: PIT2"]
pub const ALT7_PIT2_TRIGGER3: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_PCS1 of instance: LPSPI5"]
pub const ALT8_LPSPI5_PCS1: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO06 of instance: GPIO12"]
pub const ALT10_GPIO12_IO6: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_06"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_07 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_07 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPI2C6_SCL of instance: LPI2C6"]
pub const ALT0_LPI2C6_SCL: u32 = 0;
#[doc = "Select mux mode: ALT2 mux port: SAI4_RX_BCLK of instance: SAI4"]
pub const ALT2_SAI4_RX_BCLK: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: LPUART12_RXD of instance: LPUART12"]
pub const ALT3_LPUART12_RX: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_PCS2 of instance: LPSPI6"]
pub const ALT4_LPSPI6_PCS2: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO07 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO7: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: FLEXCAN3_RX of instance: FLEXCAN3"]
pub const ALT6_CAN3_RX: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: PIT2_TRIGGER2 of instance: PIT2"]
pub const ALT7_PIT2_TRIGGER2: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_PCS2 of instance: LPSPI5"]
pub const ALT8_LPSPI5_PCS2: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO07 of instance: GPIO12"]
pub const ALT10_GPIO12_IO7: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_07"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_08 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_08 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPUART11_TXD of instance: LPUART11"]
pub const ALT0_LPUART11_TX: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: FLEXCAN3_TX of instance: FLEXCAN3"]
pub const ALT1_CAN3_TX: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: SAI4_RX_SYNC of instance: SAI4"]
pub const ALT2_SAI4_RX_SYNC: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MIC_CLK of instance: MIC"]
pub const ALT3_MIC_CLK: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_PCS1 of instance: LPSPI6"]
pub const ALT4_LPSPI6_PCS1: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO08 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO8: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPI2C5_SDA of instance: LPI2C5"]
pub const ALT6_LPI2C5_SDA: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: PIT2_TRIGGER1 of instance: PIT2"]
pub const ALT7_PIT2_TRIGGER1: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_PCS3 of instance: LPSPI5"]
pub const ALT8_LPSPI5_PCS3: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO08 of instance: GPIO12"]
pub const ALT10_GPIO12_IO8: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_08"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_09 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_09 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: LPUART11_RXD of instance: LPUART11"]
pub const ALT0_LPUART11_RX: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: FLEXCAN3_RX of instance: FLEXCAN3"]
pub const ALT1_CAN3_RX: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: PIT2_TRIGGER0 of instance: PIT2"]
pub const ALT2_PIT2_TRIGGER0: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MIC_BITSTREAM0 of instance: MIC"]
pub const ALT3_MIC_BITSTREAM0: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_PCS0 of instance: LPSPI6"]
pub const ALT4_LPSPI6_PCS0: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO09 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO9: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPI2C5_SCL of instance: LPI2C5"]
pub const ALT6_LPI2C5_SCL: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: SAI4_TX_DATA of instance: SAI4"]
pub const ALT7_SAI4_TX_DATA: u32 = 0x07;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO09 of instance: GPIO12"]
pub const ALT10_GPIO12_IO9: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_09"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_10 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_10 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX"]
pub const ALT0_JTAG_MUX_TRSTB: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11"]
pub const ALT1_LPUART11_CTS_B: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6"]
pub const ALT2_LPI2C6_SDA: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC"]
pub const ALT3_MIC_BITSTREAM1: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6"]
pub const ALT4_LPSPI6_SCK: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO10: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5"]
pub const ALT6_LPI2C5_SCLS: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4"]
pub const ALT7_SAI4_TX_SYNC: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12"]
pub const ALT8_LPUART12_TX: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12"]
pub const ALT10_GPIO12_IO10: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_10"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_11 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_11 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TDO of instance: JTAG_MUX"]
pub const ALT0_JTAG_MUX_TDO: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: LPUART11_RTS_B of instance: LPUART11"]
pub const ALT1_LPUART11_RTS_B: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: LPI2C6_SCL of instance: LPI2C6"]
pub const ALT2_LPI2C6_SCL: u32 = 0x02;
#[doc = "Select mux mode: ALT3 mux port: MIC_BITSTREAM2 of instance: MIC"]
pub const ALT3_MIC_BITSTREAM2: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_SOUT of instance: LPSPI6"]
pub const ALT4_LPSPI6_SDO: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO11 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO11: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPI2C5_SDAS of instance: LPI2C5"]
pub const ALT6_LPI2C5_SDAS: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: ARM_TRACE_SWO of instance: ARM"]
pub const ALT7_ARM_TRACE_SWO: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPUART12_RXD of instance: LPUART12"]
pub const ALT8_LPUART12_RX: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO11 of instance: GPIO12"]
pub const ALT10_GPIO12_IO11: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_11"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_12 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_12 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TDI of instance: JTAG_MUX"]
pub const ALT0_JTAG_MUX_TDI: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: PIT2_TRIGGER0 of instance: PIT2"]
pub const ALT1_PIT2_TRIGGER0: u32 = 0x01;
#[doc = "Select mux mode: ALT3 mux port: MIC_BITSTREAM3 of instance: MIC"]
pub const ALT3_MIC_BITSTREAM3: u32 = 0x03;
#[doc = "Select mux mode: ALT4 mux port: LPSPI6_SIN of instance: LPSPI6"]
pub const ALT4_LPSPI6_SDI: u32 = 0x04;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO12 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO12: u32 = 0x05;
#[doc = "Select mux mode: ALT6 mux port: LPI2C5_HREQ of instance: LPI2C5"]
pub const ALT6_LPI2C5_HREQ: u32 = 0x06;
#[doc = "Select mux mode: ALT7 mux port: SAI4_TX_BCLK of instance: SAI4"]
pub const ALT7_SAI4_TX_BCLK: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_SCK of instance: LPSPI5"]
pub const ALT8_LPSPI5_SCK: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO12 of instance: GPIO12"]
pub const ALT10_GPIO12_IO12: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_12"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_13 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_13 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: JTAG_MUX"]
pub const ALT0_JTAG_MUX_MOD: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: MIC_BITSTREAM1 of instance: MIC"]
pub const ALT1_MIC_BITSTREAM1: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: PIT2_TRIGGER1 of instance: PIT2"]
pub const ALT2_PIT2_TRIGGER1: u32 = 0x02;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO13 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO13: u32 = 0x05;
#[doc = "Select mux mode: ALT7 mux port: SAI4_RX_DATA of instance: SAI4"]
pub const ALT7_SAI4_RX_DATA: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_PCS0 of instance: LPSPI5"]
pub const ALT8_LPSPI5_PCS0: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO13 of instance: GPIO12"]
pub const ALT10_GPIO12_IO13: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_13"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_14 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_14 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: JTAG_MUX/SWD_CLK"]
pub const ALT0_JTAG_MUX_TCK: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: MIC_BITSTREAM2 of instance: MIC"]
pub const ALT1_MIC_BITSTREAM2: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: PIT2_TRIGGER2 of instance: PIT2"]
pub const ALT2_PIT2_TRIGGER2: u32 = 0x02;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO14 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO14: u32 = 0x05;
#[doc = "Select mux mode: ALT7 mux port: SAI4_RX_BCLK of instance: SAI4"]
pub const ALT7_SAI4_RX_BCLK: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_SOUT of instance: LPSPI5"]
pub const ALT8_LPSPI5_SDO: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO14 of instance: GPIO12"]
pub const ALT10_GPIO12_IO14: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_14"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register"]
pub mod SW_MUX_CTL_PAD_GPIO_LPSR_15 {
#[doc = "MUX Mode Select Field."]
pub mod MUX_MODE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: JTAG_MUX/SWD_DIO"]
pub const ALT0_JTAG_MUX_TMS: u32 = 0;
#[doc = "Select mux mode: ALT1 mux port: MIC_BITSTREAM3 of instance: MIC"]
pub const ALT1_MIC_BITSTREAM3: u32 = 0x01;
#[doc = "Select mux mode: ALT2 mux port: PIT2_TRIGGER3 of instance: PIT2"]
pub const ALT2_PIT2_TRIGGER3: u32 = 0x02;
#[doc = "Select mux mode: ALT5 mux port: GPIO_MUX6_IO15 of instance: GPIO_MUX6"]
pub const ALT5_GPIO_MUX6_IO15: u32 = 0x05;
#[doc = "Select mux mode: ALT7 mux port: SAI4_RX_SYNC of instance: SAI4"]
pub const ALT7_SAI4_RX_SYNC: u32 = 0x07;
#[doc = "Select mux mode: ALT8 mux port: LPSPI5_SIN of instance: LPSPI5"]
pub const ALT8_LPSPI5_SDI: u32 = 0x08;
#[doc = "Select mux mode: ALT10 mux port: GPIO12_IO15 of instance: GPIO12"]
pub const ALT10_GPIO12_IO15: u32 = 0x0a;
}
}
#[doc = "Software Input On Field."]
pub mod SION {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Input Path is determined by functionality"]
pub const DISABLED: u32 = 0;
#[doc = "Force input path of pad GPIO_LPSR_15"]
pub const ENABLED: u32 = 0x01;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_00 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_01 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_01 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_02 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_02 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_03 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_03 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_04 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_04 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_05 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_05 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_06 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_06 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_07 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_07 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_08 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_08 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_09 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_09 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_10 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_10 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_11 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_11 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_12 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_12 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_13 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_13 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_14 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_14 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register"]
pub mod SW_PAD_CTL_PAD_GPIO_LPSR_15 {
#[doc = "Slew Rate Field"]
pub mod SRE {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Slow Slew Rate"]
pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
#[doc = "Fast Slew Rate"]
pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
}
}
#[doc = "Drive Strength Field"]
pub mod DSE {
pub const offset: u32 = 1;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "normal driver"]
pub const DSE_0_NORMAL_DRIVER: u32 = 0;
#[doc = "high driver"]
pub const DSE_1_HIGH_DRIVER: u32 = 0x01;
}
}
#[doc = "Pull / Keep Select Field"]
pub mod PUE {
pub const offset: u32 = 2;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Pull Disable"]
pub const PUE_0_DISABLE: u32 = 0;
#[doc = "Pull Enable"]
pub const PUE_1_PULL: u32 = 0x01;
}
}
#[doc = "Pull Up / Down Config. Field"]
pub mod PUS {
pub const offset: u32 = 3;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Weak pull down"]
pub const PUS_0_WEAK_PULL_DOWN: u32 = 0;
#[doc = "Weak pull up"]
pub const PUS_1_WEAK_PULL_UP: u32 = 0x01;
}
}
#[doc = "Open Drain LPSR Field"]
pub mod ODE_LPSR {
pub const offset: u32 = 5;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Disabled"]
pub const ODE_LPSR_0_DISABLED: u32 = 0;
#[doc = "Enabled"]
pub const ODE_LPSR_1_ENABLED: u32 = 0x01;
}
}
#[doc = "Domain write protection"]
pub mod DWP {
pub const offset: u32 = 28;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Both cores are allowed"]
pub const FORBID_NONE: u32 = 0;
#[doc = "CM7 is forbidden"]
pub const FORBID_CM7: u32 = 0x01;
#[doc = "CM4 is forbidden"]
pub const FORBID_CM4: u32 = 0x02;
#[doc = "Both cores are forbidden"]
pub const FORBID_BOTH: u32 = 0x03;
}
}
#[doc = "Domain write protection lock"]
pub mod DWP_LOCK {
pub const offset: u32 = 30;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Neither of DWP bits is locked"]
pub const LOCK_NONE: u32 = 0;
#[doc = "The lower DWP bit is locked"]
pub const LOCK_LOW: u32 = 0x01;
#[doc = "The higher DWP bit is locked"]
pub const LOCK_HIGH: u32 = 0x02;
#[doc = "Both DWP bits are locked"]
pub const LOCK_BOTH: u32 = 0x03;
}
}
}
#[doc = "CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register"]
pub mod CAN3_IPP_IND_CANRX_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_01 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_01_ALT0: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_07 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_07_ALT6: u32 = 0x01;
#[doc = "Selecting Pad: GPIO_LPSR_09 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_09_ALT1: u32 = 0x02;
}
}
}
#[doc = "LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub mod LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_05 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_05_ALT0: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_09 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_09_ALT6: u32 = 0x01;
}
}
}
#[doc = "LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub mod LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_04 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_04_ALT0: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_08 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_08_ALT6: u32 = 0x01;
}
}
}
#[doc = "LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register"]
pub mod LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_07 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_07_ALT0: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_11 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_11_ALT2: u32 = 0x01;
}
}
}
#[doc = "LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register"]
pub mod LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_06 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_06_ALT0: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_10 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_10_ALT2: u32 = 0x01;
}
}
}
#[doc = "LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register"]
pub mod LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_03 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_03_ALT1: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_13 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_13_ALT8: u32 = 0x01;
}
}
}
#[doc = "LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register"]
pub mod LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_02 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_02_ALT1: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_12 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_12_ALT8: u32 = 0x01;
}
}
}
#[doc = "LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register"]
pub mod LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_05 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_05_ALT1: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_15 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_15_ALT8: u32 = 0x01;
}
}
}
#[doc = "LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register"]
pub mod LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_04 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_04_ALT1: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_14 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_14_ALT8: u32 = 0x01;
}
}
}
#[doc = "LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub mod LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_05 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_05_ALT6: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_09 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_09_ALT0: u32 = 0x01;
}
}
}
#[doc = "LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub mod LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_04 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_04_ALT6: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_08 for Mode: ALT0"]
pub const SELECT_GPIO_LPSR_08_ALT0: u32 = 0x01;
}
}
}
#[doc = "LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY Register"]
pub mod LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_01 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_01_ALT6: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_07 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_07_ALT3: u32 = 0x01;
#[doc = "Selecting Pad: GPIO_LPSR_11 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_11_ALT8: u32 = 0x02;
}
}
}
#[doc = "LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY Register"]
pub mod LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_00 for Mode: ALT6"]
pub const SELECT_GPIO_LPSR_00_ALT6: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_06 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_06_ALT3: u32 = 0x01;
#[doc = "Selecting Pad: GPIO_LPSR_10 for Mode: ALT8"]
pub const SELECT_GPIO_LPSR_10_ALT8: u32 = 0x02;
}
}
}
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register"]
pub mod MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_01 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_01_ALT1: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_09 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_09_ALT3: u32 = 0x01;
}
}
}
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 DAISY Register"]
pub mod MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_10 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_10_ALT3: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_13 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_13_ALT1: u32 = 0x01;
}
}
}
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 DAISY Register"]
pub mod MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_11 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_11_ALT3: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_14 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_14_ALT1: u32 = 0x01;
}
}
}
#[doc = "MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 DAISY Register"]
pub mod MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_12 for Mode: ALT3"]
pub const SELECT_GPIO_LPSR_12_ALT3: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_15 for Mode: ALT1"]
pub const SELECT_GPIO_LPSR_15_ALT1: u32 = 0x01;
}
}
}
#[doc = "NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register"]
pub mod NMI_GLUE_IPP_IND_NMI_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_05 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_05_ALT7: u32 = 0;
#[doc = "Selecting Pad: WAKEUP_DIG for Mode: ALT7"]
pub const SELECT_WAKEUP_DIG_ALT7: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register"]
pub mod SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_00 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_00_ALT7: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_05 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_05_ALT2: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
pub mod SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_07 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_07_ALT2: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_14 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_14_ALT7: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
pub mod SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_06 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_06_ALT2: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_13 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_13_ALT7: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
pub mod SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_08 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_08_ALT2: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_15 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_15_ALT7: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
pub mod SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_04 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_04_ALT2: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_12 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_12_ALT7: u32 = 0x01;
}
}
}
#[doc = "SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
pub mod SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT {
#[doc = "Selecting Pads Involved in Daisy Chain."]
pub mod DAISY {
pub const offset: u32 = 0;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Selecting Pad: GPIO_LPSR_03 for Mode: ALT2"]
pub const SELECT_GPIO_LPSR_03_ALT2: u32 = 0;
#[doc = "Selecting Pad: GPIO_LPSR_10 for Mode: ALT7"]
pub const SELECT_GPIO_LPSR_10_ALT7: u32 = 0x01;
}
}
}