gd32f1 0.3.0

Device support crate for GD32F1 devices
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

#[doc = "Register `DMATB` reader"]
pub struct R(crate::R<DMATB_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DMATB_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::convert::From<crate::R<DMATB_SPEC>> for R {
    fn from(reader: crate::R<DMATB_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DMATB` writer"]
pub struct W(crate::W<DMATB_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DMATB_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl core::convert::From<crate::W<DMATB_SPEC>> for W {
    fn from(writer: crate::W<DMATB_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `DMATB` reader - DMA transfer"]
pub struct DMATB_R(crate::FieldReader<u16, u16>);
impl DMATB_R {
    pub(crate) fn new(bits: u16) -> Self {
        DMATB_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DMATB_R {
    type Target = crate::FieldReader<u16, u16>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
#[doc = "Field `DMATB` writer - DMA transfer"]
pub struct DMATB_W<'a> {
    w: &'a mut W,
}
impl<'a> DMATB_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u16) -> &'a mut W {
        self.w.bits = (self.w.bits & !0xffff) | (value as u16 & 0xffff);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:15 - DMA transfer"]
    #[inline(always)]
    pub fn dmatb(&self) -> DMATB_R {
        DMATB_R::new((self.bits & 0xffff) as u16)
    }
}
impl W {
    #[doc = "Bits 0:15 - DMA transfer"]
    #[inline(always)]
    pub fn dmatb(&mut self) -> DMATB_W {
        DMATB_W { w: self }
    }
    #[doc = "Writes raw bits to the register."]
    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "DMA transfer buffer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatb](index.html) module"]
pub struct DMATB_SPEC;
impl crate::RegisterSpec for DMATB_SPEC {
    type Ux = u16;
}
#[doc = "`read()` method returns [dmatb::R](R) reader structure"]
impl crate::Readable for DMATB_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmatb::W](W) writer structure"]
impl crate::Writable for DMATB_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets DMATB to value 0"]
impl crate::Resettable for DMATB_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}