#[doc = "Register `CTL1` reader"]
pub struct R(crate::R<CTL1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTL1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::convert::From<crate::R<CTL1_SPEC>> for R {
fn from(reader: crate::R<CTL1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTL1` writer"]
pub struct W(crate::W<CTL1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTL1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl core::convert::From<crate::W<CTL1_SPEC>> for W {
fn from(writer: crate::W<CTL1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Idle state of channel 0 complementary output"]
pub type ISO0N_A = crate::gd32f190::timer0::ctl1::ISO0N_A;
#[doc = "Field `ISO0N` reader - Idle state of channel 0 complementary output"]
pub type ISO0N_R = crate::gd32f190::timer0::ctl1::ISO0N_R;
#[doc = "Field `ISO0N` writer - Idle state of channel 0 complementary output"]
pub struct ISO0N_W<'a> {
w: &'a mut W,
}
impl<'a> ISO0N_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ISO0N_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "CHn_ON=0 when POEN=0"]
#[inline(always)]
pub fn low(self) -> &'a mut W {
self.variant(ISO0N_A::LOW)
}
#[doc = "CHn_ON=1 when POEN=0"]
#[inline(always)]
pub fn high(self) -> &'a mut W {
self.variant(ISO0N_A::HIGH)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9);
self.w
}
}
#[doc = "Idle state of channel 0 output"]
pub type ISO0_A = crate::gd32f190::timer0::ctl1::ISO0_A;
#[doc = "Field `ISO0` reader - Idle state of channel 0 output"]
pub type ISO0_R = crate::gd32f190::timer0::ctl1::ISO0_R;
#[doc = "Field `ISO0` writer - Idle state of channel 0 output"]
pub struct ISO0_W<'a> {
w: &'a mut W,
}
impl<'a> ISO0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ISO0_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0"]
#[inline(always)]
pub fn low(self) -> &'a mut W {
self.variant(ISO0_A::LOW)
}
#[doc = "CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0"]
#[inline(always)]
pub fn high(self) -> &'a mut W {
self.variant(ISO0_A::HIGH)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8);
self.w
}
}
#[doc = "DMA request source selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAS_A {
#[doc = "0: CCx DMA request sent when CCx event occurs"]
ONCOMPARE = 0,
#[doc = "1: CCx DMA request sent when update event occurs"]
ONUPDATE = 1,
}
impl From<DMAS_A> for bool {
#[inline(always)]
fn from(variant: DMAS_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DMAS` reader - DMA request source selection"]
pub struct DMAS_R(crate::FieldReader<bool, DMAS_A>);
impl DMAS_R {
pub(crate) fn new(bits: bool) -> Self {
DMAS_R(crate::FieldReader::new(bits))
}
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DMAS_A {
match self.bits {
false => DMAS_A::ONCOMPARE,
true => DMAS_A::ONUPDATE,
}
}
#[doc = "Checks if the value of the field is `ONCOMPARE`"]
#[inline(always)]
pub fn is_on_compare(&self) -> bool {
**self == DMAS_A::ONCOMPARE
}
#[doc = "Checks if the value of the field is `ONUPDATE`"]
#[inline(always)]
pub fn is_on_update(&self) -> bool {
**self == DMAS_A::ONUPDATE
}
}
impl core::ops::Deref for DMAS_R {
type Target = crate::FieldReader<bool, DMAS_A>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DMAS` writer - DMA request source selection"]
pub struct DMAS_W<'a> {
w: &'a mut W,
}
impl<'a> DMAS_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMAS_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "CCx DMA request sent when CCx event occurs"]
#[inline(always)]
pub fn on_compare(self) -> &'a mut W {
self.variant(DMAS_A::ONCOMPARE)
}
#[doc = "CCx DMA request sent when update event occurs"]
#[inline(always)]
pub fn on_update(self) -> &'a mut W {
self.variant(DMAS_A::ONUPDATE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3);
self.w
}
}
#[doc = "Commutation control shadow register update control"]
pub type CCUC_A = crate::gd32f190::timer0::ctl1::CCUC_A;
#[doc = "Field `CCUC` reader - Commutation control shadow register update control"]
pub type CCUC_R = crate::gd32f190::timer0::ctl1::CCUC_R;
#[doc = "Field `CCUC` writer - Commutation control shadow register update control"]
pub struct CCUC_W<'a> {
w: &'a mut W,
}
impl<'a> CCUC_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CCUC_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Capture/compare are updated only by setting the CMTG bit"]
#[inline(always)]
pub fn default(self) -> &'a mut W {
self.variant(CCUC_A::DEFAULT)
}
#[doc = "Capture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI"]
#[inline(always)]
pub fn with_rising_edge(self) -> &'a mut W {
self.variant(CCUC_A::WITHRISINGEDGE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2);
self.w
}
}
#[doc = "Commutation control shadow register enable"]
pub type CCSE_A = crate::gd32f190::timer0::ctl1::CCSE_A;
#[doc = "Field `CCSE` reader - Commutation control shadow register enable"]
pub type CCSE_R = crate::gd32f190::timer0::ctl1::CCSE_R;
#[doc = "Field `CCSE` writer - Commutation control shadow register enable"]
pub struct CCSE_W<'a> {
w: &'a mut W,
}
impl<'a> CCSE_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CCSE_A) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled"]
#[inline(always)]
pub fn not_preloaded(self) -> &'a mut W {
self.variant(CCSE_A::NOTPRELOADED)
}
#[doc = "The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled"]
#[inline(always)]
pub fn preloaded(self) -> &'a mut W {
self.variant(CCSE_A::PRELOADED)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01);
self.w
}
}
impl R {
#[doc = "Bit 9 - Idle state of channel 0 complementary output"]
#[inline(always)]
pub fn iso0n(&self) -> ISO0N_R {
ISO0N_R::new(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 8 - Idle state of channel 0 output"]
#[inline(always)]
pub fn iso0(&self) -> ISO0_R {
ISO0_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 3 - DMA request source selection"]
#[inline(always)]
pub fn dmas(&self) -> DMAS_R {
DMAS_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - Commutation control shadow register update control"]
#[inline(always)]
pub fn ccuc(&self) -> CCUC_R {
CCUC_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 0 - Commutation control shadow register enable"]
#[inline(always)]
pub fn ccse(&self) -> CCSE_R {
CCSE_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 9 - Idle state of channel 0 complementary output"]
#[inline(always)]
pub fn iso0n(&mut self) -> ISO0N_W {
ISO0N_W { w: self }
}
#[doc = "Bit 8 - Idle state of channel 0 output"]
#[inline(always)]
pub fn iso0(&mut self) -> ISO0_W {
ISO0_W { w: self }
}
#[doc = "Bit 3 - DMA request source selection"]
#[inline(always)]
pub fn dmas(&mut self) -> DMAS_W {
DMAS_W { w: self }
}
#[doc = "Bit 2 - Commutation control shadow register update control"]
#[inline(always)]
pub fn ccuc(&mut self) -> CCUC_W {
CCUC_W { w: self }
}
#[doc = "Bit 0 - Commutation control shadow register enable"]
#[inline(always)]
pub fn ccse(&mut self) -> CCSE_W {
CCSE_W { w: self }
}
#[doc = "Writes raw bits to the register."]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl1](index.html) module"]
pub struct CTL1_SPEC;
impl crate::RegisterSpec for CTL1_SPEC {
type Ux = u16;
}
#[doc = "`read()` method returns [ctl1::R](R) reader structure"]
impl crate::Readable for CTL1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctl1::W](W) writer structure"]
impl crate::Writable for CTL1_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CTL1 to value 0"]
impl crate::Resettable for CTL1_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}