esp32c5 0.2.2

Peripheral access crate for the ESP32-C5
Documentation 
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#[doc = "Register `EVT_ST4_CLR` writer"]
pub type W = crate::W<EVT_ST4_CLR_SPEC>;
#[doc = "Field `GDMA_EVT_OUT_DONE_CH0_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_DONE_CH1_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_DONE_CH2_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_EOF_CH0_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_EOF_CH1_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_EOF_CH2_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMU_EVT_SLEEP_WEEKUP_ST_CLR` writer - Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
pub type PMU_EVT_SLEEP_WEEKUP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<EVT_ST4_CLR_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    #[doc = "Bit 0 - Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_done_ch0_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_DONE_CH0_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_DONE_CH0_ST_CLR_W::new(self, 0)
    }
    #[doc = "Bit 1 - Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_done_ch1_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_DONE_CH1_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_DONE_CH1_ST_CLR_W::new(self, 1)
    }
    #[doc = "Bit 2 - Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_done_ch2_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_DONE_CH2_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_DONE_CH2_ST_CLR_W::new(self, 2)
    }
    #[doc = "Bit 3 - Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_eof_ch0_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_EOF_CH0_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_EOF_CH0_ST_CLR_W::new(self, 3)
    }
    #[doc = "Bit 4 - Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_eof_ch1_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_EOF_CH1_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_EOF_CH1_ST_CLR_W::new(self, 4)
    }
    #[doc = "Bit 5 - Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_eof_ch2_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_EOF_CH2_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_EOF_CH2_ST_CLR_W::new(self, 5)
    }
    #[doc = "Bit 6 - Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_total_eof_ch0_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W::new(self, 6)
    }
    #[doc = "Bit 7 - Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_total_eof_ch1_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W::new(self, 7)
    }
    #[doc = "Bit 8 - Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_total_eof_ch2_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W::new(self, 8)
    }
    #[doc = "Bit 9 - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_empty_ch0_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 9)
    }
    #[doc = "Bit 10 - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_empty_ch1_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 10)
    }
    #[doc = "Bit 11 - Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_empty_ch2_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 11)
    }
    #[doc = "Bit 12 - Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_full_ch0_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W::new(self, 12)
    }
    #[doc = "Bit 13 - Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_full_ch1_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W::new(self, 13)
    }
    #[doc = "Bit 14 - Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn gdma_evt_out_fifo_full_ch2_st_clr(
        &mut self,
    ) -> GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W::new(self, 14)
    }
    #[doc = "Bit 15 - Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\\\0: Invalid, No effect\\\\1: Clear"]
    #[inline(always)]
    pub fn pmu_evt_sleep_weekup_st_clr(
        &mut self,
    ) -> PMU_EVT_SLEEP_WEEKUP_ST_CLR_W<'_, EVT_ST4_CLR_SPEC> {
        PMU_EVT_SLEEP_WEEKUP_ST_CLR_W::new(self, 15)
    }
}
#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`evt_st4_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_ST4_CLR_SPEC;
impl crate::RegisterSpec for EVT_ST4_CLR_SPEC {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`evt_st4_clr::W`](W) writer structure"]
impl crate::Writable for EVT_ST4_CLR_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EVT_ST4_CLR to value 0"]
impl crate::Resettable for EVT_ST4_CLR_SPEC {}