Expand description
SPI input delay number configuration
Structs§
- DIN_
NUM_ SPEC - SPI input delay number configuration
Type Aliases§
- DIN0_
NUM_ R - Field
DIN0_NUM
reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN0_
NUM_ W - Field
DIN0_NUM
writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN1_
NUM_ R - Field
DIN1_NUM
reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN1_
NUM_ W - Field
DIN1_NUM
writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN2_
NUM_ R - Field
DIN2_NUM
reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN2_
NUM_ W - Field
DIN2_NUM
writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN3_
NUM_ R - Field
DIN3_NUM
reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - DIN3_
NUM_ W - Field
DIN3_NUM
writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. - R
- Register
DIN_NUM
reader - W
- Register
DIN_NUM
writer