esp32c3/spi2/
din_num.rs

1#[doc = "Register `DIN_NUM` reader"]
2pub type R = crate::R<DIN_NUM_SPEC>;
3#[doc = "Register `DIN_NUM` writer"]
4pub type W = crate::W<DIN_NUM_SPEC>;
5#[doc = "Field `DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
6pub type DIN0_NUM_R = crate::FieldReader;
7#[doc = "Field `DIN0_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
8pub type DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
10pub type DIN1_NUM_R = crate::FieldReader;
11#[doc = "Field `DIN1_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
12pub type DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
14pub type DIN2_NUM_R = crate::FieldReader;
15#[doc = "Field `DIN2_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
16pub type DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
18pub type DIN3_NUM_R = crate::FieldReader;
19#[doc = "Field `DIN3_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
20pub type DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21impl R {
22    #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
23    #[inline(always)]
24    pub fn din0_num(&self) -> DIN0_NUM_R {
25        DIN0_NUM_R::new((self.bits & 3) as u8)
26    }
27    #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
28    #[inline(always)]
29    pub fn din1_num(&self) -> DIN1_NUM_R {
30        DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
31    }
32    #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
33    #[inline(always)]
34    pub fn din2_num(&self) -> DIN2_NUM_R {
35        DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
36    }
37    #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
38    #[inline(always)]
39    pub fn din3_num(&self) -> DIN3_NUM_R {
40        DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("DIN_NUM")
47            .field("din0_num", &self.din0_num())
48            .field("din1_num", &self.din1_num())
49            .field("din2_num", &self.din2_num())
50            .field("din3_num", &self.din3_num())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
56    #[inline(always)]
57    pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
58        DIN0_NUM_W::new(self, 0)
59    }
60    #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
61    #[inline(always)]
62    pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
63        DIN1_NUM_W::new(self, 2)
64    }
65    #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
66    #[inline(always)]
67    pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
68        DIN2_NUM_W::new(self, 4)
69    }
70    #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
71    #[inline(always)]
72    pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
73        DIN3_NUM_W::new(self, 6)
74    }
75}
76#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`din_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct DIN_NUM_SPEC;
78impl crate::RegisterSpec for DIN_NUM_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`din_num::R`](R) reader structure"]
82impl crate::Readable for DIN_NUM_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`din_num::W`](W) writer structure"]
84impl crate::Writable for DIN_NUM_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets DIN_NUM to value 0"]
90impl crate::Resettable for DIN_NUM_SPEC {
91    const RESET_VALUE: u32 = 0;
92}
esp32c3/spi2/din_num.rs

esp32c3/spi2/
din_num.rs
