#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 0;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
fn WIFI_MAC();
fn WIFI_NMI();
fn WIFI_BB();
fn BT_MAC();
fn BT_BB();
fn BT_BB_NMI();
fn RWBT();
fn RWBLE();
fn RWBT_NMI();
fn RWBLE_NMI();
fn UHCI0();
fn UHCI1();
fn TG0_T0_LEVEL();
fn TG0_T1_LEVEL();
fn TG0_WDT_LEVEL();
fn TG0_LACT_LEVEL();
fn TG1_T0_LEVEL();
fn TG1_T1_LEVEL();
fn TG1_WDT_LEVEL();
fn TG1_LACT_LEVEL();
fn GPIO();
fn GPIO_NMI();
fn FROM_CPU_INTR0();
fn FROM_CPU_INTR1();
fn FROM_CPU_INTR2();
fn FROM_CPU_INTR3();
fn SPI0();
fn SPI1();
fn SPI2();
fn SPI3();
fn I2S0();
fn I2S1();
fn UART0();
fn UART1();
fn UART2();
fn SDIO_HOST();
fn ETH_MAC();
fn MCPWM0();
fn MCPWM1();
fn MCPWM2();
fn MCPWM3();
fn LEDC();
fn EFUSE();
fn TWAI0();
fn RTC_CORE();
fn RMT();
fn PCNT();
fn I2C_EXT0();
fn I2C_EXT1();
fn RSA();
fn SPI1_DMA();
fn SPI2_DMA();
fn SPI3_DMA();
fn WDT();
fn TIMER1();
fn TIMER2();
fn TG0_T0_EDGE();
fn TG0_T1_EDGE();
fn TG0_WDT_EDGE();
fn TG0_LACT_EDGE();
fn TG1_T0_EDGE();
fn TG1_T1_EDGE();
fn TG1_WDT_EDGE();
fn TG1_LACT_EDGE();
fn MMU_IA();
fn MPU_IA();
fn CACHE_IA();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
pub _handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".rwtext"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 69] = [
Vector { _handler: WIFI_MAC },
Vector { _handler: WIFI_NMI },
Vector { _handler: WIFI_BB },
Vector { _handler: BT_MAC },
Vector { _handler: BT_BB },
Vector {
_handler: BT_BB_NMI,
},
Vector { _handler: RWBT },
Vector { _handler: RWBLE },
Vector { _handler: RWBT_NMI },
Vector {
_handler: RWBLE_NMI,
},
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: UHCI0 },
Vector { _handler: UHCI1 },
Vector {
_handler: TG0_T0_LEVEL,
},
Vector {
_handler: TG0_T1_LEVEL,
},
Vector {
_handler: TG0_WDT_LEVEL,
},
Vector {
_handler: TG0_LACT_LEVEL,
},
Vector {
_handler: TG1_T0_LEVEL,
},
Vector {
_handler: TG1_T1_LEVEL,
},
Vector {
_handler: TG1_WDT_LEVEL,
},
Vector {
_handler: TG1_LACT_LEVEL,
},
Vector { _handler: GPIO },
Vector { _handler: GPIO_NMI },
Vector {
_handler: FROM_CPU_INTR0,
},
Vector {
_handler: FROM_CPU_INTR1,
},
Vector {
_handler: FROM_CPU_INTR2,
},
Vector {
_handler: FROM_CPU_INTR3,
},
Vector { _handler: SPI0 },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: SPI3 },
Vector { _handler: I2S0 },
Vector { _handler: I2S1 },
Vector { _handler: UART0 },
Vector { _handler: UART1 },
Vector { _handler: UART2 },
Vector {
_handler: SDIO_HOST,
},
Vector { _handler: ETH_MAC },
Vector { _handler: MCPWM0 },
Vector { _handler: MCPWM1 },
Vector { _handler: MCPWM2 },
Vector { _handler: MCPWM3 },
Vector { _handler: LEDC },
Vector { _handler: EFUSE },
Vector { _handler: TWAI0 },
Vector { _handler: RTC_CORE },
Vector { _handler: RMT },
Vector { _handler: PCNT },
Vector { _handler: I2C_EXT0 },
Vector { _handler: I2C_EXT1 },
Vector { _handler: RSA },
Vector { _handler: SPI1_DMA },
Vector { _handler: SPI2_DMA },
Vector { _handler: SPI3_DMA },
Vector { _handler: WDT },
Vector { _handler: TIMER1 },
Vector { _handler: TIMER2 },
Vector {
_handler: TG0_T0_EDGE,
},
Vector {
_handler: TG0_T1_EDGE,
},
Vector {
_handler: TG0_WDT_EDGE,
},
Vector {
_handler: TG0_LACT_EDGE,
},
Vector {
_handler: TG1_T0_EDGE,
},
Vector {
_handler: TG1_T1_EDGE,
},
Vector {
_handler: TG1_WDT_EDGE,
},
Vector {
_handler: TG1_LACT_EDGE,
},
Vector { _handler: MMU_IA },
Vector { _handler: MPU_IA },
Vector { _handler: CACHE_IA },
];
#[doc = r"Enumeration of all the interrupts."]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "0 - WIFI_MAC"]
WIFI_MAC = 0,
#[doc = "1 - WIFI_NMI"]
WIFI_NMI = 1,
#[doc = "2 - WIFI_BB"]
WIFI_BB = 2,
#[doc = "3 - BT_MAC"]
BT_MAC = 3,
#[doc = "4 - BT_BB"]
BT_BB = 4,
#[doc = "5 - BT_BB_NMI"]
BT_BB_NMI = 5,
#[doc = "6 - RWBT"]
RWBT = 6,
#[doc = "7 - RWBLE"]
RWBLE = 7,
#[doc = "8 - RWBT_NMI"]
RWBT_NMI = 8,
#[doc = "9 - RWBLE_NMI"]
RWBLE_NMI = 9,
#[doc = "12 - UHCI0"]
UHCI0 = 12,
#[doc = "13 - UHCI1"]
UHCI1 = 13,
#[doc = "14 - TG0_T0_LEVEL"]
TG0_T0_LEVEL = 14,
#[doc = "15 - TG0_T1_LEVEL"]
TG0_T1_LEVEL = 15,
#[doc = "16 - TG0_WDT_LEVEL"]
TG0_WDT_LEVEL = 16,
#[doc = "17 - TG0_LACT_LEVEL"]
TG0_LACT_LEVEL = 17,
#[doc = "18 - TG1_T0_LEVEL"]
TG1_T0_LEVEL = 18,
#[doc = "19 - TG1_T1_LEVEL"]
TG1_T1_LEVEL = 19,
#[doc = "20 - TG1_WDT_LEVEL"]
TG1_WDT_LEVEL = 20,
#[doc = "21 - TG1_LACT_LEVEL"]
TG1_LACT_LEVEL = 21,
#[doc = "22 - GPIO"]
GPIO = 22,
#[doc = "23 - GPIO_NMI"]
GPIO_NMI = 23,
#[doc = "24 - FROM_CPU_INTR0"]
FROM_CPU_INTR0 = 24,
#[doc = "25 - FROM_CPU_INTR1"]
FROM_CPU_INTR1 = 25,
#[doc = "26 - FROM_CPU_INTR2"]
FROM_CPU_INTR2 = 26,
#[doc = "27 - FROM_CPU_INTR3"]
FROM_CPU_INTR3 = 27,
#[doc = "28 - SPI0"]
SPI0 = 28,
#[doc = "29 - SPI1"]
SPI1 = 29,
#[doc = "30 - SPI2"]
SPI2 = 30,
#[doc = "31 - SPI3"]
SPI3 = 31,
#[doc = "32 - I2S0"]
I2S0 = 32,
#[doc = "33 - I2S1"]
I2S1 = 33,
#[doc = "34 - UART0"]
UART0 = 34,
#[doc = "35 - UART1"]
UART1 = 35,
#[doc = "36 - UART2"]
UART2 = 36,
#[doc = "37 - SDIO_HOST"]
SDIO_HOST = 37,
#[doc = "38 - ETH_MAC"]
ETH_MAC = 38,
#[doc = "39 - MCPWM0"]
MCPWM0 = 39,
#[doc = "40 - MCPWM1"]
MCPWM1 = 40,
#[doc = "41 - MCPWM2"]
MCPWM2 = 41,
#[doc = "42 - MCPWM3"]
MCPWM3 = 42,
#[doc = "43 - LEDC"]
LEDC = 43,
#[doc = "44 - EFUSE"]
EFUSE = 44,
#[doc = "45 - TWAI0"]
TWAI0 = 45,
#[doc = "46 - RTC_CORE"]
RTC_CORE = 46,
#[doc = "47 - RMT"]
RMT = 47,
#[doc = "48 - PCNT"]
PCNT = 48,
#[doc = "49 - I2C_EXT0"]
I2C_EXT0 = 49,
#[doc = "50 - I2C_EXT1"]
I2C_EXT1 = 50,
#[doc = "51 - RSA"]
RSA = 51,
#[doc = "52 - SPI1_DMA"]
SPI1_DMA = 52,
#[doc = "53 - SPI2_DMA"]
SPI2_DMA = 53,
#[doc = "54 - SPI3_DMA"]
SPI3_DMA = 54,
#[doc = "55 - WDT"]
WDT = 55,
#[doc = "56 - TIMER1"]
TIMER1 = 56,
#[doc = "57 - TIMER2"]
TIMER2 = 57,
#[doc = "58 - TG0_T0_EDGE"]
TG0_T0_EDGE = 58,
#[doc = "59 - TG0_T1_EDGE"]
TG0_T1_EDGE = 59,
#[doc = "60 - TG0_WDT_EDGE"]
TG0_WDT_EDGE = 60,
#[doc = "61 - TG0_LACT_EDGE"]
TG0_LACT_EDGE = 61,
#[doc = "62 - TG1_T0_EDGE"]
TG1_T0_EDGE = 62,
#[doc = "63 - TG1_T1_EDGE"]
TG1_T1_EDGE = 63,
#[doc = "64 - TG1_WDT_EDGE"]
TG1_WDT_EDGE = 64,
#[doc = "65 - TG1_LACT_EDGE"]
TG1_LACT_EDGE = 65,
#[doc = "66 - MMU_IA"]
MMU_IA = 66,
#[doc = "67 - MPU_IA"]
MPU_IA = 67,
#[doc = "68 - CACHE_IA"]
CACHE_IA = 68,
}
#[doc = r" TryFromInterruptError"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Debug, Copy, Clone)]
pub struct TryFromInterruptError(());
impl Interrupt {
#[doc = r" Attempt to convert a given value into an `Interrupt`"]
#[inline]
pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError> {
match value {
0 => Ok(Interrupt::WIFI_MAC),
1 => Ok(Interrupt::WIFI_NMI),
2 => Ok(Interrupt::WIFI_BB),
3 => Ok(Interrupt::BT_MAC),
4 => Ok(Interrupt::BT_BB),
5 => Ok(Interrupt::BT_BB_NMI),
6 => Ok(Interrupt::RWBT),
7 => Ok(Interrupt::RWBLE),
8 => Ok(Interrupt::RWBT_NMI),
9 => Ok(Interrupt::RWBLE_NMI),
12 => Ok(Interrupt::UHCI0),
13 => Ok(Interrupt::UHCI1),
14 => Ok(Interrupt::TG0_T0_LEVEL),
15 => Ok(Interrupt::TG0_T1_LEVEL),
16 => Ok(Interrupt::TG0_WDT_LEVEL),
17 => Ok(Interrupt::TG0_LACT_LEVEL),
18 => Ok(Interrupt::TG1_T0_LEVEL),
19 => Ok(Interrupt::TG1_T1_LEVEL),
20 => Ok(Interrupt::TG1_WDT_LEVEL),
21 => Ok(Interrupt::TG1_LACT_LEVEL),
22 => Ok(Interrupt::GPIO),
23 => Ok(Interrupt::GPIO_NMI),
24 => Ok(Interrupt::FROM_CPU_INTR0),
25 => Ok(Interrupt::FROM_CPU_INTR1),
26 => Ok(Interrupt::FROM_CPU_INTR2),
27 => Ok(Interrupt::FROM_CPU_INTR3),
28 => Ok(Interrupt::SPI0),
29 => Ok(Interrupt::SPI1),
30 => Ok(Interrupt::SPI2),
31 => Ok(Interrupt::SPI3),
32 => Ok(Interrupt::I2S0),
33 => Ok(Interrupt::I2S1),
34 => Ok(Interrupt::UART0),
35 => Ok(Interrupt::UART1),
36 => Ok(Interrupt::UART2),
37 => Ok(Interrupt::SDIO_HOST),
38 => Ok(Interrupt::ETH_MAC),
39 => Ok(Interrupt::MCPWM0),
40 => Ok(Interrupt::MCPWM1),
41 => Ok(Interrupt::MCPWM2),
42 => Ok(Interrupt::MCPWM3),
43 => Ok(Interrupt::LEDC),
44 => Ok(Interrupt::EFUSE),
45 => Ok(Interrupt::TWAI0),
46 => Ok(Interrupt::RTC_CORE),
47 => Ok(Interrupt::RMT),
48 => Ok(Interrupt::PCNT),
49 => Ok(Interrupt::I2C_EXT0),
50 => Ok(Interrupt::I2C_EXT1),
51 => Ok(Interrupt::RSA),
52 => Ok(Interrupt::SPI1_DMA),
53 => Ok(Interrupt::SPI2_DMA),
54 => Ok(Interrupt::SPI3_DMA),
55 => Ok(Interrupt::WDT),
56 => Ok(Interrupt::TIMER1),
57 => Ok(Interrupt::TIMER2),
58 => Ok(Interrupt::TG0_T0_EDGE),
59 => Ok(Interrupt::TG0_T1_EDGE),
60 => Ok(Interrupt::TG0_WDT_EDGE),
61 => Ok(Interrupt::TG0_LACT_EDGE),
62 => Ok(Interrupt::TG1_T0_EDGE),
63 => Ok(Interrupt::TG1_T1_EDGE),
64 => Ok(Interrupt::TG1_WDT_EDGE),
65 => Ok(Interrupt::TG1_LACT_EDGE),
66 => Ok(Interrupt::MMU_IA),
67 => Ok(Interrupt::MPU_IA),
68 => Ok(Interrupt::CACHE_IA),
_ => Err(TryFromInterruptError(())),
}
}
}
#[doc = "AES (Advanced Encryption Standard) Accelerator"]
pub type AES = crate::Periph<aes::RegisterBlock, 0x3ff0_1000>;
impl core::fmt::Debug for AES {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AES").finish()
}
}
#[doc = "AES (Advanced Encryption Standard) Accelerator"]
pub mod aes;
#[doc = "APB (Advanced Peripheral Bus) Controller"]
pub type APB_CTRL = crate::Periph<apb_ctrl::RegisterBlock, 0x3ff6_6000>;
impl core::fmt::Debug for APB_CTRL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("APB_CTRL").finish()
}
}
#[doc = "APB (Advanced Peripheral Bus) Controller"]
pub mod apb_ctrl;
#[doc = "BB Peripheral"]
pub type BB = crate::Periph<bb::RegisterBlock, 0x3ff5_d000>;
impl core::fmt::Debug for BB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BB").finish()
}
}
#[doc = "BB Peripheral"]
pub mod bb;
#[doc = "DPORT Peripheral"]
pub type DPORT = crate::Periph<dport::RegisterBlock, 0x3ff0_0000>;
impl core::fmt::Debug for DPORT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DPORT").finish()
}
}
#[doc = "DPORT Peripheral"]
pub mod dport;
#[doc = "eFuse Controller"]
pub type EFUSE = crate::Periph<efuse::RegisterBlock, 0x3ff5_a000>;
impl core::fmt::Debug for EFUSE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EFUSE").finish()
}
}
#[doc = "eFuse Controller"]
pub mod efuse;
#[doc = "Ethernet DMA configuration and control registers"]
pub type EMAC_DMA = crate::Periph<emac_dma::RegisterBlock, 0x3ff6_9000>;
impl core::fmt::Debug for EMAC_DMA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EMAC_DMA").finish()
}
}
#[doc = "Ethernet DMA configuration and control registers"]
pub mod emac_dma;
#[doc = "Ethernet Clock, PHY type, and SRAM configuration registers"]
pub type EMAC_EXT = crate::Periph<emac_ext::RegisterBlock, 0x3ff6_9800>;
impl core::fmt::Debug for EMAC_EXT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EMAC_EXT").finish()
}
}
#[doc = "Ethernet Clock, PHY type, and SRAM configuration registers"]
pub mod emac_ext;
#[doc = "Ethernet MAC configuration and control registers"]
pub type EMAC_MAC = crate::Periph<emac_mac::RegisterBlock, 0x3ff6_a000>;
impl core::fmt::Debug for EMAC_MAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EMAC_MAC").finish()
}
}
#[doc = "Ethernet MAC configuration and control registers"]
pub mod emac_mac;
#[doc = "FLASH_ENCRYPTION Peripheral"]
pub type FLASH_ENCRYPTION = crate::Periph<flash_encryption::RegisterBlock, 0x3ff4_6000>;
impl core::fmt::Debug for FLASH_ENCRYPTION {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH_ENCRYPTION").finish()
}
}
#[doc = "FLASH_ENCRYPTION Peripheral"]
pub mod flash_encryption;
#[doc = "FRC_TIMER Peripheral"]
pub type FRC_TIMER = crate::Periph<frc_timer::RegisterBlock, 0x3ff4_7000>;
impl core::fmt::Debug for FRC_TIMER {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FRC_TIMER").finish()
}
}
#[doc = "FRC_TIMER Peripheral"]
pub mod frc_timer;
#[doc = "General Purpose Input/Output"]
pub type GPIO = crate::Periph<gpio::RegisterBlock, 0x3ff4_4000>;
impl core::fmt::Debug for GPIO {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIO").finish()
}
}
#[doc = "General Purpose Input/Output"]
pub mod gpio;
#[doc = "Sigma-Delta Modulation"]
pub type GPIO_SD = crate::Periph<gpio_sd::RegisterBlock, 0x3ff4_4f00>;
impl core::fmt::Debug for GPIO_SD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIO_SD").finish()
}
}
#[doc = "Sigma-Delta Modulation"]
pub mod gpio_sd;
#[doc = "HINF Peripheral"]
pub type HINF = crate::Periph<hinf::RegisterBlock, 0x3ff4_b000>;
impl core::fmt::Debug for HINF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HINF").finish()
}
}
#[doc = "HINF Peripheral"]
pub mod hinf;
#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
pub type I2C0 = crate::Periph<i2c0::RegisterBlock, 0x3ff5_3000>;
impl core::fmt::Debug for I2C0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C0").finish()
}
}
#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
pub mod i2c0;
#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
pub type I2C1 = crate::Periph<i2c0::RegisterBlock, 0x3ff6_7000>;
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
pub use self::i2c0 as i2c1;
#[doc = "I2S (Inter-IC Sound) Controller 0"]
pub type I2S0 = crate::Periph<i2s0::RegisterBlock, 0x3ff4_f000>;
impl core::fmt::Debug for I2S0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S0").finish()
}
}
#[doc = "I2S (Inter-IC Sound) Controller 0"]
pub mod i2s0;
#[doc = "I2S (Inter-IC Sound) Controller 1"]
pub type I2S1 = crate::Periph<i2s0::RegisterBlock, 0x3ff6_d000>;
impl core::fmt::Debug for I2S1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2S1").finish()
}
}
#[doc = "I2S (Inter-IC Sound) Controller 1"]
pub use self::i2s0 as i2s1;
#[doc = "Input/Output Multiplexer"]
pub type IO_MUX = crate::Periph<io_mux::RegisterBlock, 0x3ff4_9000>;
impl core::fmt::Debug for IO_MUX {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IO_MUX").finish()
}
}
#[doc = "Input/Output Multiplexer"]
pub mod io_mux;
#[doc = "LED Control PWM (Pulse Width Modulation)"]
pub type LEDC = crate::Periph<ledc::RegisterBlock, 0x3ff5_9000>;
impl core::fmt::Debug for LEDC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LEDC").finish()
}
}
#[doc = "LED Control PWM (Pulse Width Modulation)"]
pub mod ledc;
#[doc = "Motor Control Pulse-Width Modulation 0"]
pub type MCPWM0 = crate::Periph<mcpwm0::RegisterBlock, 0x3ff5_e000>;
impl core::fmt::Debug for MCPWM0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MCPWM0").finish()
}
}
#[doc = "Motor Control Pulse-Width Modulation 0"]
pub mod mcpwm0;
#[doc = "Motor Control Pulse-Width Modulation 1"]
pub type MCPWM1 = crate::Periph<mcpwm0::RegisterBlock, 0x3ff6_c000>;
impl core::fmt::Debug for MCPWM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MCPWM1").finish()
}
}
#[doc = "Motor Control Pulse-Width Modulation 1"]
pub use self::mcpwm0 as mcpwm1;
#[doc = "NRX Peripheral"]
pub type NRX = crate::Periph<nrx::RegisterBlock, 0x3ff5_cc00>;
impl core::fmt::Debug for NRX {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("NRX").finish()
}
}
#[doc = "NRX Peripheral"]
pub mod nrx;
#[doc = "Pulse Count Controller"]
pub type PCNT = crate::Periph<pcnt::RegisterBlock, 0x3ff5_7000>;
impl core::fmt::Debug for PCNT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PCNT").finish()
}
}
#[doc = "Pulse Count Controller"]
pub mod pcnt;
#[doc = "Remote Control"]
pub type RMT = crate::Periph<rmt::RegisterBlock, 0x3ff5_6000>;
impl core::fmt::Debug for RMT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RMT").finish()
}
}
#[doc = "Remote Control"]
pub mod rmt;
#[doc = "Hardware Random Number Generator"]
pub type RNG = crate::Periph<rng::RegisterBlock, 0x6003_5000>;
impl core::fmt::Debug for RNG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RNG").finish()
}
}
#[doc = "Hardware Random Number Generator"]
pub mod rng;
#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
pub type RSA = crate::Periph<rsa::RegisterBlock, 0x3ff0_2000>;
impl core::fmt::Debug for RSA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RSA").finish()
}
}
#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
pub mod rsa;
#[doc = "Real-Time Clock Control"]
pub type RTC_CNTL = crate::Periph<rtc_cntl::RegisterBlock, 0x3ff4_8000>;
impl core::fmt::Debug for RTC_CNTL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC_CNTL").finish()
}
}
#[doc = "Real-Time Clock Control"]
pub mod rtc_cntl;
#[doc = "Low-power Input/Output"]
pub type RTC_IO = crate::Periph<rtc_io::RegisterBlock, 0x3ff4_8400>;
impl core::fmt::Debug for RTC_IO {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC_IO").finish()
}
}
#[doc = "Low-power Input/Output"]
pub mod rtc_io;
#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
pub type RTC_I2C = crate::Periph<rtc_i2c::RegisterBlock, 0x3ff4_8c00>;
impl core::fmt::Debug for RTC_I2C {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC_I2C").finish()
}
}
#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
pub mod rtc_i2c;
#[doc = "SD/MMC Host Controller"]
pub type SDHOST = crate::Periph<sdhost::RegisterBlock, 0x3ff6_8000>;
impl core::fmt::Debug for SDHOST {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDHOST").finish()
}
}
#[doc = "SD/MMC Host Controller"]
pub mod sdhost;
#[doc = "SENS Peripheral"]
pub type SENS = crate::Periph<sens::RegisterBlock, 0x3ff4_8800>;
impl core::fmt::Debug for SENS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SENS").finish()
}
}
#[doc = "SENS Peripheral"]
pub mod sens;
#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
pub type SHA = crate::Periph<sha::RegisterBlock, 0x3ff0_3000>;
impl core::fmt::Debug for SHA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SHA").finish()
}
}
#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
pub mod sha;
#[doc = "SLC Peripheral"]
pub type SLC = crate::Periph<slc::RegisterBlock, 0x3ff5_8000>;
impl core::fmt::Debug for SLC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SLC").finish()
}
}
#[doc = "SLC Peripheral"]
pub mod slc;
#[doc = "SLCHOST Peripheral"]
pub type SLCHOST = crate::Periph<slchost::RegisterBlock, 0x3ff5_5000>;
impl core::fmt::Debug for SLCHOST {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SLCHOST").finish()
}
}
#[doc = "SLCHOST Peripheral"]
pub mod slchost;
#[doc = "SPI (Serial Peripheral Interface) Controller 0"]
pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x3ff4_3000>;
impl core::fmt::Debug for SPI0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI0").finish()
}
}
#[doc = "SPI (Serial Peripheral Interface) Controller 0"]
pub mod spi0;
#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
pub type SPI1 = crate::Periph<spi0::RegisterBlock, 0x3ff4_2000>;
impl core::fmt::Debug for SPI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI1").finish()
}
}
#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
pub use self::spi0 as spi1;
#[doc = "SPI (Serial Peripheral Interface) Controller 2"]
pub type SPI2 = crate::Periph<spi0::RegisterBlock, 0x3ff6_4000>;
impl core::fmt::Debug for SPI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI2").finish()
}
}
#[doc = "SPI (Serial Peripheral Interface) Controller 2"]
pub use self::spi0 as spi2;
#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
pub type SPI3 = crate::Periph<spi0::RegisterBlock, 0x3ff6_5000>;
impl core::fmt::Debug for SPI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI3").finish()
}
}
#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
pub use self::spi0 as spi3;
#[doc = "Timer Group 0"]
pub type TIMG0 = crate::Periph<timg0::RegisterBlock, 0x3ff5_f000>;
impl core::fmt::Debug for TIMG0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMG0").finish()
}
}
#[doc = "Timer Group 0"]
pub mod timg0;
#[doc = "Timer Group 1"]
pub type TIMG1 = crate::Periph<timg0::RegisterBlock, 0x3ff6_0000>;
impl core::fmt::Debug for TIMG1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMG1").finish()
}
}
#[doc = "Timer Group 1"]
pub use self::timg0 as timg1;
#[doc = "Two-Wire Automotive Interface"]
pub type TWAI0 = crate::Periph<twai0::RegisterBlock, 0x3ff6_b000>;
impl core::fmt::Debug for TWAI0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TWAI0").finish()
}
}
#[doc = "Two-Wire Automotive Interface"]
pub mod twai0;
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
pub type UART0 = crate::Periph<uart0::RegisterBlock, 0x3ff4_0000>;
impl core::fmt::Debug for UART0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART0").finish()
}
}
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
pub mod uart0;
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
pub type UART1 = crate::Periph<uart0::RegisterBlock, 0x3ff5_0000>;
impl core::fmt::Debug for UART1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART1").finish()
}
}
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
pub use self::uart0 as uart1;
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 2"]
pub type UART2 = crate::Periph<uart0::RegisterBlock, 0x3ff6_e000>;
impl core::fmt::Debug for UART2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART2").finish()
}
}
#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 2"]
pub use self::uart0 as uart2;
#[doc = "Dual mode Bluetooth Core peripheral"]
pub type BTDM = crate::Periph<btdm::RegisterBlock, 0x3ff7_1000>;
impl core::fmt::Debug for BTDM {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BTDM").finish()
}
}
#[doc = "Dual mode Bluetooth Core peripheral"]
pub mod btdm;
#[doc = "MAC controller for Wi-Fi peripheral"]
pub type WIFI = crate::Periph<wifi::RegisterBlock, 0x3ff7_3000>;
impl core::fmt::Debug for WIFI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WIFI").finish()
}
}
#[doc = "MAC controller for Wi-Fi peripheral"]
pub mod wifi;
#[doc = "Universal Host Controller Interface 0"]
pub type UHCI0 = crate::Periph<uhci0::RegisterBlock, 0x3ff5_4000>;
impl core::fmt::Debug for UHCI0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UHCI0").finish()
}
}
#[doc = "Universal Host Controller Interface 0"]
pub mod uhci0;
#[doc = "Universal Host Controller Interface 1"]
pub type UHCI1 = crate::Periph<uhci0::RegisterBlock, 0x3ff4_c000>;
impl core::fmt::Debug for UHCI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UHCI1").finish()
}
}
#[doc = "Universal Host Controller Interface 1"]
pub use self::uhci0 as uhci1;