efm32pg1b-pac 0.4.3

Peripheral access API for Silicon Labs EFM32PG1B microcontrollers
Documentation 
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///Register `CACHECMD` writer
pub type W = crate::W<CACHECMDrs>;
///Field `INVCACHE` writer - Invalidate Instruction Cache
pub type InvcacheW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `STARTPC` writer - Start Performance Counters
pub type StartpcW<'a, REG> = crate::BitWriter<'a, REG>;
///Field `STOPPC` writer - Stop Performance Counters
pub type StoppcW<'a, REG> = crate::BitWriter<'a, REG>;
impl core::fmt::Debug for crate::generic::Reg<CACHECMDrs> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    ///Bit 0 - Invalidate Instruction Cache
    #[inline(always)]
    pub fn invcache(&mut self) -> InvcacheW<'_, CACHECMDrs> {
        InvcacheW::new(self, 0)
    }
    ///Bit 1 - Start Performance Counters
    #[inline(always)]
    pub fn startpc(&mut self) -> StartpcW<'_, CACHECMDrs> {
        StartpcW::new(self, 1)
    }
    ///Bit 2 - Stop Performance Counters
    #[inline(always)]
    pub fn stoppc(&mut self) -> StoppcW<'_, CACHECMDrs> {
        StoppcW::new(self, 2)
    }
}
///Flash Cache Command Register
///
///You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cachecmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
pub struct CACHECMDrs;
impl crate::RegisterSpec for CACHECMDrs {
    type Ux = u32;
}
///`write(|w| ..)` method takes [`cachecmd::W`](W) writer structure
impl crate::Writable for CACHECMDrs {
    type Safety = crate::Unsafe;
}
///`reset()` method sets CACHECMD to value 0
impl crate::Resettable for CACHECMDrs {}