#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ch {
ptr: *mut u8,
}
unsafe impl Send for Ch {}
unsafe impl Sync for Ch {}
impl Ch {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "DMA channel configuration register (DMA_CCR)"]
#[inline(always)]
pub const fn cr(self) -> crate::common::Reg<regs::Cr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "DMA channel 1 number of data register"]
#[inline(always)]
pub const fn ndtr(self) -> crate::common::Reg<regs::Ndtr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "DMA channel 1 peripheral address register"]
#[inline(always)]
pub const fn par(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "DMA channel 1 memory address register"]
#[inline(always)]
pub const fn mar(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
}
#[doc = "DMA controller"]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dma {
ptr: *mut u8,
}
unsafe impl Send for Dma {}
unsafe impl Sync for Dma {}
impl Dma {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "DMA interrupt status register (DMA_ISR)"]
#[inline(always)]
pub const fn isr(self) -> crate::common::Reg<regs::Isr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
#[inline(always)]
pub const fn ifcr(self) -> crate::common::Reg<regs::Isr, crate::common::W> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
#[inline(always)]
pub const fn ch(self, n: usize) -> Ch {
assert!(n < 8usize);
unsafe { Ch::from_ptr(self.ptr.add(0x08usize + n * 20usize) as _) }
}
#[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"]
#[inline(always)]
pub const fn ech(self, n: usize) -> Ch {
assert!(n < 3usize);
unsafe { Ch::from_ptr(self.ptr.add(0xa0usize + n * 20usize) as _) }
}
#[doc = "DMA interrupt status register (DMA_ISR)"]
#[inline(always)]
pub const fn eisr(self) -> crate::common::Reg<regs::Isr, crate::common::R> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd0usize) as _) }
}
#[doc = "DMA interrupt flag clear register (DMA_IFCR)"]
#[inline(always)]
pub const fn eifcr(self) -> crate::common::Reg<regs::Isr, crate::common::W> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0xd4usize) as _) }
}
}
pub mod regs {
#[doc = "DMA channel configuration register (DMA_CCR)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Cr(pub u32);
impl Cr {
#[doc = "Channel enable"]
#[inline(always)]
pub const fn en(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "Channel enable"]
#[inline(always)]
pub fn set_en(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "Transfer complete interrupt enable"]
#[inline(always)]
pub const fn tcie(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "Transfer complete interrupt enable"]
#[inline(always)]
pub fn set_tcie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "Half Transfer interrupt enable"]
#[inline(always)]
pub const fn htie(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "Half Transfer interrupt enable"]
#[inline(always)]
pub fn set_htie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "Transfer error interrupt enable"]
#[inline(always)]
pub const fn teie(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "Transfer error interrupt enable"]
#[inline(always)]
pub fn set_teie(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "Data transfer direction"]
#[inline(always)]
pub const fn dir(&self) -> super::vals::Dir {
let val = (self.0 >> 4usize) & 0x01;
super::vals::Dir::from_bits(val as u8)
}
#[doc = "Data transfer direction"]
#[inline(always)]
pub fn set_dir(&mut self, val: super::vals::Dir) {
self.0 = (self.0 & !(0x01 << 4usize)) | (((val.to_bits() as u32) & 0x01) << 4usize);
}
#[doc = "Circular mode enabled"]
#[inline(always)]
pub const fn circ(&self) -> bool {
let val = (self.0 >> 5usize) & 0x01;
val != 0
}
#[doc = "Circular mode enabled"]
#[inline(always)]
pub fn set_circ(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
}
#[doc = "Peripheral increment mode enabled"]
#[inline(always)]
pub const fn pinc(&self) -> bool {
let val = (self.0 >> 6usize) & 0x01;
val != 0
}
#[doc = "Peripheral increment mode enabled"]
#[inline(always)]
pub fn set_pinc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
}
#[doc = "Memory increment mode enabled"]
#[inline(always)]
pub const fn minc(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Memory increment mode enabled"]
#[inline(always)]
pub fn set_minc(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
#[doc = "Peripheral size"]
#[inline(always)]
pub const fn psize(&self) -> super::vals::Size {
let val = (self.0 >> 8usize) & 0x03;
super::vals::Size::from_bits(val as u8)
}
#[doc = "Peripheral size"]
#[inline(always)]
pub fn set_psize(&mut self, val: super::vals::Size) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val.to_bits() as u32) & 0x03) << 8usize);
}
#[doc = "Memory size"]
#[inline(always)]
pub const fn msize(&self) -> super::vals::Size {
let val = (self.0 >> 10usize) & 0x03;
super::vals::Size::from_bits(val as u8)
}
#[doc = "Memory size"]
#[inline(always)]
pub fn set_msize(&mut self, val: super::vals::Size) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val.to_bits() as u32) & 0x03) << 10usize);
}
#[doc = "Channel Priority level"]
#[inline(always)]
pub const fn pl(&self) -> super::vals::Pl {
let val = (self.0 >> 12usize) & 0x03;
super::vals::Pl::from_bits(val as u8)
}
#[doc = "Channel Priority level"]
#[inline(always)]
pub fn set_pl(&mut self, val: super::vals::Pl) {
self.0 = (self.0 & !(0x03 << 12usize)) | (((val.to_bits() as u32) & 0x03) << 12usize);
}
#[doc = "Memory to memory mode enabled"]
#[inline(always)]
pub const fn mem2mem(&self) -> bool {
let val = (self.0 >> 14usize) & 0x01;
val != 0
}
#[doc = "Memory to memory mode enabled"]
#[inline(always)]
pub fn set_mem2mem(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
}
}
impl Default for Cr {
#[inline(always)]
fn default() -> Cr {
Cr(0)
}
}
#[doc = "DMA interrupt status register (DMA_ISR)"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Isr(pub u32);
impl Isr {
#[doc = "Channel 1 Global interrupt flag"]
#[inline(always)]
pub const fn gif(&self, n: usize) -> bool {
assert!(n < 8usize);
let offs = 0usize + n * 4usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Channel 1 Global interrupt flag"]
#[inline(always)]
pub fn set_gif(&mut self, n: usize, val: bool) {
assert!(n < 8usize);
let offs = 0usize + n * 4usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Channel 1 Transfer Complete flag"]
#[inline(always)]
pub const fn tcif(&self, n: usize) -> bool {
assert!(n < 8usize);
let offs = 1usize + n * 4usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Channel 1 Transfer Complete flag"]
#[inline(always)]
pub fn set_tcif(&mut self, n: usize, val: bool) {
assert!(n < 8usize);
let offs = 1usize + n * 4usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Channel 1 Half Transfer Complete flag"]
#[inline(always)]
pub const fn htif(&self, n: usize) -> bool {
assert!(n < 8usize);
let offs = 2usize + n * 4usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Channel 1 Half Transfer Complete flag"]
#[inline(always)]
pub fn set_htif(&mut self, n: usize, val: bool) {
assert!(n < 8usize);
let offs = 2usize + n * 4usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
#[doc = "Channel 1 Transfer Error flag"]
#[inline(always)]
pub const fn teif(&self, n: usize) -> bool {
assert!(n < 8usize);
let offs = 3usize + n * 4usize;
let val = (self.0 >> offs) & 0x01;
val != 0
}
#[doc = "Channel 1 Transfer Error flag"]
#[inline(always)]
pub fn set_teif(&mut self, n: usize, val: bool) {
assert!(n < 8usize);
let offs = 3usize + n * 4usize;
self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs);
}
}
impl Default for Isr {
#[inline(always)]
fn default() -> Isr {
Isr(0)
}
}
#[doc = "DMA channel 1 number of data register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ndtr(pub u32);
impl Ndtr {
#[doc = "Number of data to transfer"]
#[inline(always)]
pub const fn ndt(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Number of data to transfer"]
#[inline(always)]
pub fn set_ndt(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Ndtr {
#[inline(always)]
fn default() -> Ndtr {
Ndtr(0)
}
}
}
pub mod vals {
#[repr(u8)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub enum Dir {
#[doc = "Read from peripheral"]
FROMPERIPHERAL = 0x0,
#[doc = "Read from memory"]
FROMMEMORY = 0x01,
}
impl Dir {
#[inline(always)]
pub const fn from_bits(val: u8) -> Dir {
unsafe { core::mem::transmute(val & 0x01) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Dir {
#[inline(always)]
fn from(val: u8) -> Dir {
Dir::from_bits(val)
}
}
impl From<Dir> for u8 {
#[inline(always)]
fn from(val: Dir) -> u8 {
Dir::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub enum Pl {
#[doc = "Low priority"]
LOW = 0x0,
#[doc = "Medium priority"]
MEDIUM = 0x01,
#[doc = "High priority"]
HIGH = 0x02,
#[doc = "Very high priority"]
VERYHIGH = 0x03,
}
impl Pl {
#[inline(always)]
pub const fn from_bits(val: u8) -> Pl {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Pl {
#[inline(always)]
fn from(val: u8) -> Pl {
Pl::from_bits(val)
}
}
impl From<Pl> for u8 {
#[inline(always)]
fn from(val: Pl) -> u8 {
Pl::to_bits(val)
}
}
#[repr(u8)]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub enum Size {
#[doc = "8-bit size"]
BITS8 = 0x0,
#[doc = "16-bit size"]
BITS16 = 0x01,
#[doc = "32-bit size"]
BITS32 = 0x02,
_RESERVED_3 = 0x03,
}
impl Size {
#[inline(always)]
pub const fn from_bits(val: u8) -> Size {
unsafe { core::mem::transmute(val & 0x03) }
}
#[inline(always)]
pub const fn to_bits(self) -> u8 {
unsafe { core::mem::transmute(self) }
}
}
impl From<u8> for Size {
#[inline(always)]
fn from(val: u8) -> Size {
Size::from_bits(val)
}
}
impl From<Size> for u8 {
#[inline(always)]
fn from(val: Size) -> u8 {
Size::to_bits(val)
}
}
}