#![allow(clippy::missing_safety_doc)]
#![allow(clippy::identity_op)]
#![allow(clippy::unnecessary_cast)]
#![allow(clippy::erasing_op)]
#[doc = "Alternate function I/O."]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Afio {
ptr: *mut u8,
}
unsafe impl Send for Afio {}
unsafe impl Sync for Afio {}
impl Afio {
#[inline(always)]
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
Self { ptr: ptr as _ }
}
#[inline(always)]
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Event Control Register (AFIO_ECR)."]
#[inline(always)]
pub const fn ecr(self) -> crate::common::Reg<regs::Ecr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR1)."]
#[inline(always)]
pub const fn pcfr1(self) -> crate::common::Reg<regs::Pcfr1, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x04usize) as _) }
}
#[doc = "External interrupt configuration registers (AFIO_EXTICRs)."]
#[inline(always)]
pub const fn exticr(self, n: usize) -> crate::common::Reg<regs::Exticr, crate::common::RW> {
assert!(n < 4usize);
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize + n * 4usize) as _) }
}
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR2)."]
#[inline(always)]
pub const fn pcfr2(self) -> crate::common::Reg<regs::Pcfr2, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
}
}
pub mod regs {
#[doc = "Event Control Register (AFIO_ECR)."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Ecr(pub u32);
impl Ecr {
#[doc = "Pin selection."]
#[inline(always)]
pub const fn pin(&self) -> u8 {
let val = (self.0 >> 0usize) & 0x0f;
val as u8
}
#[doc = "Pin selection."]
#[inline(always)]
pub fn set_pin(&mut self, val: u8) {
self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
}
#[doc = "Port selection."]
#[inline(always)]
pub const fn port(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x07;
val as u8
}
#[doc = "Port selection."]
#[inline(always)]
pub fn set_port(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
}
#[doc = "Event Output Enable."]
#[inline(always)]
pub const fn evoe(&self) -> bool {
let val = (self.0 >> 7usize) & 0x01;
val != 0
}
#[doc = "Event Output Enable."]
#[inline(always)]
pub fn set_evoe(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
}
}
impl Default for Ecr {
#[inline(always)]
fn default() -> Ecr {
Ecr(0)
}
}
#[doc = "External interrupt configuration register (AFIO_EXTICRx)."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Exticr(pub u32);
impl Exticr {
#[doc = "EXTI configuration."]
#[inline(always)]
pub const fn exti(&self, n: usize) -> u8 {
assert!(n < 4usize);
let offs = 0usize + n * 4usize;
let val = (self.0 >> offs) & 0x0f;
val as u8
}
#[doc = "EXTI configuration."]
#[inline(always)]
pub fn set_exti(&mut self, n: usize, val: u8) {
assert!(n < 4usize);
let offs = 0usize + n * 4usize;
self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs);
}
}
impl Default for Exticr {
#[inline(always)]
fn default() -> Exticr {
Exticr(0)
}
}
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR1)."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcfr1(pub u32);
impl Pcfr1 {
#[doc = "SPI1 remapping."]
#[inline(always)]
pub const fn spi1_rm(&self) -> bool {
let val = (self.0 >> 0usize) & 0x01;
val != 0
}
#[doc = "SPI1 remapping."]
#[inline(always)]
pub fn set_spi1_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
}
#[doc = "I2C1 remapping."]
#[inline(always)]
pub const fn i2c1_rm(&self) -> bool {
let val = (self.0 >> 1usize) & 0x01;
val != 0
}
#[doc = "I2C1 remapping."]
#[inline(always)]
pub fn set_i2c1_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
}
#[doc = "USART1 remapping."]
#[inline(always)]
pub const fn usart1_rm(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "USART1 remapping."]
#[inline(always)]
pub fn set_usart1_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "USART2 remapping."]
#[inline(always)]
pub const fn usart2_rm(&self) -> bool {
let val = (self.0 >> 3usize) & 0x01;
val != 0
}
#[doc = "USART2 remapping."]
#[inline(always)]
pub fn set_usart2_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
}
#[doc = "USART3 remapping."]
#[inline(always)]
pub const fn usart3_rm(&self) -> u8 {
let val = (self.0 >> 4usize) & 0x03;
val as u8
}
#[doc = "USART3 remapping."]
#[inline(always)]
pub fn set_usart3_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 4usize)) | (((val as u32) & 0x03) << 4usize);
}
#[doc = "TIM1 remapping."]
#[inline(always)]
pub const fn tim1_rm(&self) -> u8 {
let val = (self.0 >> 6usize) & 0x03;
val as u8
}
#[doc = "TIM1 remapping."]
#[inline(always)]
pub fn set_tim1_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 6usize)) | (((val as u32) & 0x03) << 6usize);
}
#[doc = "TIM2 remapping."]
#[inline(always)]
pub const fn tim2_rm(&self) -> u8 {
let val = (self.0 >> 8usize) & 0x03;
val as u8
}
#[doc = "TIM2 remapping."]
#[inline(always)]
pub fn set_tim2_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize);
}
#[doc = "TIM3 remapping."]
#[inline(always)]
pub const fn tim3_rm(&self) -> u8 {
let val = (self.0 >> 10usize) & 0x03;
val as u8
}
#[doc = "TIM3 remapping."]
#[inline(always)]
pub fn set_tim3_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
}
#[doc = "TIM4 remapping."]
#[inline(always)]
pub const fn tim4_rm(&self) -> bool {
let val = (self.0 >> 12usize) & 0x01;
val != 0
}
#[doc = "TIM4 remapping."]
#[inline(always)]
pub fn set_tim4_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
}
#[doc = "CAN1 remapping."]
#[inline(always)]
pub const fn can1_rm(&self) -> u8 {
let val = (self.0 >> 13usize) & 0x03;
val as u8
}
#[doc = "CAN1 remapping."]
#[inline(always)]
pub fn set_can1_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 13usize)) | (((val as u32) & 0x03) << 13usize);
}
#[doc = "Port D0/Port D1 mapping on OSCIN/OSCOUT."]
#[inline(always)]
pub const fn pd01_rm(&self) -> bool {
let val = (self.0 >> 15usize) & 0x01;
val != 0
}
#[doc = "Port D0/Port D1 mapping on OSCIN/OSCOUT."]
#[inline(always)]
pub fn set_pd01_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
}
#[doc = "TIM5 channel4 internal remap."]
#[inline(always)]
pub const fn tim5ch4_rm(&self) -> bool {
let val = (self.0 >> 16usize) & 0x01;
val != 0
}
#[doc = "TIM5 channel4 internal remap."]
#[inline(always)]
pub fn set_tim5ch4_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
}
#[doc = "ADC 1 External trigger injected conversion remapping."]
#[inline(always)]
pub const fn adc1_etrginj_rm(&self) -> bool {
let val = (self.0 >> 17usize) & 0x01;
val != 0
}
#[doc = "ADC 1 External trigger injected conversion remapping."]
#[inline(always)]
pub fn set_adc1_etrginj_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
}
#[doc = "ADC 1 external trigger regular conversion remapping."]
#[inline(always)]
pub const fn adc1_etrgreg_rm(&self) -> bool {
let val = (self.0 >> 18usize) & 0x01;
val != 0
}
#[doc = "ADC 1 external trigger regular conversion remapping."]
#[inline(always)]
pub fn set_adc1_etrgreg_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
}
#[doc = "ADC 2 External trigger injected conversion remapping."]
#[inline(always)]
pub const fn adc2_etrginj_rm(&self) -> bool {
let val = (self.0 >> 19usize) & 0x01;
val != 0
}
#[doc = "ADC 2 External trigger injected conversion remapping."]
#[inline(always)]
pub fn set_adc2_etrginj_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
}
#[doc = "ADC 2 external trigger regular conversion remapping."]
#[inline(always)]
pub const fn adc2_etrgreg_rm(&self) -> bool {
let val = (self.0 >> 20usize) & 0x01;
val != 0
}
#[doc = "ADC 2 external trigger regular conversion remapping."]
#[inline(always)]
pub fn set_adc2_etrgreg_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
}
#[doc = "Ethernet remapping."]
#[inline(always)]
pub const fn eth_rm(&self) -> bool {
let val = (self.0 >> 21usize) & 0x01;
val != 0
}
#[doc = "Ethernet remapping."]
#[inline(always)]
pub fn set_eth_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
}
#[doc = "CAN2 remapping."]
#[inline(always)]
pub const fn can2_rm(&self) -> bool {
let val = (self.0 >> 22usize) & 0x01;
val != 0
}
#[doc = "CAN2 remapping."]
#[inline(always)]
pub fn set_can2_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
}
#[doc = "MII_RMII_SEL."]
#[inline(always)]
pub const fn mii_rmii_sel(&self) -> bool {
let val = (self.0 >> 23usize) & 0x01;
val != 0
}
#[doc = "MII_RMII_SEL."]
#[inline(always)]
pub fn set_mii_rmii_sel(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
}
#[doc = "Serial wire JTAG configuration."]
#[inline(always)]
pub const fn swcfg(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x07;
val as u8
}
#[doc = "Serial wire JTAG configuration."]
#[inline(always)]
pub fn set_swcfg(&mut self, val: u8) {
self.0 = (self.0 & !(0x07 << 24usize)) | (((val as u32) & 0x07) << 24usize);
}
#[doc = "SPI3 remapping."]
#[inline(always)]
pub const fn spi3_rm(&self) -> bool {
let val = (self.0 >> 28usize) & 0x01;
val != 0
}
#[doc = "SPI3 remapping."]
#[inline(always)]
pub fn set_spi3_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
}
#[doc = "TIM2 internally triggers 1 remapping."]
#[inline(always)]
pub const fn tim2itra_rm(&self) -> bool {
let val = (self.0 >> 29usize) & 0x01;
val != 0
}
#[doc = "TIM2 internally triggers 1 remapping."]
#[inline(always)]
pub fn set_tim2itra_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
}
#[doc = "Ethernet PTP_PPS remapping."]
#[inline(always)]
pub const fn ptp_ppsp_rm(&self) -> bool {
let val = (self.0 >> 30usize) & 0x01;
val != 0
}
#[doc = "Ethernet PTP_PPS remapping."]
#[inline(always)]
pub fn set_ptp_ppsp_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
}
}
impl Default for Pcfr1 {
#[inline(always)]
fn default() -> Pcfr1 {
Pcfr1(0)
}
}
#[doc = "AF remap and debug I/O configuration register (AFIO_PCFR2)."]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Pcfr2(pub u32);
impl Pcfr2 {
#[doc = "TIM8 remapping."]
#[inline(always)]
pub const fn tim8_rm(&self) -> bool {
let val = (self.0 >> 2usize) & 0x01;
val != 0
}
#[doc = "TIM8 remapping."]
#[inline(always)]
pub fn set_tim8_rm(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
}
#[doc = "TIM9 remapping."]
#[inline(always)]
pub const fn tim9_rm(&self) -> u8 {
let val = (self.0 >> 3usize) & 0x03;
val as u8
}
#[doc = "TIM9 remapping."]
#[inline(always)]
pub fn set_tim9_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 3usize)) | (((val as u32) & 0x03) << 3usize);
}
#[doc = "TIM10 remapping."]
#[inline(always)]
pub const fn tim10_rm(&self) -> u8 {
let val = (self.0 >> 5usize) & 0x03;
val as u8
}
#[doc = "TIM10 remapping."]
#[inline(always)]
pub fn set_tim10_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 5usize)) | (((val as u32) & 0x03) << 5usize);
}
#[doc = "FSMC_NADV."]
#[inline(always)]
pub const fn fsmc_nadv(&self) -> bool {
let val = (self.0 >> 10usize) & 0x01;
val != 0
}
#[doc = "FSMC_NADV."]
#[inline(always)]
pub fn set_fsmc_nadv(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
}
#[doc = "USART4 remapping."]
#[inline(always)]
pub const fn usart4_rm(&self) -> u8 {
let val = (self.0 >> 16usize) & 0x03;
val as u8
}
#[doc = "USART4 remapping."]
#[inline(always)]
pub fn set_usart4_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 16usize)) | (((val as u32) & 0x03) << 16usize);
}
#[doc = "USART5 remapping."]
#[inline(always)]
pub const fn usart5_rm(&self) -> u8 {
let val = (self.0 >> 18usize) & 0x03;
val as u8
}
#[doc = "USART5 remapping."]
#[inline(always)]
pub fn set_usart5_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize);
}
#[doc = "USART6 remapping."]
#[inline(always)]
pub const fn usart6_rm(&self) -> u8 {
let val = (self.0 >> 20usize) & 0x03;
val as u8
}
#[doc = "USART6 remapping."]
#[inline(always)]
pub fn set_usart6_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
}
#[doc = "USART7 remapping."]
#[inline(always)]
pub const fn usart7_rm(&self) -> u8 {
let val = (self.0 >> 22usize) & 0x03;
val as u8
}
#[doc = "USART7 remapping."]
#[inline(always)]
pub fn set_usart7_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize);
}
#[doc = "USART8 remapping."]
#[inline(always)]
pub const fn usart8_rm(&self) -> u8 {
let val = (self.0 >> 24usize) & 0x03;
val as u8
}
#[doc = "USART8 remapping."]
#[inline(always)]
pub fn set_usart8_rm(&mut self, val: u8) {
self.0 = (self.0 & !(0x03 << 24usize)) | (((val as u32) & 0x03) << 24usize);
}
#[doc = "USART1 remapping."]
#[inline(always)]
pub const fn usart1_rm2(&self) -> bool {
let val = (self.0 >> 26usize) & 0x01;
val != 0
}
#[doc = "USART1 remapping."]
#[inline(always)]
pub fn set_usart1_rm2(&mut self, val: bool) {
self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
}
}
impl Default for Pcfr2 {
#[inline(always)]
fn default() -> Pcfr2 {
Pcfr2(0)
}
}
}