---
source: crates/celox/tests/false_loop.rs
expression: sir_output
---
=== Evaluation Flip-Flops (eval_apply_ffs) ===
=== Evaluation Flip-Flops (eval_only_ffs) ===
=== Application Flip-Flops (apply_ffs) ===
=== Evaluation Combinational Logic (eval_comb) ===
Execution Unit 0:
Entry Block: 0
Registers:
r0: bit<64>
r1: bit<64>
r2: bit<64>
r3: bit<1>
r5: bit<1>
r9: bit<31>
r10: logic<1>
r11: logic<32>
r13: logic<1>
r14: bit<1>
r15: logic<1>
r16: logic<1>
r17: bit<1>
r19: bit<1>
r28: bit<1>
r29: bit<1>
r30: bit<1>
r39: bit<1>
r40: bit<1>
r41: bit<1>
r50: bit<1>
r51: bit<1>
r52: bit<1>
r61: bit<1>
r62: bit<1>
r63: bit<1>
r72: bit<1>
r73: bit<1>
r74: bit<1>
r83: bit<1>
r84: bit<1>
r85: bit<1>
r94: bit<1>
r95: bit<1>
r96: bit<1>
r105: bit<1>
r106: bit<1>
r107: bit<1>
r116: bit<1>
r117: bit<1>
r118: bit<1>
r127: bit<1>
r128: bit<1>
r129: bit<1>
r138: bit<1>
r139: bit<1>
r140: bit<1>
r149: bit<1>
r150: bit<1>
r151: bit<1>
r160: bit<1>
r161: bit<1>
r162: bit<1>
r171: bit<1>
r172: bit<1>
r173: bit<1>
r182: bit<1>
r183: bit<1>
r184: bit<1>
r193: bit<1>
r194: bit<1>
r195: bit<1>
r204: bit<1>
r205: bit<1>
r206: bit<1>
r215: bit<1>
r216: bit<1>
r217: bit<1>
r226: bit<1>
r227: bit<1>
r228: bit<64>
r229: bit<64>
r230: logic<20>
r231: logic<20>
r232: bit<20>
r233: bit<20>
b0:
r0 = SIRValue(0x0)
r1 = SIRValue(0x13)
Jump(b1 [r0])
b1:
params: [r2]
r3 = r2 LtU r1
Branch(r3 ? b2 : b4)
b2:
r5 = Load(addr=v (region=0), offset=3, bits=1)
r10 = Load(addr=i (region=0), offset=0, bits=1)
r19 = Load(addr=v (region=0), offset=4, bits=1)
r30 = Load(addr=v (region=0), offset=2, bits=1)
r41 = Load(addr=v (region=0), offset=1, bits=1)
r52 = Load(addr=v (region=0), offset=5, bits=1)
r63 = Load(addr=v (region=0), offset=6, bits=1)
r74 = Load(addr=v (region=0), offset=7, bits=1)
r9 = SIRValue(0x0)
r11 = Concat(r9, r10)
r85 = Load(addr=v (region=0), offset=8, bits=1)
r13 = r11 Shr r0
r14 = SIRValue(0x1)
r15 = r13 And r14
r16 = Ident r15
r17 = r5 Ne r16
r96 = Load(addr=v (region=0), offset=9, bits=1)
r28 = r19 Ne r16
r107 = Load(addr=v (region=0), offset=10, bits=1)
r29 = r17 Or r28
r39 = r30 Ne r16
r118 = Load(addr=v (region=0), offset=11, bits=1)
r40 = r29 Or r39
r50 = r41 Ne r16
r129 = Load(addr=v (region=0), offset=12, bits=1)
r51 = r40 Or r50
r61 = r52 Ne r16
r140 = Load(addr=v (region=0), offset=13, bits=1)
r62 = r51 Or r61
r72 = r63 Ne r16
r151 = Load(addr=v (region=0), offset=14, bits=1)
r73 = r62 Or r72
r83 = r74 Ne r16
r162 = Load(addr=v (region=0), offset=15, bits=1)
r84 = r73 Or r83
r94 = r85 Ne r16
r173 = Load(addr=v (region=0), offset=16, bits=1)
r95 = r84 Or r94
r105 = r96 Ne r16
r184 = Load(addr=v (region=0), offset=17, bits=1)
r106 = r95 Or r105
r116 = r107 Ne r16
r195 = Load(addr=v (region=0), offset=18, bits=1)
r117 = r106 Or r116
r127 = r118 Ne r16
r206 = Load(addr=v (region=0), offset=19, bits=1)
r128 = r117 Or r127
r138 = r129 Ne r16
r217 = Load(addr=v (region=0), offset=0, bits=1)
r139 = r128 Or r138
r149 = r140 Ne r16
r150 = r139 Or r149
r160 = r151 Ne r16
r161 = r150 Or r160
r171 = r162 Ne r16
r172 = r161 Or r171
r182 = r173 Ne r16
r183 = r172 Or r182
r193 = r184 Ne r16
r194 = r183 Or r193
r204 = r195 Ne r16
r205 = r194 Or r204
r215 = r206 Ne r16
r216 = r205 Or r215
r226 = r217 Ne r16
r227 = r216 Or r226
r232 = SIRValue(0x0)
r233 = SIRValue(0xfffff)
r231 = Mux(cond=r16, then=r233, else=r232)
Store(addr=v (region=0), offset=0, bits=20, src_reg = 231)
r228 = SIRValue(0x1)
r229 = r2 Add r228
Branch(r227 ? b1 [r229] : b3)
b3:
r230 = Load(addr=v (region=0), offset=0, bits=20)
Store(addr=o (region=0), offset=0, bits=20, src_reg = 230)
Return
b4:
Error(2000)