celox 0.4.1

Celox HDL Simulator
Documentation 
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---
source: crates/celox/tests/basic.rs
expression: output
---
=== Evaluation Flip-Flops (eval_apply_ffs) ===

=== Evaluation Flip-Flops (eval_only_ffs) ===

=== Application Flip-Flops (apply_ffs) ===

=== Evaluation Combinational Logic (eval_comb) ===
Execution Unit 0:
  Entry Block: 0
  Registers:
    r0: logic<32>
    r1: logic<32>
    r2: logic<32>
    r3: bit<32>
    r4: logic<32>
    r5: bit<32>
    r6: logic<32>
  b0:
    r0 = Load(addr=a (region=0), offset=0, bits=32)
    r1 = Load(addr=b (region=0), offset=0, bits=32)
    r2 = r0 Add r1
    r3 = SIRValue(0x1)
    r4 = r2 And r3
    Store(addr=x (region=0), offset=0, bits=32, src_reg = 4)
    r5 = SIRValue(0x2)
    r6 = r2 Or r5
    Store(addr=y (region=0), offset=0, bits=32, src_reg = 6)
    Return