#[doc = "Register `RTCPS1CTL` reader"]
pub type R = crate::R<Rtcps1ctlSpec>;
#[doc = "Register `RTCPS1CTL` writer"]
pub type W = crate::W<Rtcps1ctlSpec>;
#[doc = "Field `RT1PSIFG` reader - RTC Prescale Timer 1 Interrupt Flag"]
pub type Rt1psifgR = crate::BitReader;
#[doc = "Field `RT1PSIFG` writer - RTC Prescale Timer 1 Interrupt Flag"]
pub type Rt1psifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT1PSIE` reader - RTC Prescale Timer 1 Interrupt Enable Flag"]
pub type Rt1psieR = crate::BitReader;
#[doc = "Field `RT1PSIE` writer - RTC Prescale Timer 1 Interrupt Enable Flag"]
pub type Rt1psieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 1 Interrupt Interval Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt1ip {
#[doc = "0: RTC Prescale Timer 1 Interrupt Interval /2"]
Rt1ip0 = 0,
#[doc = "1: RTC Prescale Timer 1 Interrupt Interval /4"]
Rt1ip1 = 1,
#[doc = "2: RTC Prescale Timer 1 Interrupt Interval /8"]
Rt1ip2 = 2,
#[doc = "3: RTC Prescale Timer 1 Interrupt Interval /16"]
Rt1ip3 = 3,
#[doc = "4: RTC Prescale Timer 1 Interrupt Interval /32"]
Rt1ip4 = 4,
#[doc = "5: RTC Prescale Timer 1 Interrupt Interval /64"]
Rt1ip5 = 5,
#[doc = "6: RTC Prescale Timer 1 Interrupt Interval /128"]
Rt1ip6 = 6,
#[doc = "7: RTC Prescale Timer 1 Interrupt Interval /256"]
Rt1ip7 = 7,
}
impl From<Rt1ip> for u8 {
#[inline(always)]
fn from(variant: Rt1ip) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt1ip {
type Ux = u8;
}
impl crate::IsEnum for Rt1ip {}
#[doc = "Field `RT1IP` reader - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
pub type Rt1ipR = crate::FieldReader<Rt1ip>;
impl Rt1ipR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt1ip {
match self.bits {
0 => Rt1ip::Rt1ip0,
1 => Rt1ip::Rt1ip1,
2 => Rt1ip::Rt1ip2,
3 => Rt1ip::Rt1ip3,
4 => Rt1ip::Rt1ip4,
5 => Rt1ip::Rt1ip5,
6 => Rt1ip::Rt1ip6,
7 => Rt1ip::Rt1ip7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /2"]
#[inline(always)]
pub fn is_rt1ip_0(&self) -> bool {
*self == Rt1ip::Rt1ip0
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /4"]
#[inline(always)]
pub fn is_rt1ip_1(&self) -> bool {
*self == Rt1ip::Rt1ip1
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /8"]
#[inline(always)]
pub fn is_rt1ip_2(&self) -> bool {
*self == Rt1ip::Rt1ip2
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /16"]
#[inline(always)]
pub fn is_rt1ip_3(&self) -> bool {
*self == Rt1ip::Rt1ip3
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /32"]
#[inline(always)]
pub fn is_rt1ip_4(&self) -> bool {
*self == Rt1ip::Rt1ip4
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /64"]
#[inline(always)]
pub fn is_rt1ip_5(&self) -> bool {
*self == Rt1ip::Rt1ip5
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /128"]
#[inline(always)]
pub fn is_rt1ip_6(&self) -> bool {
*self == Rt1ip::Rt1ip6
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /256"]
#[inline(always)]
pub fn is_rt1ip_7(&self) -> bool {
*self == Rt1ip::Rt1ip7
}
}
#[doc = "Field `RT1IP` writer - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
pub type Rt1ipW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt1ip, crate::Safe>;
impl<'a, REG> Rt1ipW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 1 Interrupt Interval /2"]
#[inline(always)]
pub fn rt1ip_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip0)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /4"]
#[inline(always)]
pub fn rt1ip_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip1)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /8"]
#[inline(always)]
pub fn rt1ip_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip2)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /16"]
#[inline(always)]
pub fn rt1ip_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip3)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /32"]
#[inline(always)]
pub fn rt1ip_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip4)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /64"]
#[inline(always)]
pub fn rt1ip_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip5)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /128"]
#[inline(always)]
pub fn rt1ip_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip6)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /256"]
#[inline(always)]
pub fn rt1ip_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip7)
}
}
#[doc = "Field `RT1PSHOLD` reader - RTC Prescale Timer 1 Hold"]
pub type Rt1psholdR = crate::BitReader;
#[doc = "Field `RT1PSHOLD` writer - RTC Prescale Timer 1 Hold"]
pub type Rt1psholdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 1 Clock Divide Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt1psdiv {
#[doc = "0: RTC Prescale Timer 1 Clock Divide /2"]
Rt1psdiv0 = 0,
#[doc = "1: RTC Prescale Timer 1 Clock Divide /4"]
Rt1psdiv1 = 1,
#[doc = "2: RTC Prescale Timer 1 Clock Divide /8"]
Rt1psdiv2 = 2,
#[doc = "3: RTC Prescale Timer 1 Clock Divide /16"]
Rt1psdiv3 = 3,
#[doc = "4: RTC Prescale Timer 1 Clock Divide /32"]
Rt1psdiv4 = 4,
#[doc = "5: RTC Prescale Timer 1 Clock Divide /64"]
Rt1psdiv5 = 5,
#[doc = "6: RTC Prescale Timer 1 Clock Divide /128"]
Rt1psdiv6 = 6,
#[doc = "7: RTC Prescale Timer 1 Clock Divide /256"]
Rt1psdiv7 = 7,
}
impl From<Rt1psdiv> for u8 {
#[inline(always)]
fn from(variant: Rt1psdiv) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt1psdiv {
type Ux = u8;
}
impl crate::IsEnum for Rt1psdiv {}
#[doc = "Field `RT1PSDIV` reader - RTC Prescale Timer 1 Clock Divide Bit: 2"]
pub type Rt1psdivR = crate::FieldReader<Rt1psdiv>;
impl Rt1psdivR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt1psdiv {
match self.bits {
0 => Rt1psdiv::Rt1psdiv0,
1 => Rt1psdiv::Rt1psdiv1,
2 => Rt1psdiv::Rt1psdiv2,
3 => Rt1psdiv::Rt1psdiv3,
4 => Rt1psdiv::Rt1psdiv4,
5 => Rt1psdiv::Rt1psdiv5,
6 => Rt1psdiv::Rt1psdiv6,
7 => Rt1psdiv::Rt1psdiv7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 1 Clock Divide /2"]
#[inline(always)]
pub fn is_rt1psdiv_0(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv0
}
#[doc = "RTC Prescale Timer 1 Clock Divide /4"]
#[inline(always)]
pub fn is_rt1psdiv_1(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv1
}
#[doc = "RTC Prescale Timer 1 Clock Divide /8"]
#[inline(always)]
pub fn is_rt1psdiv_2(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv2
}
#[doc = "RTC Prescale Timer 1 Clock Divide /16"]
#[inline(always)]
pub fn is_rt1psdiv_3(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv3
}
#[doc = "RTC Prescale Timer 1 Clock Divide /32"]
#[inline(always)]
pub fn is_rt1psdiv_4(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv4
}
#[doc = "RTC Prescale Timer 1 Clock Divide /64"]
#[inline(always)]
pub fn is_rt1psdiv_5(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv5
}
#[doc = "RTC Prescale Timer 1 Clock Divide /128"]
#[inline(always)]
pub fn is_rt1psdiv_6(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv6
}
#[doc = "RTC Prescale Timer 1 Clock Divide /256"]
#[inline(always)]
pub fn is_rt1psdiv_7(&self) -> bool {
*self == Rt1psdiv::Rt1psdiv7
}
}
#[doc = "Field `RT1PSDIV` writer - RTC Prescale Timer 1 Clock Divide Bit: 2"]
pub type Rt1psdivW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt1psdiv, crate::Safe>;
impl<'a, REG> Rt1psdivW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 1 Clock Divide /2"]
#[inline(always)]
pub fn rt1psdiv_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv0)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /4"]
#[inline(always)]
pub fn rt1psdiv_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv1)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /8"]
#[inline(always)]
pub fn rt1psdiv_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv2)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /16"]
#[inline(always)]
pub fn rt1psdiv_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv3)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /32"]
#[inline(always)]
pub fn rt1psdiv_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv4)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /64"]
#[inline(always)]
pub fn rt1psdiv_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv5)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /128"]
#[inline(always)]
pub fn rt1psdiv_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv6)
}
#[doc = "RTC Prescale Timer 1 Clock Divide /256"]
#[inline(always)]
pub fn rt1psdiv_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt1psdiv::Rt1psdiv7)
}
}
#[doc = "RTC Prescale Timer 1 Source Select Bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt1ssel {
#[doc = "0: RTC Prescale Timer Source Select ACLK"]
Rt1ssel0 = 0,
#[doc = "1: RTC Prescale Timer Source Select SMCLK"]
Rt1ssel1 = 1,
#[doc = "2: RTC Prescale Timer Source Select RT0PS"]
Rt1ssel2 = 2,
#[doc = "3: RTC Prescale Timer Source Select RT0PS"]
Rt1ssel3 = 3,
}
impl From<Rt1ssel> for u8 {
#[inline(always)]
fn from(variant: Rt1ssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt1ssel {
type Ux = u8;
}
impl crate::IsEnum for Rt1ssel {}
#[doc = "Field `RT1SSEL` reader - RTC Prescale Timer 1 Source Select Bit 1"]
pub type Rt1sselR = crate::FieldReader<Rt1ssel>;
impl Rt1sselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt1ssel {
match self.bits {
0 => Rt1ssel::Rt1ssel0,
1 => Rt1ssel::Rt1ssel1,
2 => Rt1ssel::Rt1ssel2,
3 => Rt1ssel::Rt1ssel3,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer Source Select ACLK"]
#[inline(always)]
pub fn is_rt1ssel_0(&self) -> bool {
*self == Rt1ssel::Rt1ssel0
}
#[doc = "RTC Prescale Timer Source Select SMCLK"]
#[inline(always)]
pub fn is_rt1ssel_1(&self) -> bool {
*self == Rt1ssel::Rt1ssel1
}
#[doc = "RTC Prescale Timer Source Select RT0PS"]
#[inline(always)]
pub fn is_rt1ssel_2(&self) -> bool {
*self == Rt1ssel::Rt1ssel2
}
#[doc = "RTC Prescale Timer Source Select RT0PS"]
#[inline(always)]
pub fn is_rt1ssel_3(&self) -> bool {
*self == Rt1ssel::Rt1ssel3
}
}
#[doc = "Field `RT1SSEL` writer - RTC Prescale Timer 1 Source Select Bit 1"]
pub type Rt1sselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rt1ssel, crate::Safe>;
impl<'a, REG> Rt1sselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer Source Select ACLK"]
#[inline(always)]
pub fn rt1ssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ssel::Rt1ssel0)
}
#[doc = "RTC Prescale Timer Source Select SMCLK"]
#[inline(always)]
pub fn rt1ssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ssel::Rt1ssel1)
}
#[doc = "RTC Prescale Timer Source Select RT0PS"]
#[inline(always)]
pub fn rt1ssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ssel::Rt1ssel2)
}
#[doc = "RTC Prescale Timer Source Select RT0PS"]
#[inline(always)]
pub fn rt1ssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ssel::Rt1ssel3)
}
}
impl R {
#[doc = "Bit 0 - RTC Prescale Timer 1 Interrupt Flag"]
#[inline(always)]
pub fn rt1psifg(&self) -> Rt1psifgR {
Rt1psifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 1 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt1psie(&self) -> Rt1psieR {
Rt1psieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt1ip(&self) -> Rt1ipR {
Rt1ipR::new(((self.bits >> 2) & 7) as u8)
}
#[doc = "Bit 8 - RTC Prescale Timer 1 Hold"]
#[inline(always)]
pub fn rt1pshold(&self) -> Rt1psholdR {
Rt1psholdR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 11:13 - RTC Prescale Timer 1 Clock Divide Bit: 2"]
#[inline(always)]
pub fn rt1psdiv(&self) -> Rt1psdivR {
Rt1psdivR::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bits 14:15 - RTC Prescale Timer 1 Source Select Bit 1"]
#[inline(always)]
pub fn rt1ssel(&self) -> Rt1sselR {
Rt1sselR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - RTC Prescale Timer 1 Interrupt Flag"]
#[inline(always)]
pub fn rt1psifg(&mut self) -> Rt1psifgW<'_, Rtcps1ctlSpec> {
Rt1psifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 1 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt1psie(&mut self) -> Rt1psieW<'_, Rtcps1ctlSpec> {
Rt1psieW::new(self, 1)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt1ip(&mut self) -> Rt1ipW<'_, Rtcps1ctlSpec> {
Rt1ipW::new(self, 2)
}
#[doc = "Bit 8 - RTC Prescale Timer 1 Hold"]
#[inline(always)]
pub fn rt1pshold(&mut self) -> Rt1psholdW<'_, Rtcps1ctlSpec> {
Rt1psholdW::new(self, 8)
}
#[doc = "Bits 11:13 - RTC Prescale Timer 1 Clock Divide Bit: 2"]
#[inline(always)]
pub fn rt1psdiv(&mut self) -> Rt1psdivW<'_, Rtcps1ctlSpec> {
Rt1psdivW::new(self, 11)
}
#[doc = "Bits 14:15 - RTC Prescale Timer 1 Source Select Bit 1"]
#[inline(always)]
pub fn rt1ssel(&mut self) -> Rt1sselW<'_, Rtcps1ctlSpec> {
Rt1sselW::new(self, 14)
}
}
#[doc = "Real Timer Prescale Timer 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcps1ctlSpec;
impl crate::RegisterSpec for Rtcps1ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcps1ctl::R`](R) reader structure"]
impl crate::Readable for Rtcps1ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcps1ctl::W`](W) writer structure"]
impl crate::Writable for Rtcps1ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCPS1CTL to value 0"]
impl crate::Resettable for Rtcps1ctlSpec {}