#[doc = "Register `RTCPS0CTL` reader"]
pub type R = crate::R<Rtcps0ctlSpec>;
#[doc = "Register `RTCPS0CTL` writer"]
pub type W = crate::W<Rtcps0ctlSpec>;
#[doc = "Field `RT0PSIFG` reader - RTC Prescale Timer 0 Interrupt Flag"]
pub type Rt0psifgR = crate::BitReader;
#[doc = "Field `RT0PSIFG` writer - RTC Prescale Timer 0 Interrupt Flag"]
pub type Rt0psifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT0PSIE` reader - RTC Prescale Timer 0 Interrupt Enable Flag"]
pub type Rt0psieR = crate::BitReader;
#[doc = "Field `RT0PSIE` writer - RTC Prescale Timer 0 Interrupt Enable Flag"]
pub type Rt0psieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 0 Interrupt Interval Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt0ip {
#[doc = "0: RTC Prescale Timer 0 Interrupt Interval /2"]
Rt0ip0 = 0,
#[doc = "1: RTC Prescale Timer 0 Interrupt Interval /4"]
Rt0ip1 = 1,
#[doc = "2: RTC Prescale Timer 0 Interrupt Interval /8"]
Rt0ip2 = 2,
#[doc = "3: RTC Prescale Timer 0 Interrupt Interval /16"]
Rt0ip3 = 3,
#[doc = "4: RTC Prescale Timer 0 Interrupt Interval /32"]
Rt0ip4 = 4,
#[doc = "5: RTC Prescale Timer 0 Interrupt Interval /64"]
Rt0ip5 = 5,
#[doc = "6: RTC Prescale Timer 0 Interrupt Interval /128"]
Rt0ip6 = 6,
#[doc = "7: RTC Prescale Timer 0 Interrupt Interval /256"]
Rt0ip7 = 7,
}
impl From<Rt0ip> for u8 {
#[inline(always)]
fn from(variant: Rt0ip) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt0ip {
type Ux = u8;
}
impl crate::IsEnum for Rt0ip {}
#[doc = "Field `RT0IP` reader - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
pub type Rt0ipR = crate::FieldReader<Rt0ip>;
impl Rt0ipR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt0ip {
match self.bits {
0 => Rt0ip::Rt0ip0,
1 => Rt0ip::Rt0ip1,
2 => Rt0ip::Rt0ip2,
3 => Rt0ip::Rt0ip3,
4 => Rt0ip::Rt0ip4,
5 => Rt0ip::Rt0ip5,
6 => Rt0ip::Rt0ip6,
7 => Rt0ip::Rt0ip7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /2"]
#[inline(always)]
pub fn is_rt0ip_0(&self) -> bool {
*self == Rt0ip::Rt0ip0
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /4"]
#[inline(always)]
pub fn is_rt0ip_1(&self) -> bool {
*self == Rt0ip::Rt0ip1
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /8"]
#[inline(always)]
pub fn is_rt0ip_2(&self) -> bool {
*self == Rt0ip::Rt0ip2
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /16"]
#[inline(always)]
pub fn is_rt0ip_3(&self) -> bool {
*self == Rt0ip::Rt0ip3
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /32"]
#[inline(always)]
pub fn is_rt0ip_4(&self) -> bool {
*self == Rt0ip::Rt0ip4
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /64"]
#[inline(always)]
pub fn is_rt0ip_5(&self) -> bool {
*self == Rt0ip::Rt0ip5
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /128"]
#[inline(always)]
pub fn is_rt0ip_6(&self) -> bool {
*self == Rt0ip::Rt0ip6
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /256"]
#[inline(always)]
pub fn is_rt0ip_7(&self) -> bool {
*self == Rt0ip::Rt0ip7
}
}
#[doc = "Field `RT0IP` writer - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
pub type Rt0ipW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt0ip, crate::Safe>;
impl<'a, REG> Rt0ipW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 0 Interrupt Interval /2"]
#[inline(always)]
pub fn rt0ip_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip0)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /4"]
#[inline(always)]
pub fn rt0ip_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip1)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /8"]
#[inline(always)]
pub fn rt0ip_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip2)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /16"]
#[inline(always)]
pub fn rt0ip_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip3)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /32"]
#[inline(always)]
pub fn rt0ip_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip4)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /64"]
#[inline(always)]
pub fn rt0ip_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip5)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /128"]
#[inline(always)]
pub fn rt0ip_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip6)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /256"]
#[inline(always)]
pub fn rt0ip_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip7)
}
}
#[doc = "Field `RT0PSHOLD` reader - RTC Prescale Timer 0 Hold"]
pub type Rt0psholdR = crate::BitReader;
#[doc = "Field `RT0PSHOLD` writer - RTC Prescale Timer 0 Hold"]
pub type Rt0psholdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 0 Clock Divide Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt0psdiv {
#[doc = "0: RTC Prescale Timer 0 Clock Divide /2"]
Rt0psdiv0 = 0,
#[doc = "1: RTC Prescale Timer 0 Clock Divide /4"]
Rt0psdiv1 = 1,
#[doc = "2: RTC Prescale Timer 0 Clock Divide /8"]
Rt0psdiv2 = 2,
#[doc = "3: RTC Prescale Timer 0 Clock Divide /16"]
Rt0psdiv3 = 3,
#[doc = "4: RTC Prescale Timer 0 Clock Divide /32"]
Rt0psdiv4 = 4,
#[doc = "5: RTC Prescale Timer 0 Clock Divide /64"]
Rt0psdiv5 = 5,
#[doc = "6: RTC Prescale Timer 0 Clock Divide /128"]
Rt0psdiv6 = 6,
#[doc = "7: RTC Prescale Timer 0 Clock Divide /256"]
Rt0psdiv7 = 7,
}
impl From<Rt0psdiv> for u8 {
#[inline(always)]
fn from(variant: Rt0psdiv) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt0psdiv {
type Ux = u8;
}
impl crate::IsEnum for Rt0psdiv {}
#[doc = "Field `RT0PSDIV` reader - RTC Prescale Timer 0 Clock Divide Bit: 2"]
pub type Rt0psdivR = crate::FieldReader<Rt0psdiv>;
impl Rt0psdivR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt0psdiv {
match self.bits {
0 => Rt0psdiv::Rt0psdiv0,
1 => Rt0psdiv::Rt0psdiv1,
2 => Rt0psdiv::Rt0psdiv2,
3 => Rt0psdiv::Rt0psdiv3,
4 => Rt0psdiv::Rt0psdiv4,
5 => Rt0psdiv::Rt0psdiv5,
6 => Rt0psdiv::Rt0psdiv6,
7 => Rt0psdiv::Rt0psdiv7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 0 Clock Divide /2"]
#[inline(always)]
pub fn is_rt0psdiv_0(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv0
}
#[doc = "RTC Prescale Timer 0 Clock Divide /4"]
#[inline(always)]
pub fn is_rt0psdiv_1(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv1
}
#[doc = "RTC Prescale Timer 0 Clock Divide /8"]
#[inline(always)]
pub fn is_rt0psdiv_2(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv2
}
#[doc = "RTC Prescale Timer 0 Clock Divide /16"]
#[inline(always)]
pub fn is_rt0psdiv_3(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv3
}
#[doc = "RTC Prescale Timer 0 Clock Divide /32"]
#[inline(always)]
pub fn is_rt0psdiv_4(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv4
}
#[doc = "RTC Prescale Timer 0 Clock Divide /64"]
#[inline(always)]
pub fn is_rt0psdiv_5(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv5
}
#[doc = "RTC Prescale Timer 0 Clock Divide /128"]
#[inline(always)]
pub fn is_rt0psdiv_6(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv6
}
#[doc = "RTC Prescale Timer 0 Clock Divide /256"]
#[inline(always)]
pub fn is_rt0psdiv_7(&self) -> bool {
*self == Rt0psdiv::Rt0psdiv7
}
}
#[doc = "Field `RT0PSDIV` writer - RTC Prescale Timer 0 Clock Divide Bit: 2"]
pub type Rt0psdivW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt0psdiv, crate::Safe>;
impl<'a, REG> Rt0psdivW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 0 Clock Divide /2"]
#[inline(always)]
pub fn rt0psdiv_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv0)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /4"]
#[inline(always)]
pub fn rt0psdiv_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv1)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /8"]
#[inline(always)]
pub fn rt0psdiv_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv2)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /16"]
#[inline(always)]
pub fn rt0psdiv_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv3)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /32"]
#[inline(always)]
pub fn rt0psdiv_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv4)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /64"]
#[inline(always)]
pub fn rt0psdiv_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv5)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /128"]
#[inline(always)]
pub fn rt0psdiv_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv6)
}
#[doc = "RTC Prescale Timer 0 Clock Divide /256"]
#[inline(always)]
pub fn rt0psdiv_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt0psdiv::Rt0psdiv7)
}
}
#[doc = "Field `RT0SSEL` reader - RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK"]
pub type Rt0sselR = crate::BitReader;
#[doc = "Field `RT0SSEL` writer - RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK"]
pub type Rt0sselW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RTC Prescale Timer 0 Interrupt Flag"]
#[inline(always)]
pub fn rt0psifg(&self) -> Rt0psifgR {
Rt0psifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 0 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt0psie(&self) -> Rt0psieR {
Rt0psieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt0ip(&self) -> Rt0ipR {
Rt0ipR::new(((self.bits >> 2) & 7) as u8)
}
#[doc = "Bit 8 - RTC Prescale Timer 0 Hold"]
#[inline(always)]
pub fn rt0pshold(&self) -> Rt0psholdR {
Rt0psholdR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 11:13 - RTC Prescale Timer 0 Clock Divide Bit: 2"]
#[inline(always)]
pub fn rt0psdiv(&self) -> Rt0psdivR {
Rt0psdivR::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14 - RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK"]
#[inline(always)]
pub fn rt0ssel(&self) -> Rt0sselR {
Rt0sselR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RTC Prescale Timer 0 Interrupt Flag"]
#[inline(always)]
pub fn rt0psifg(&mut self) -> Rt0psifgW<'_, Rtcps0ctlSpec> {
Rt0psifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 0 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt0psie(&mut self) -> Rt0psieW<'_, Rtcps0ctlSpec> {
Rt0psieW::new(self, 1)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt0ip(&mut self) -> Rt0ipW<'_, Rtcps0ctlSpec> {
Rt0ipW::new(self, 2)
}
#[doc = "Bit 8 - RTC Prescale Timer 0 Hold"]
#[inline(always)]
pub fn rt0pshold(&mut self) -> Rt0psholdW<'_, Rtcps0ctlSpec> {
Rt0psholdW::new(self, 8)
}
#[doc = "Bits 11:13 - RTC Prescale Timer 0 Clock Divide Bit: 2"]
#[inline(always)]
pub fn rt0psdiv(&mut self) -> Rt0psdivW<'_, Rtcps0ctlSpec> {
Rt0psdivW::new(self, 11)
}
#[doc = "Bit 14 - RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK"]
#[inline(always)]
pub fn rt0ssel(&mut self) -> Rt0sselW<'_, Rtcps0ctlSpec> {
Rt0sselW::new(self, 14)
}
}
#[doc = "Real Timer Prescale Timer 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcps0ctlSpec;
impl crate::RegisterSpec for Rtcps0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcps0ctl::R`](R) reader structure"]
impl crate::Readable for Rtcps0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcps0ctl::W`](W) writer structure"]
impl crate::Writable for Rtcps0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCPS0CTL to value 0"]
impl crate::Resettable for Rtcps0ctlSpec {}