#[doc = "Register `RTCCTL01` reader"]
pub type R = crate::R<Rtcctl01Spec>;
#[doc = "Register `RTCCTL01` writer"]
pub type W = crate::W<Rtcctl01Spec>;
#[doc = "Field `RTCRDYIFG` reader - RTC Ready Interrupt Flag"]
pub type RtcrdyifgR = crate::BitReader;
#[doc = "Field `RTCRDYIFG` writer - RTC Ready Interrupt Flag"]
pub type RtcrdyifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAIFG` reader - RTC Alarm Interrupt Flag"]
pub type RtcaifgR = crate::BitReader;
#[doc = "Field `RTCAIFG` writer - RTC Alarm Interrupt Flag"]
pub type RtcaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCTEVIFG` reader - RTC Time Event Interrupt Flag"]
pub type RtctevifgR = crate::BitReader;
#[doc = "Field `RTCTEVIFG` writer - RTC Time Event Interrupt Flag"]
pub type RtctevifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCRDYIE` reader - RTC Ready Interrupt Enable Flag"]
pub type RtcrdyieR = crate::BitReader;
#[doc = "Field `RTCRDYIE` writer - RTC Ready Interrupt Enable Flag"]
pub type RtcrdyieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAIE` reader - RTC Alarm Interrupt Enable Flag"]
pub type RtcaieR = crate::BitReader;
#[doc = "Field `RTCAIE` writer - RTC Alarm Interrupt Enable Flag"]
pub type RtcaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCTEVIE` reader - RTC Time Event Interrupt Enable Flag"]
pub type RtctevieR = crate::BitReader;
#[doc = "Field `RTCTEVIE` writer - RTC Time Event Interrupt Enable Flag"]
pub type RtctevieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Time Event 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rtctev {
#[doc = "0: RTC Time Event: 0 (Min. changed)"]
Rtctev0 = 0,
#[doc = "1: RTC Time Event: 1 (Hour changed)"]
Rtctev1 = 1,
#[doc = "2: RTC Time Event: 2 (12:00 changed)"]
Rtctev2 = 2,
#[doc = "3: RTC Time Event: 3 (00:00 changed)"]
Rtctev3 = 3,
}
impl From<Rtctev> for u8 {
#[inline(always)]
fn from(variant: Rtctev) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rtctev {
type Ux = u8;
}
impl crate::IsEnum for Rtctev {}
#[doc = "Field `RTCTEV` reader - RTC Time Event 1"]
pub type RtctevR = crate::FieldReader<Rtctev>;
impl RtctevR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rtctev {
match self.bits {
0 => Rtctev::Rtctev0,
1 => Rtctev::Rtctev1,
2 => Rtctev::Rtctev2,
3 => Rtctev::Rtctev3,
_ => unreachable!(),
}
}
#[doc = "RTC Time Event: 0 (Min. changed)"]
#[inline(always)]
pub fn is_rtctev_0(&self) -> bool {
*self == Rtctev::Rtctev0
}
#[doc = "RTC Time Event: 1 (Hour changed)"]
#[inline(always)]
pub fn is_rtctev_1(&self) -> bool {
*self == Rtctev::Rtctev1
}
#[doc = "RTC Time Event: 2 (12:00 changed)"]
#[inline(always)]
pub fn is_rtctev_2(&self) -> bool {
*self == Rtctev::Rtctev2
}
#[doc = "RTC Time Event: 3 (00:00 changed)"]
#[inline(always)]
pub fn is_rtctev_3(&self) -> bool {
*self == Rtctev::Rtctev3
}
}
#[doc = "Field `RTCTEV` writer - RTC Time Event 1"]
pub type RtctevW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rtctev, crate::Safe>;
impl<'a, REG> RtctevW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Time Event: 0 (Min. changed)"]
#[inline(always)]
pub fn rtctev_0(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev0)
}
#[doc = "RTC Time Event: 1 (Hour changed)"]
#[inline(always)]
pub fn rtctev_1(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev1)
}
#[doc = "RTC Time Event: 2 (12:00 changed)"]
#[inline(always)]
pub fn rtctev_2(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev2)
}
#[doc = "RTC Time Event: 3 (00:00 changed)"]
#[inline(always)]
pub fn rtctev_3(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev3)
}
}
#[doc = "RTC Source Select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rtcssel {
#[doc = "0: RTC Source Select ACLK"]
Rtcssel0 = 0,
#[doc = "1: RTC Source Select SMCLK"]
Rtcssel1 = 1,
#[doc = "2: RTC Source Select RT1PS"]
Rtcssel2 = 2,
#[doc = "3: RTC Source Select RT1PS"]
Rtcssel3 = 3,
}
impl From<Rtcssel> for u8 {
#[inline(always)]
fn from(variant: Rtcssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rtcssel {
type Ux = u8;
}
impl crate::IsEnum for Rtcssel {}
#[doc = "Field `RTCSSEL` reader - RTC Source Select 1"]
pub type RtcsselR = crate::FieldReader<Rtcssel>;
impl RtcsselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rtcssel {
match self.bits {
0 => Rtcssel::Rtcssel0,
1 => Rtcssel::Rtcssel1,
2 => Rtcssel::Rtcssel2,
3 => Rtcssel::Rtcssel3,
_ => unreachable!(),
}
}
#[doc = "RTC Source Select ACLK"]
#[inline(always)]
pub fn is_rtcssel_0(&self) -> bool {
*self == Rtcssel::Rtcssel0
}
#[doc = "RTC Source Select SMCLK"]
#[inline(always)]
pub fn is_rtcssel_1(&self) -> bool {
*self == Rtcssel::Rtcssel1
}
#[doc = "RTC Source Select RT1PS"]
#[inline(always)]
pub fn is_rtcssel_2(&self) -> bool {
*self == Rtcssel::Rtcssel2
}
#[doc = "RTC Source Select RT1PS"]
#[inline(always)]
pub fn is_rtcssel_3(&self) -> bool {
*self == Rtcssel::Rtcssel3
}
}
#[doc = "Field `RTCSSEL` writer - RTC Source Select 1"]
pub type RtcsselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rtcssel, crate::Safe>;
impl<'a, REG> RtcsselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Source Select ACLK"]
#[inline(always)]
pub fn rtcssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Rtcssel::Rtcssel0)
}
#[doc = "RTC Source Select SMCLK"]
#[inline(always)]
pub fn rtcssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Rtcssel::Rtcssel1)
}
#[doc = "RTC Source Select RT1PS"]
#[inline(always)]
pub fn rtcssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Rtcssel::Rtcssel2)
}
#[doc = "RTC Source Select RT1PS"]
#[inline(always)]
pub fn rtcssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Rtcssel::Rtcssel3)
}
}
#[doc = "Field `RTCRDY` reader - RTC Ready"]
pub type RtcrdyR = crate::BitReader;
#[doc = "Field `RTCRDY` writer - RTC Ready"]
pub type RtcrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCMODE` reader - RTC Mode 0:Counter / 1: Calendar"]
pub type RtcmodeR = crate::BitReader;
#[doc = "Field `RTCMODE` writer - RTC Mode 0:Counter / 1: Calendar"]
pub type RtcmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCHOLD` reader - RTC Hold"]
pub type RtcholdR = crate::BitReader;
#[doc = "Field `RTCHOLD` writer - RTC Hold"]
pub type RtcholdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCBCD` reader - RTC BCD 0:Binary / 1:BCD"]
pub type RtcbcdR = crate::BitReader;
#[doc = "Field `RTCBCD` writer - RTC BCD 0:Binary / 1:BCD"]
pub type RtcbcdW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RTC Ready Interrupt Flag"]
#[inline(always)]
pub fn rtcrdyifg(&self) -> RtcrdyifgR {
RtcrdyifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Alarm Interrupt Flag"]
#[inline(always)]
pub fn rtcaifg(&self) -> RtcaifgR {
RtcaifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RTC Time Event Interrupt Flag"]
#[inline(always)]
pub fn rtctevifg(&self) -> RtctevifgR {
RtctevifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - RTC Ready Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcrdyie(&self) -> RtcrdyieR {
RtcrdyieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RTC Alarm Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcaie(&self) -> RtcaieR {
RtcaieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RTC Time Event Interrupt Enable Flag"]
#[inline(always)]
pub fn rtctevie(&self) -> RtctevieR {
RtctevieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 8:9 - RTC Time Event 1"]
#[inline(always)]
pub fn rtctev(&self) -> RtctevR {
RtctevR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - RTC Source Select 1"]
#[inline(always)]
pub fn rtcssel(&self) -> RtcsselR {
RtcsselR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 12 - RTC Ready"]
#[inline(always)]
pub fn rtcrdy(&self) -> RtcrdyR {
RtcrdyR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - RTC Mode 0:Counter / 1: Calendar"]
#[inline(always)]
pub fn rtcmode(&self) -> RtcmodeR {
RtcmodeR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - RTC Hold"]
#[inline(always)]
pub fn rtchold(&self) -> RtcholdR {
RtcholdR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - RTC BCD 0:Binary / 1:BCD"]
#[inline(always)]
pub fn rtcbcd(&self) -> RtcbcdR {
RtcbcdR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RTC Ready Interrupt Flag"]
#[inline(always)]
pub fn rtcrdyifg(&mut self) -> RtcrdyifgW<'_, Rtcctl01Spec> {
RtcrdyifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Alarm Interrupt Flag"]
#[inline(always)]
pub fn rtcaifg(&mut self) -> RtcaifgW<'_, Rtcctl01Spec> {
RtcaifgW::new(self, 1)
}
#[doc = "Bit 2 - RTC Time Event Interrupt Flag"]
#[inline(always)]
pub fn rtctevifg(&mut self) -> RtctevifgW<'_, Rtcctl01Spec> {
RtctevifgW::new(self, 2)
}
#[doc = "Bit 4 - RTC Ready Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcrdyie(&mut self) -> RtcrdyieW<'_, Rtcctl01Spec> {
RtcrdyieW::new(self, 4)
}
#[doc = "Bit 5 - RTC Alarm Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcaie(&mut self) -> RtcaieW<'_, Rtcctl01Spec> {
RtcaieW::new(self, 5)
}
#[doc = "Bit 6 - RTC Time Event Interrupt Enable Flag"]
#[inline(always)]
pub fn rtctevie(&mut self) -> RtctevieW<'_, Rtcctl01Spec> {
RtctevieW::new(self, 6)
}
#[doc = "Bits 8:9 - RTC Time Event 1"]
#[inline(always)]
pub fn rtctev(&mut self) -> RtctevW<'_, Rtcctl01Spec> {
RtctevW::new(self, 8)
}
#[doc = "Bits 10:11 - RTC Source Select 1"]
#[inline(always)]
pub fn rtcssel(&mut self) -> RtcsselW<'_, Rtcctl01Spec> {
RtcsselW::new(self, 10)
}
#[doc = "Bit 12 - RTC Ready"]
#[inline(always)]
pub fn rtcrdy(&mut self) -> RtcrdyW<'_, Rtcctl01Spec> {
RtcrdyW::new(self, 12)
}
#[doc = "Bit 13 - RTC Mode 0:Counter / 1: Calendar"]
#[inline(always)]
pub fn rtcmode(&mut self) -> RtcmodeW<'_, Rtcctl01Spec> {
RtcmodeW::new(self, 13)
}
#[doc = "Bit 14 - RTC Hold"]
#[inline(always)]
pub fn rtchold(&mut self) -> RtcholdW<'_, Rtcctl01Spec> {
RtcholdW::new(self, 14)
}
#[doc = "Bit 15 - RTC BCD 0:Binary / 1:BCD"]
#[inline(always)]
pub fn rtcbcd(&mut self) -> RtcbcdW<'_, Rtcctl01Spec> {
RtcbcdW::new(self, 15)
}
}
#[doc = "Real Timer Control 0/1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl01::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl01::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcctl01Spec;
impl crate::RegisterSpec for Rtcctl01Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcctl01::R`](R) reader structure"]
impl crate::Readable for Rtcctl01Spec {}
#[doc = "`write(|w| ..)` method takes [`rtcctl01::W`](W) writer structure"]
impl crate::Writable for Rtcctl01Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCCTL01 to value 0"]
impl crate::Resettable for Rtcctl01Spec {}