#[doc = "Register `DMACTL1` reader"]
pub type R = crate::R<Dmactl1Spec>;
#[doc = "Register `DMACTL1` writer"]
pub type W = crate::W<Dmactl1Spec>;
#[doc = "DMA channel 2 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma2tsel {
#[doc = "0: DMA channel 2 transfer select 0: DMA_REQ (sw)"]
Dma2tsel0 = 0,
#[doc = "1: DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
Dma2tsel1 = 1,
#[doc = "2: DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
Dma2tsel2 = 2,
#[doc = "3: DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
Dma2tsel3 = 3,
#[doc = "4: DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
Dma2tsel4 = 4,
#[doc = "5: DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG)"]
Dma2tsel5 = 5,
#[doc = "6: DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG)"]
Dma2tsel6 = 6,
#[doc = "7: DMA channel 2 transfer select 7: Reserved"]
Dma2tsel7 = 7,
#[doc = "8: DMA channel 2 transfer select 8: Reserved"]
Dma2tsel8 = 8,
#[doc = "9: DMA channel 2 transfer select 9: Reserved"]
Dma2tsel9 = 9,
#[doc = "10: DMA channel 2 transfer select 10: Reserved"]
Dma2tsel10 = 10,
#[doc = "11: DMA channel 2 transfer select 11: Reserved"]
Dma2tsel11 = 11,
#[doc = "12: DMA channel 2 transfer select 12: Reserved"]
Dma2tsel12 = 12,
#[doc = "13: DMA channel 2 transfer select 13: Reserved"]
Dma2tsel13 = 13,
#[doc = "14: DMA channel 2 transfer select 14: RFRXIFG"]
Dma2tsel14 = 14,
#[doc = "15: DMA channel 2 transfer select 15: RFTXIFG"]
Dma2tsel15 = 15,
#[doc = "16: DMA channel 2 transfer select 16: USCIA0 receive"]
Dma2tsel16 = 16,
#[doc = "17: DMA channel 2 transfer select 17: USCIA0 transmit"]
Dma2tsel17 = 17,
#[doc = "18: DMA channel 2 transfer select 18: USCIB0 receive"]
Dma2tsel18 = 18,
#[doc = "19: DMA channel 2 transfer select 19: USCIB0 transmit"]
Dma2tsel19 = 19,
#[doc = "20: DMA channel 2 transfer select 20: Reserved"]
Dma2tsel20 = 20,
#[doc = "21: DMA channel 2 transfer select 21: Reserved"]
Dma2tsel21 = 21,
#[doc = "22: DMA channel 2 transfer select 22: Reserved"]
Dma2tsel22 = 22,
#[doc = "23: DMA channel 2 transfer select 23: Reserved"]
Dma2tsel23 = 23,
#[doc = "24: DMA channel 2 transfer select 24: ADC12IFGx"]
Dma2tsel24 = 24,
#[doc = "25: DMA channel 2 transfer select 25: Reserved"]
Dma2tsel25 = 25,
#[doc = "26: DMA channel 2 transfer select 26: Reserved"]
Dma2tsel26 = 26,
#[doc = "27: DMA channel 2 transfer select 27: Reserved"]
Dma2tsel27 = 27,
#[doc = "28: DMA channel 2 transfer select 28: Reserved"]
Dma2tsel28 = 28,
#[doc = "29: DMA channel 2 transfer select 29: Multiplier ready"]
Dma2tsel29 = 29,
#[doc = "30: DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
Dma2tsel30 = 30,
#[doc = "31: DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
Dma2tsel31 = 31,
}
impl From<Dma2tsel> for u8 {
#[inline(always)]
fn from(variant: Dma2tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma2tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma2tsel {}
#[doc = "Field `DMA2TSEL` reader - DMA channel 2 transfer select bit 0"]
pub type Dma2tselR = crate::FieldReader<Dma2tsel>;
impl Dma2tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma2tsel {
match self.bits {
0 => Dma2tsel::Dma2tsel0,
1 => Dma2tsel::Dma2tsel1,
2 => Dma2tsel::Dma2tsel2,
3 => Dma2tsel::Dma2tsel3,
4 => Dma2tsel::Dma2tsel4,
5 => Dma2tsel::Dma2tsel5,
6 => Dma2tsel::Dma2tsel6,
7 => Dma2tsel::Dma2tsel7,
8 => Dma2tsel::Dma2tsel8,
9 => Dma2tsel::Dma2tsel9,
10 => Dma2tsel::Dma2tsel10,
11 => Dma2tsel::Dma2tsel11,
12 => Dma2tsel::Dma2tsel12,
13 => Dma2tsel::Dma2tsel13,
14 => Dma2tsel::Dma2tsel14,
15 => Dma2tsel::Dma2tsel15,
16 => Dma2tsel::Dma2tsel16,
17 => Dma2tsel::Dma2tsel17,
18 => Dma2tsel::Dma2tsel18,
19 => Dma2tsel::Dma2tsel19,
20 => Dma2tsel::Dma2tsel20,
21 => Dma2tsel::Dma2tsel21,
22 => Dma2tsel::Dma2tsel22,
23 => Dma2tsel::Dma2tsel23,
24 => Dma2tsel::Dma2tsel24,
25 => Dma2tsel::Dma2tsel25,
26 => Dma2tsel::Dma2tsel26,
27 => Dma2tsel::Dma2tsel27,
28 => Dma2tsel::Dma2tsel28,
29 => Dma2tsel::Dma2tsel29,
30 => Dma2tsel::Dma2tsel30,
31 => Dma2tsel::Dma2tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 2 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma2tsel_0(&self) -> bool {
*self == Dma2tsel::Dma2tsel0
}
#[doc = "DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_1(&self) -> bool {
*self == Dma2tsel::Dma2tsel1
}
#[doc = "DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_2(&self) -> bool {
*self == Dma2tsel::Dma2tsel2
}
#[doc = "DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_3(&self) -> bool {
*self == Dma2tsel::Dma2tsel3
}
#[doc = "DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_4(&self) -> bool {
*self == Dma2tsel::Dma2tsel4
}
#[doc = "DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_5(&self) -> bool {
*self == Dma2tsel::Dma2tsel5
}
#[doc = "DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma2tsel_6(&self) -> bool {
*self == Dma2tsel::Dma2tsel6
}
#[doc = "DMA channel 2 transfer select 7: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_7(&self) -> bool {
*self == Dma2tsel::Dma2tsel7
}
#[doc = "DMA channel 2 transfer select 8: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_8(&self) -> bool {
*self == Dma2tsel::Dma2tsel8
}
#[doc = "DMA channel 2 transfer select 9: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_9(&self) -> bool {
*self == Dma2tsel::Dma2tsel9
}
#[doc = "DMA channel 2 transfer select 10: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_10(&self) -> bool {
*self == Dma2tsel::Dma2tsel10
}
#[doc = "DMA channel 2 transfer select 11: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_11(&self) -> bool {
*self == Dma2tsel::Dma2tsel11
}
#[doc = "DMA channel 2 transfer select 12: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_12(&self) -> bool {
*self == Dma2tsel::Dma2tsel12
}
#[doc = "DMA channel 2 transfer select 13: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_13(&self) -> bool {
*self == Dma2tsel::Dma2tsel13
}
#[doc = "DMA channel 2 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn is_dma2tsel_14(&self) -> bool {
*self == Dma2tsel::Dma2tsel14
}
#[doc = "DMA channel 2 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn is_dma2tsel_15(&self) -> bool {
*self == Dma2tsel::Dma2tsel15
}
#[doc = "DMA channel 2 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn is_dma2tsel_16(&self) -> bool {
*self == Dma2tsel::Dma2tsel16
}
#[doc = "DMA channel 2 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn is_dma2tsel_17(&self) -> bool {
*self == Dma2tsel::Dma2tsel17
}
#[doc = "DMA channel 2 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn is_dma2tsel_18(&self) -> bool {
*self == Dma2tsel::Dma2tsel18
}
#[doc = "DMA channel 2 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn is_dma2tsel_19(&self) -> bool {
*self == Dma2tsel::Dma2tsel19
}
#[doc = "DMA channel 2 transfer select 20: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_20(&self) -> bool {
*self == Dma2tsel::Dma2tsel20
}
#[doc = "DMA channel 2 transfer select 21: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_21(&self) -> bool {
*self == Dma2tsel::Dma2tsel21
}
#[doc = "DMA channel 2 transfer select 22: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_22(&self) -> bool {
*self == Dma2tsel::Dma2tsel22
}
#[doc = "DMA channel 2 transfer select 23: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_23(&self) -> bool {
*self == Dma2tsel::Dma2tsel23
}
#[doc = "DMA channel 2 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn is_dma2tsel_24(&self) -> bool {
*self == Dma2tsel::Dma2tsel24
}
#[doc = "DMA channel 2 transfer select 25: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_25(&self) -> bool {
*self == Dma2tsel::Dma2tsel25
}
#[doc = "DMA channel 2 transfer select 26: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_26(&self) -> bool {
*self == Dma2tsel::Dma2tsel26
}
#[doc = "DMA channel 2 transfer select 27: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_27(&self) -> bool {
*self == Dma2tsel::Dma2tsel27
}
#[doc = "DMA channel 2 transfer select 28: Reserved"]
#[inline(always)]
pub fn is_dma2tsel_28(&self) -> bool {
*self == Dma2tsel::Dma2tsel28
}
#[doc = "DMA channel 2 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn is_dma2tsel_29(&self) -> bool {
*self == Dma2tsel::Dma2tsel29
}
#[doc = "DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
#[inline(always)]
pub fn is_dma2tsel_30(&self) -> bool {
*self == Dma2tsel::Dma2tsel30
}
#[doc = "DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma2tsel_31(&self) -> bool {
*self == Dma2tsel::Dma2tsel31
}
}
#[doc = "Field `DMA2TSEL` writer - DMA channel 2 transfer select bit 0"]
pub type Dma2tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma2tsel, crate::Safe>;
impl<'a, REG> Dma2tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 2 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma2tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel0)
}
#[doc = "DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn dma2tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel1)
}
#[doc = "DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn dma2tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel2)
}
#[doc = "DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn dma2tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel3)
}
#[doc = "DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn dma2tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel4)
}
#[doc = "DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn dma2tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel5)
}
#[doc = "DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn dma2tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel6)
}
#[doc = "DMA channel 2 transfer select 7: Reserved"]
#[inline(always)]
pub fn dma2tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel7)
}
#[doc = "DMA channel 2 transfer select 8: Reserved"]
#[inline(always)]
pub fn dma2tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel8)
}
#[doc = "DMA channel 2 transfer select 9: Reserved"]
#[inline(always)]
pub fn dma2tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel9)
}
#[doc = "DMA channel 2 transfer select 10: Reserved"]
#[inline(always)]
pub fn dma2tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel10)
}
#[doc = "DMA channel 2 transfer select 11: Reserved"]
#[inline(always)]
pub fn dma2tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel11)
}
#[doc = "DMA channel 2 transfer select 12: Reserved"]
#[inline(always)]
pub fn dma2tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel12)
}
#[doc = "DMA channel 2 transfer select 13: Reserved"]
#[inline(always)]
pub fn dma2tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel13)
}
#[doc = "DMA channel 2 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn dma2tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel14)
}
#[doc = "DMA channel 2 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn dma2tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel15)
}
#[doc = "DMA channel 2 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn dma2tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel16)
}
#[doc = "DMA channel 2 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn dma2tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel17)
}
#[doc = "DMA channel 2 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn dma2tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel18)
}
#[doc = "DMA channel 2 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn dma2tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel19)
}
#[doc = "DMA channel 2 transfer select 20: Reserved"]
#[inline(always)]
pub fn dma2tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel20)
}
#[doc = "DMA channel 2 transfer select 21: Reserved"]
#[inline(always)]
pub fn dma2tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel21)
}
#[doc = "DMA channel 2 transfer select 22: Reserved"]
#[inline(always)]
pub fn dma2tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel22)
}
#[doc = "DMA channel 2 transfer select 23: Reserved"]
#[inline(always)]
pub fn dma2tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel23)
}
#[doc = "DMA channel 2 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn dma2tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel24)
}
#[doc = "DMA channel 2 transfer select 25: Reserved"]
#[inline(always)]
pub fn dma2tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel25)
}
#[doc = "DMA channel 2 transfer select 26: Reserved"]
#[inline(always)]
pub fn dma2tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel26)
}
#[doc = "DMA channel 2 transfer select 27: Reserved"]
#[inline(always)]
pub fn dma2tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel27)
}
#[doc = "DMA channel 2 transfer select 28: Reserved"]
#[inline(always)]
pub fn dma2tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel28)
}
#[doc = "DMA channel 2 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn dma2tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel29)
}
#[doc = "DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
#[inline(always)]
pub fn dma2tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel30)
}
#[doc = "DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma2tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel31)
}
}
impl R {
#[doc = "Bits 0:4 - DMA channel 2 transfer select bit 0"]
#[inline(always)]
pub fn dma2tsel(&self) -> Dma2tselR {
Dma2tselR::new((self.bits & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - DMA channel 2 transfer select bit 0"]
#[inline(always)]
pub fn dma2tsel(&mut self) -> Dma2tselW<'_, Dmactl1Spec> {
Dma2tselW::new(self, 0)
}
}
#[doc = "DMA Module Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl1Spec;
impl crate::RegisterSpec for Dmactl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl1::R`](R) reader structure"]
impl crate::Readable for Dmactl1Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl1::W`](W) writer structure"]
impl crate::Writable for Dmactl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL1 to value 0"]
impl crate::Resettable for Dmactl1Spec {}