#[doc = "Register `DMACTL0` reader"]
pub type R = crate::R<Dmactl0Spec>;
#[doc = "Register `DMACTL0` writer"]
pub type W = crate::W<Dmactl0Spec>;
#[doc = "DMA channel 0 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma0tsel {
#[doc = "0: DMA channel 0 transfer select 0: DMA_REQ (sw)"]
Dma0tsel0 = 0,
#[doc = "1: DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
Dma0tsel1 = 1,
#[doc = "2: DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
Dma0tsel2 = 2,
#[doc = "3: DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
Dma0tsel3 = 3,
#[doc = "4: DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
Dma0tsel4 = 4,
#[doc = "5: DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG)"]
Dma0tsel5 = 5,
#[doc = "6: DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG)"]
Dma0tsel6 = 6,
#[doc = "7: DMA channel 0 transfer select 7: Reserved"]
Dma0tsel7 = 7,
#[doc = "8: DMA channel 0 transfer select 8: Reserved"]
Dma0tsel8 = 8,
#[doc = "9: DMA channel 0 transfer select 9: Reserved"]
Dma0tsel9 = 9,
#[doc = "10: DMA channel 0 transfer select 10: Reserved"]
Dma0tsel10 = 10,
#[doc = "11: DMA channel 0 transfer select 11: Reserved"]
Dma0tsel11 = 11,
#[doc = "12: DMA channel 0 transfer select 12: Reserved"]
Dma0tsel12 = 12,
#[doc = "13: DMA channel 0 transfer select 13: Reserved"]
Dma0tsel13 = 13,
#[doc = "14: DMA channel 0 transfer select 14: RFRXIFG"]
Dma0tsel14 = 14,
#[doc = "15: DMA channel 0 transfer select 15: RFTXIFG"]
Dma0tsel15 = 15,
#[doc = "16: DMA channel 0 transfer select 16: USCIA0 receive"]
Dma0tsel16 = 16,
#[doc = "17: DMA channel 0 transfer select 17: USCIA0 transmit"]
Dma0tsel17 = 17,
#[doc = "18: DMA channel 0 transfer select 18: USCIB0 receive"]
Dma0tsel18 = 18,
#[doc = "19: DMA channel 0 transfer select 19: USCIB0 transmit"]
Dma0tsel19 = 19,
#[doc = "20: DMA channel 0 transfer select 20: Reserved"]
Dma0tsel20 = 20,
#[doc = "21: DMA channel 0 transfer select 21: Reserved"]
Dma0tsel21 = 21,
#[doc = "22: DMA channel 0 transfer select 22: Reserved"]
Dma0tsel22 = 22,
#[doc = "23: DMA channel 0 transfer select 23: Reserved"]
Dma0tsel23 = 23,
#[doc = "24: DMA channel 0 transfer select 24: ADC12IFGx"]
Dma0tsel24 = 24,
#[doc = "25: DMA channel 0 transfer select 25: Reserved"]
Dma0tsel25 = 25,
#[doc = "26: DMA channel 0 transfer select 26: Reserved"]
Dma0tsel26 = 26,
#[doc = "27: DMA channel 0 transfer select 27: Reserved"]
Dma0tsel27 = 27,
#[doc = "28: DMA channel 0 transfer select 28: Reserved"]
Dma0tsel28 = 28,
#[doc = "29: DMA channel 0 transfer select 29: Multiplier ready"]
Dma0tsel29 = 29,
#[doc = "30: DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
Dma0tsel30 = 30,
#[doc = "31: DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
Dma0tsel31 = 31,
}
impl From<Dma0tsel> for u8 {
#[inline(always)]
fn from(variant: Dma0tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma0tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma0tsel {}
#[doc = "Field `DMA0TSEL` reader - DMA channel 0 transfer select bit 0"]
pub type Dma0tselR = crate::FieldReader<Dma0tsel>;
impl Dma0tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma0tsel {
match self.bits {
0 => Dma0tsel::Dma0tsel0,
1 => Dma0tsel::Dma0tsel1,
2 => Dma0tsel::Dma0tsel2,
3 => Dma0tsel::Dma0tsel3,
4 => Dma0tsel::Dma0tsel4,
5 => Dma0tsel::Dma0tsel5,
6 => Dma0tsel::Dma0tsel6,
7 => Dma0tsel::Dma0tsel7,
8 => Dma0tsel::Dma0tsel8,
9 => Dma0tsel::Dma0tsel9,
10 => Dma0tsel::Dma0tsel10,
11 => Dma0tsel::Dma0tsel11,
12 => Dma0tsel::Dma0tsel12,
13 => Dma0tsel::Dma0tsel13,
14 => Dma0tsel::Dma0tsel14,
15 => Dma0tsel::Dma0tsel15,
16 => Dma0tsel::Dma0tsel16,
17 => Dma0tsel::Dma0tsel17,
18 => Dma0tsel::Dma0tsel18,
19 => Dma0tsel::Dma0tsel19,
20 => Dma0tsel::Dma0tsel20,
21 => Dma0tsel::Dma0tsel21,
22 => Dma0tsel::Dma0tsel22,
23 => Dma0tsel::Dma0tsel23,
24 => Dma0tsel::Dma0tsel24,
25 => Dma0tsel::Dma0tsel25,
26 => Dma0tsel::Dma0tsel26,
27 => Dma0tsel::Dma0tsel27,
28 => Dma0tsel::Dma0tsel28,
29 => Dma0tsel::Dma0tsel29,
30 => Dma0tsel::Dma0tsel30,
31 => Dma0tsel::Dma0tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 0 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma0tsel_0(&self) -> bool {
*self == Dma0tsel::Dma0tsel0
}
#[doc = "DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_1(&self) -> bool {
*self == Dma0tsel::Dma0tsel1
}
#[doc = "DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_2(&self) -> bool {
*self == Dma0tsel::Dma0tsel2
}
#[doc = "DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_3(&self) -> bool {
*self == Dma0tsel::Dma0tsel3
}
#[doc = "DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_4(&self) -> bool {
*self == Dma0tsel::Dma0tsel4
}
#[doc = "DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_5(&self) -> bool {
*self == Dma0tsel::Dma0tsel5
}
#[doc = "DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma0tsel_6(&self) -> bool {
*self == Dma0tsel::Dma0tsel6
}
#[doc = "DMA channel 0 transfer select 7: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_7(&self) -> bool {
*self == Dma0tsel::Dma0tsel7
}
#[doc = "DMA channel 0 transfer select 8: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_8(&self) -> bool {
*self == Dma0tsel::Dma0tsel8
}
#[doc = "DMA channel 0 transfer select 9: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_9(&self) -> bool {
*self == Dma0tsel::Dma0tsel9
}
#[doc = "DMA channel 0 transfer select 10: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_10(&self) -> bool {
*self == Dma0tsel::Dma0tsel10
}
#[doc = "DMA channel 0 transfer select 11: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_11(&self) -> bool {
*self == Dma0tsel::Dma0tsel11
}
#[doc = "DMA channel 0 transfer select 12: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_12(&self) -> bool {
*self == Dma0tsel::Dma0tsel12
}
#[doc = "DMA channel 0 transfer select 13: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_13(&self) -> bool {
*self == Dma0tsel::Dma0tsel13
}
#[doc = "DMA channel 0 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn is_dma0tsel_14(&self) -> bool {
*self == Dma0tsel::Dma0tsel14
}
#[doc = "DMA channel 0 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn is_dma0tsel_15(&self) -> bool {
*self == Dma0tsel::Dma0tsel15
}
#[doc = "DMA channel 0 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn is_dma0tsel_16(&self) -> bool {
*self == Dma0tsel::Dma0tsel16
}
#[doc = "DMA channel 0 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn is_dma0tsel_17(&self) -> bool {
*self == Dma0tsel::Dma0tsel17
}
#[doc = "DMA channel 0 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn is_dma0tsel_18(&self) -> bool {
*self == Dma0tsel::Dma0tsel18
}
#[doc = "DMA channel 0 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn is_dma0tsel_19(&self) -> bool {
*self == Dma0tsel::Dma0tsel19
}
#[doc = "DMA channel 0 transfer select 20: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_20(&self) -> bool {
*self == Dma0tsel::Dma0tsel20
}
#[doc = "DMA channel 0 transfer select 21: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_21(&self) -> bool {
*self == Dma0tsel::Dma0tsel21
}
#[doc = "DMA channel 0 transfer select 22: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_22(&self) -> bool {
*self == Dma0tsel::Dma0tsel22
}
#[doc = "DMA channel 0 transfer select 23: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_23(&self) -> bool {
*self == Dma0tsel::Dma0tsel23
}
#[doc = "DMA channel 0 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn is_dma0tsel_24(&self) -> bool {
*self == Dma0tsel::Dma0tsel24
}
#[doc = "DMA channel 0 transfer select 25: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_25(&self) -> bool {
*self == Dma0tsel::Dma0tsel25
}
#[doc = "DMA channel 0 transfer select 26: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_26(&self) -> bool {
*self == Dma0tsel::Dma0tsel26
}
#[doc = "DMA channel 0 transfer select 27: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_27(&self) -> bool {
*self == Dma0tsel::Dma0tsel27
}
#[doc = "DMA channel 0 transfer select 28: Reserved"]
#[inline(always)]
pub fn is_dma0tsel_28(&self) -> bool {
*self == Dma0tsel::Dma0tsel28
}
#[doc = "DMA channel 0 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn is_dma0tsel_29(&self) -> bool {
*self == Dma0tsel::Dma0tsel29
}
#[doc = "DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
#[inline(always)]
pub fn is_dma0tsel_30(&self) -> bool {
*self == Dma0tsel::Dma0tsel30
}
#[doc = "DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma0tsel_31(&self) -> bool {
*self == Dma0tsel::Dma0tsel31
}
}
#[doc = "Field `DMA0TSEL` writer - DMA channel 0 transfer select bit 0"]
pub type Dma0tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma0tsel, crate::Safe>;
impl<'a, REG> Dma0tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 0 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma0tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel0)
}
#[doc = "DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn dma0tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel1)
}
#[doc = "DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn dma0tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel2)
}
#[doc = "DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn dma0tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel3)
}
#[doc = "DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn dma0tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel4)
}
#[doc = "DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn dma0tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel5)
}
#[doc = "DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn dma0tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel6)
}
#[doc = "DMA channel 0 transfer select 7: Reserved"]
#[inline(always)]
pub fn dma0tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel7)
}
#[doc = "DMA channel 0 transfer select 8: Reserved"]
#[inline(always)]
pub fn dma0tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel8)
}
#[doc = "DMA channel 0 transfer select 9: Reserved"]
#[inline(always)]
pub fn dma0tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel9)
}
#[doc = "DMA channel 0 transfer select 10: Reserved"]
#[inline(always)]
pub fn dma0tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel10)
}
#[doc = "DMA channel 0 transfer select 11: Reserved"]
#[inline(always)]
pub fn dma0tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel11)
}
#[doc = "DMA channel 0 transfer select 12: Reserved"]
#[inline(always)]
pub fn dma0tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel12)
}
#[doc = "DMA channel 0 transfer select 13: Reserved"]
#[inline(always)]
pub fn dma0tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel13)
}
#[doc = "DMA channel 0 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn dma0tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel14)
}
#[doc = "DMA channel 0 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn dma0tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel15)
}
#[doc = "DMA channel 0 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn dma0tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel16)
}
#[doc = "DMA channel 0 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn dma0tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel17)
}
#[doc = "DMA channel 0 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn dma0tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel18)
}
#[doc = "DMA channel 0 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn dma0tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel19)
}
#[doc = "DMA channel 0 transfer select 20: Reserved"]
#[inline(always)]
pub fn dma0tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel20)
}
#[doc = "DMA channel 0 transfer select 21: Reserved"]
#[inline(always)]
pub fn dma0tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel21)
}
#[doc = "DMA channel 0 transfer select 22: Reserved"]
#[inline(always)]
pub fn dma0tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel22)
}
#[doc = "DMA channel 0 transfer select 23: Reserved"]
#[inline(always)]
pub fn dma0tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel23)
}
#[doc = "DMA channel 0 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn dma0tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel24)
}
#[doc = "DMA channel 0 transfer select 25: Reserved"]
#[inline(always)]
pub fn dma0tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel25)
}
#[doc = "DMA channel 0 transfer select 26: Reserved"]
#[inline(always)]
pub fn dma0tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel26)
}
#[doc = "DMA channel 0 transfer select 27: Reserved"]
#[inline(always)]
pub fn dma0tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel27)
}
#[doc = "DMA channel 0 transfer select 28: Reserved"]
#[inline(always)]
pub fn dma0tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel28)
}
#[doc = "DMA channel 0 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn dma0tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel29)
}
#[doc = "DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
#[inline(always)]
pub fn dma0tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel30)
}
#[doc = "DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma0tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel31)
}
}
#[doc = "DMA channel 1 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma1tsel {
#[doc = "0: DMA channel 1 transfer select 0: DMA_REQ (sw)"]
Dma1tsel0 = 0,
#[doc = "1: DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
Dma1tsel1 = 1,
#[doc = "2: DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
Dma1tsel2 = 2,
#[doc = "3: DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
Dma1tsel3 = 3,
#[doc = "4: DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
Dma1tsel4 = 4,
#[doc = "5: DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG)"]
Dma1tsel5 = 5,
#[doc = "6: DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG)"]
Dma1tsel6 = 6,
#[doc = "7: DMA channel 1 transfer select 7: Reserved"]
Dma1tsel7 = 7,
#[doc = "8: DMA channel 1 transfer select 8: Reserved"]
Dma1tsel8 = 8,
#[doc = "9: DMA channel 1 transfer select 9: Reserved"]
Dma1tsel9 = 9,
#[doc = "10: DMA channel 1 transfer select 10: Reserved"]
Dma1tsel10 = 10,
#[doc = "11: DMA channel 1 transfer select 11: Reserved"]
Dma1tsel11 = 11,
#[doc = "12: DMA channel 1 transfer select 12: Reserved"]
Dma1tsel12 = 12,
#[doc = "13: DMA channel 1 transfer select 13: Reserved"]
Dma1tsel13 = 13,
#[doc = "14: DMA channel 1 transfer select 14: RFRXIFG"]
Dma1tsel14 = 14,
#[doc = "15: DMA channel 1 transfer select 15: RFTXIFG"]
Dma1tsel15 = 15,
#[doc = "16: DMA channel 1 transfer select 16: USCIA0 receive"]
Dma1tsel16 = 16,
#[doc = "17: DMA channel 1 transfer select 17: USCIA0 transmit"]
Dma1tsel17 = 17,
#[doc = "18: DMA channel 1 transfer select 18: USCIB0 receive"]
Dma1tsel18 = 18,
#[doc = "19: DMA channel 1 transfer select 19: USCIB0 transmit"]
Dma1tsel19 = 19,
#[doc = "20: DMA channel 1 transfer select 20: Reserved"]
Dma1tsel20 = 20,
#[doc = "21: DMA channel 1 transfer select 21: Reserved"]
Dma1tsel21 = 21,
#[doc = "22: DMA channel 1 transfer select 22: Reserved"]
Dma1tsel22 = 22,
#[doc = "23: DMA channel 1 transfer select 23: Reserved"]
Dma1tsel23 = 23,
#[doc = "24: DMA channel 1 transfer select 24: ADC12IFGx"]
Dma1tsel24 = 24,
#[doc = "25: DMA channel 1 transfer select 25: Reserved"]
Dma1tsel25 = 25,
#[doc = "26: DMA channel 1 transfer select 26: Reserved"]
Dma1tsel26 = 26,
#[doc = "27: DMA channel 1 transfer select 27: Reserved"]
Dma1tsel27 = 27,
#[doc = "28: DMA channel 1 transfer select 28: Reserved"]
Dma1tsel28 = 28,
#[doc = "29: DMA channel 1 transfer select 29: Multiplier ready"]
Dma1tsel29 = 29,
#[doc = "30: DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
Dma1tsel30 = 30,
#[doc = "31: DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
Dma1tsel31 = 31,
}
impl From<Dma1tsel> for u8 {
#[inline(always)]
fn from(variant: Dma1tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma1tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma1tsel {}
#[doc = "Field `DMA1TSEL` reader - DMA channel 1 transfer select bit 0"]
pub type Dma1tselR = crate::FieldReader<Dma1tsel>;
impl Dma1tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma1tsel {
match self.bits {
0 => Dma1tsel::Dma1tsel0,
1 => Dma1tsel::Dma1tsel1,
2 => Dma1tsel::Dma1tsel2,
3 => Dma1tsel::Dma1tsel3,
4 => Dma1tsel::Dma1tsel4,
5 => Dma1tsel::Dma1tsel5,
6 => Dma1tsel::Dma1tsel6,
7 => Dma1tsel::Dma1tsel7,
8 => Dma1tsel::Dma1tsel8,
9 => Dma1tsel::Dma1tsel9,
10 => Dma1tsel::Dma1tsel10,
11 => Dma1tsel::Dma1tsel11,
12 => Dma1tsel::Dma1tsel12,
13 => Dma1tsel::Dma1tsel13,
14 => Dma1tsel::Dma1tsel14,
15 => Dma1tsel::Dma1tsel15,
16 => Dma1tsel::Dma1tsel16,
17 => Dma1tsel::Dma1tsel17,
18 => Dma1tsel::Dma1tsel18,
19 => Dma1tsel::Dma1tsel19,
20 => Dma1tsel::Dma1tsel20,
21 => Dma1tsel::Dma1tsel21,
22 => Dma1tsel::Dma1tsel22,
23 => Dma1tsel::Dma1tsel23,
24 => Dma1tsel::Dma1tsel24,
25 => Dma1tsel::Dma1tsel25,
26 => Dma1tsel::Dma1tsel26,
27 => Dma1tsel::Dma1tsel27,
28 => Dma1tsel::Dma1tsel28,
29 => Dma1tsel::Dma1tsel29,
30 => Dma1tsel::Dma1tsel30,
31 => Dma1tsel::Dma1tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 1 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma1tsel_0(&self) -> bool {
*self == Dma1tsel::Dma1tsel0
}
#[doc = "DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_1(&self) -> bool {
*self == Dma1tsel::Dma1tsel1
}
#[doc = "DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_2(&self) -> bool {
*self == Dma1tsel::Dma1tsel2
}
#[doc = "DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_3(&self) -> bool {
*self == Dma1tsel::Dma1tsel3
}
#[doc = "DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_4(&self) -> bool {
*self == Dma1tsel::Dma1tsel4
}
#[doc = "DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_5(&self) -> bool {
*self == Dma1tsel::Dma1tsel5
}
#[doc = "DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn is_dma1tsel_6(&self) -> bool {
*self == Dma1tsel::Dma1tsel6
}
#[doc = "DMA channel 1 transfer select 7: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_7(&self) -> bool {
*self == Dma1tsel::Dma1tsel7
}
#[doc = "DMA channel 1 transfer select 8: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_8(&self) -> bool {
*self == Dma1tsel::Dma1tsel8
}
#[doc = "DMA channel 1 transfer select 9: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_9(&self) -> bool {
*self == Dma1tsel::Dma1tsel9
}
#[doc = "DMA channel 1 transfer select 10: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_10(&self) -> bool {
*self == Dma1tsel::Dma1tsel10
}
#[doc = "DMA channel 1 transfer select 11: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_11(&self) -> bool {
*self == Dma1tsel::Dma1tsel11
}
#[doc = "DMA channel 1 transfer select 12: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_12(&self) -> bool {
*self == Dma1tsel::Dma1tsel12
}
#[doc = "DMA channel 1 transfer select 13: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_13(&self) -> bool {
*self == Dma1tsel::Dma1tsel13
}
#[doc = "DMA channel 1 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn is_dma1tsel_14(&self) -> bool {
*self == Dma1tsel::Dma1tsel14
}
#[doc = "DMA channel 1 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn is_dma1tsel_15(&self) -> bool {
*self == Dma1tsel::Dma1tsel15
}
#[doc = "DMA channel 1 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn is_dma1tsel_16(&self) -> bool {
*self == Dma1tsel::Dma1tsel16
}
#[doc = "DMA channel 1 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn is_dma1tsel_17(&self) -> bool {
*self == Dma1tsel::Dma1tsel17
}
#[doc = "DMA channel 1 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn is_dma1tsel_18(&self) -> bool {
*self == Dma1tsel::Dma1tsel18
}
#[doc = "DMA channel 1 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn is_dma1tsel_19(&self) -> bool {
*self == Dma1tsel::Dma1tsel19
}
#[doc = "DMA channel 1 transfer select 20: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_20(&self) -> bool {
*self == Dma1tsel::Dma1tsel20
}
#[doc = "DMA channel 1 transfer select 21: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_21(&self) -> bool {
*self == Dma1tsel::Dma1tsel21
}
#[doc = "DMA channel 1 transfer select 22: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_22(&self) -> bool {
*self == Dma1tsel::Dma1tsel22
}
#[doc = "DMA channel 1 transfer select 23: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_23(&self) -> bool {
*self == Dma1tsel::Dma1tsel23
}
#[doc = "DMA channel 1 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn is_dma1tsel_24(&self) -> bool {
*self == Dma1tsel::Dma1tsel24
}
#[doc = "DMA channel 1 transfer select 25: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_25(&self) -> bool {
*self == Dma1tsel::Dma1tsel25
}
#[doc = "DMA channel 1 transfer select 26: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_26(&self) -> bool {
*self == Dma1tsel::Dma1tsel26
}
#[doc = "DMA channel 1 transfer select 27: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_27(&self) -> bool {
*self == Dma1tsel::Dma1tsel27
}
#[doc = "DMA channel 1 transfer select 28: Reserved"]
#[inline(always)]
pub fn is_dma1tsel_28(&self) -> bool {
*self == Dma1tsel::Dma1tsel28
}
#[doc = "DMA channel 1 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn is_dma1tsel_29(&self) -> bool {
*self == Dma1tsel::Dma1tsel29
}
#[doc = "DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
#[inline(always)]
pub fn is_dma1tsel_30(&self) -> bool {
*self == Dma1tsel::Dma1tsel30
}
#[doc = "DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma1tsel_31(&self) -> bool {
*self == Dma1tsel::Dma1tsel31
}
}
#[doc = "Field `DMA1TSEL` writer - DMA channel 1 transfer select bit 0"]
pub type Dma1tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma1tsel, crate::Safe>;
impl<'a, REG> Dma1tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 1 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma1tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel0)
}
#[doc = "DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG)"]
#[inline(always)]
pub fn dma1tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel1)
}
#[doc = "DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG)"]
#[inline(always)]
pub fn dma1tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel2)
}
#[doc = "DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG)"]
#[inline(always)]
pub fn dma1tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel3)
}
#[doc = "DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG)"]
#[inline(always)]
pub fn dma1tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel4)
}
#[doc = "DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG)"]
#[inline(always)]
pub fn dma1tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel5)
}
#[doc = "DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG)"]
#[inline(always)]
pub fn dma1tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel6)
}
#[doc = "DMA channel 1 transfer select 7: Reserved"]
#[inline(always)]
pub fn dma1tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel7)
}
#[doc = "DMA channel 1 transfer select 8: Reserved"]
#[inline(always)]
pub fn dma1tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel8)
}
#[doc = "DMA channel 1 transfer select 9: Reserved"]
#[inline(always)]
pub fn dma1tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel9)
}
#[doc = "DMA channel 1 transfer select 10: Reserved"]
#[inline(always)]
pub fn dma1tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel10)
}
#[doc = "DMA channel 1 transfer select 11: Reserved"]
#[inline(always)]
pub fn dma1tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel11)
}
#[doc = "DMA channel 1 transfer select 12: Reserved"]
#[inline(always)]
pub fn dma1tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel12)
}
#[doc = "DMA channel 1 transfer select 13: Reserved"]
#[inline(always)]
pub fn dma1tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel13)
}
#[doc = "DMA channel 1 transfer select 14: RFRXIFG"]
#[inline(always)]
pub fn dma1tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel14)
}
#[doc = "DMA channel 1 transfer select 15: RFTXIFG"]
#[inline(always)]
pub fn dma1tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel15)
}
#[doc = "DMA channel 1 transfer select 16: USCIA0 receive"]
#[inline(always)]
pub fn dma1tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel16)
}
#[doc = "DMA channel 1 transfer select 17: USCIA0 transmit"]
#[inline(always)]
pub fn dma1tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel17)
}
#[doc = "DMA channel 1 transfer select 18: USCIB0 receive"]
#[inline(always)]
pub fn dma1tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel18)
}
#[doc = "DMA channel 1 transfer select 19: USCIB0 transmit"]
#[inline(always)]
pub fn dma1tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel19)
}
#[doc = "DMA channel 1 transfer select 20: Reserved"]
#[inline(always)]
pub fn dma1tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel20)
}
#[doc = "DMA channel 1 transfer select 21: Reserved"]
#[inline(always)]
pub fn dma1tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel21)
}
#[doc = "DMA channel 1 transfer select 22: Reserved"]
#[inline(always)]
pub fn dma1tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel22)
}
#[doc = "DMA channel 1 transfer select 23: Reserved"]
#[inline(always)]
pub fn dma1tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel23)
}
#[doc = "DMA channel 1 transfer select 24: ADC12IFGx"]
#[inline(always)]
pub fn dma1tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel24)
}
#[doc = "DMA channel 1 transfer select 25: Reserved"]
#[inline(always)]
pub fn dma1tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel25)
}
#[doc = "DMA channel 1 transfer select 26: Reserved"]
#[inline(always)]
pub fn dma1tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel26)
}
#[doc = "DMA channel 1 transfer select 27: Reserved"]
#[inline(always)]
pub fn dma1tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel27)
}
#[doc = "DMA channel 1 transfer select 28: Reserved"]
#[inline(always)]
pub fn dma1tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel28)
}
#[doc = "DMA channel 1 transfer select 29: Multiplier ready"]
#[inline(always)]
pub fn dma1tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel29)
}
#[doc = "DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
#[inline(always)]
pub fn dma1tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel30)
}
#[doc = "DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma1tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel31)
}
}
impl R {
#[doc = "Bits 0:4 - DMA channel 0 transfer select bit 0"]
#[inline(always)]
pub fn dma0tsel(&self) -> Dma0tselR {
Dma0tselR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 8:12 - DMA channel 1 transfer select bit 0"]
#[inline(always)]
pub fn dma1tsel(&self) -> Dma1tselR {
Dma1tselR::new(((self.bits >> 8) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - DMA channel 0 transfer select bit 0"]
#[inline(always)]
pub fn dma0tsel(&mut self) -> Dma0tselW<'_, Dmactl0Spec> {
Dma0tselW::new(self, 0)
}
#[doc = "Bits 8:12 - DMA channel 1 transfer select bit 0"]
#[inline(always)]
pub fn dma1tsel(&mut self) -> Dma1tselW<'_, Dmactl0Spec> {
Dma1tselW::new(self, 8)
}
}
#[doc = "DMA Module Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl0Spec;
impl crate::RegisterSpec for Dmactl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl0::R`](R) reader structure"]
impl crate::Readable for Dmactl0Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl0::W`](W) writer structure"]
impl crate::Writable for Dmactl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL0 to value 0"]
impl crate::Resettable for Dmactl0Spec {}