Struct cc3220sf::stackdie_ctrl::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub stk_up_reset: STK_UP_RESET,
    pub sr_master_priority: SR_MASTER_PRIORITY,
    pub stk_sr_acc_ctl_bk2: STK_SR_ACC_CTL_BK2,
    pub base_up_acc_req_bk2: BASE_UP_ACC_REQ_BK2,
    pub stk_up_acc_req_bk2: STK_UP_ACC_REQ_BK2,
    pub stk_sr_acc_ctl_bk3: STK_SR_ACC_CTL_BK3,
    pub base_up_acc_req_bk3: BASE_UP_ACC_REQ_BK3,
    pub stk_up_acc_req_bk3: STK_UP_ACC_REQ_BK3,
    pub rdsm_cfg_cpu: RDSM_CFG_CPU,
    pub rdsm_cfg_ee: RDSM_CFG_EE,
    pub base_up_irq_log: BASE_UP_IRQ_LOG,
    pub stk_up_irq_log: STK_UP_IRQ_LOG,
    pub stk_clk_en: STK_CLK_EN,
    pub spin_lock_mode: SPIN_LOCK_MODE,
    pub bus_fault_addr: BUS_FAULT_ADDR,
    pub bus_fault_clr: BUS_FAULT_CLR,
    pub reset_cause: RESET_CAUSE,
    pub wdog_timer_event: WDOG_TIMER_EVENT,
    pub dma_req: DMA_REQ,
    pub sram_jump_offset_addr: SRAM_JUMP_OFFSET_ADDR,
    pub sw_reg1: SW_REG1,
    pub sw_reg2: SW_REG2,
    pub fmc_sleep_ctl: FMC_SLEEP_CTL,
    pub misc_ctl: MISC_CTL,
    pub sw_dft_ctl: SW_DFT_CTL,
    pub padn_ctl_0: PADN_CTL_0,
    // some fields omitted
}

Register block

Fields

stk_up_reset: STK_UP_RESET

0x00 - Can be written only by Base Processor. Writing to this register will reset the stack processor reset will be de-asserted upon clearing this register.

sr_master_priority: SR_MASTER_PRIORITY

0x04 - This register defines who among base processor and stack processor have highest priority for Sram Access. Can be written only by Base Processor.

stk_sr_acc_ctl_bk2: STK_SR_ACC_CTL_BK2

0x08 - In Spinlock mode this Register defines who among base processor and stack processor have access to Sram Bank2 right now. In Handshake mode this Register defines who among base processor and stack processor have access to Sram Bank2 and Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.

base_up_acc_req_bk2: BASE_UP_ACC_REQ_BK2

0x0c - In Spinlock mode whenever Base processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.

stk_up_acc_req_bk2: STK_UP_ACC_REQ_BK2

0x10 - In Spinlock mode Whenever Stack processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.

stk_sr_acc_ctl_bk3: STK_SR_ACC_CTL_BK3

0x14 - Register defines who among base processor and stack processor have access to Sram Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.

base_up_acc_req_bk3: BASE_UP_ACC_REQ_BK3

0x18 - In Spinlock mode whenever Base processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.

stk_up_acc_req_bk3: STK_UP_ACC_REQ_BK3

0x1c - In Spinlock mode Whenever Stack processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.

rdsm_cfg_cpu: RDSM_CFG_CPU

0x20 - Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.

rdsm_cfg_ee: RDSM_CFG_EE

0x24 - Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.

base_up_irq_log: BASE_UP_IRQ_LOG

0x28 - Reading this register Base procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Base processor and can be cleared only by BASE processor.

stk_up_irq_log: STK_UP_IRQ_LOG

0x2c - Reading this register Stack procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Stack processor and can be cleared only by Stack processor.

stk_clk_en: STK_CLK_EN

0x30 - Can be written only by base processor. Controls the enable pin of the cgcs for the clocks going to CM3 dft ctrl block and Sram.

spin_lock_mode: SPIN_LOCK_MODE

0x34 - Can be written only by the base processor. Decides the ram sharing mode :: handshake or Spinlock mode.

bus_fault_addr: BUS_FAULT_ADDR

0x38 - Stores the last bus fault address.

bus_fault_clr: BUS_FAULT_CLR

0x3c - write only registers on read returns 0.W Write 1 to clear the bust fault to store the new bus fault address

reset_cause: RESET_CAUSE

0x40 - Reset cause value captured from the ICR_CLKRST block.

wdog_timer_event: WDOG_TIMER_EVENT

0x44 - Watchdog timer event value captured from the ICR_CLKRST block

dma_req: DMA_REQ

0x48 - To send Dma Request to bottom die.

sram_jump_offset_addr: SRAM_JUMP_OFFSET_ADDR

0x4c - Address offset within SRAM to which CM3 should jump after reset.

sw_reg1: SW_REG1

0x50 - These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.

sw_reg2: SW_REG2

0x54 - These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.

fmc_sleep_ctl: FMC_SLEEP_CTL

0x58 - By posting the request Flash can be put into low-power mode (Sleep) without powering down the Flash. Earlier (in Garnet) this was fully h/w controlled and the control for this was coming from SysCtl while entering into Cortex Deep-sleep mode. But for our device the D2D i/f doesnt support this. The Firmware has to program the register in the top-die for entering into this mode and wait for an interrupt.

misc_ctl: MISC_CTL

0x5c - Miscellanious control register.

sw_dft_ctl: SW_DFT_CTL

0xfc - DFT control and status bits

padn_ctl_0: PADN_CTL_0

0x100 - Mainly for For controlling the pads OEN pins. There are total 60 pads and hence 60 control registe i.e n value varies from 0 to 59. Here is the mapping for the pad_ctl register number and the functionality : 0 D2DPAD_DMAREQ1 1 D2DPAD_DMAREQ0 2 D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS 10 D2DPAD_JTAG_TDI 11-27 D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE -1:0] 28-56 D2DPAD_TOSTACK [D2D_TOSTACK_SIZE -1:0] 57-59 D2DPAD_SPARE [D2D_SPARE_PAD_SIZE -1:0] 0:00 ****************************************************************************