[][src]Type Definition cc3220sf::stackdie_ctrl::STK_SR_ACC_CTL_BK3

type STK_SR_ACC_CTL_BK3 = Reg<u32, _STK_SR_ACC_CTL_BK3>;

Register defines who among base processor and stack processor have access to Sram Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see stk_sr_acc_ctl_bk3 module

Trait Implementations

impl Readable for STK_SR_ACC_CTL_BK3[src]

read() method returns stk_sr_acc_ctl_bk3::R reader structure

impl ResetValue for STK_SR_ACC_CTL_BK3[src]

Register STK_SR_ACC_CTL_BK3 reset()'s with value 0

type Type = u32

Register size

impl Writable for STK_SR_ACC_CTL_BK3[src]

write(|w| ..) method takes stk_sr_acc_ctl_bk3::W writer structure