#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::SUBSECINC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct RESERVED24R {
bits: u8,
}
impl RESERVED24R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct VALUEINCR {
bits: u32,
}
impl VALUEINCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 24:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior."]
#[inline]
pub fn reserved24(&self) -> RESERVED24R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RESERVED24R { bits }
}
#[doc = "Bits 0:23 - This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value can be found as 2^38 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits \\[23:6\\] are aligned with SUBSEC.VALUE bits \\[17:0\\]. The remaining bits \\[5:0\\] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and AUX_WUC:RTCSUBSECINCCTL"]
#[inline]
pub fn valueinc(&self) -> VALUEINCR {
let bits = {
const MASK: u32 = 16777215;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VALUEINCR { bits }
}
}