calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    add = std_add(32);
  }
  wires {
    group do_add {
      add.right = do_add[go] ? 32'd4;
      add.left = do_add[go] ? 32'd4;
      do_add[done] = 1'd1;
    }
  }
  control {}
}