calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
comb component layout_hw0() -> (flat_port_addr0: 4) {
  cells {
    add_0 = std_add(4);
  }
  wires {
    flat_port_addr0 = add_0.out;
    add_0.left = 4'd1;
    add_0.right = 4'd2;
  }
}
component main(@clk clk: 1, @go go: 1, @reset reset: 1) -> (out: 32, @done done: 1) {
  cells {
    r = std_reg(32);
  }
  wires {
    out = r.out;
    r.clk = clk;
  }
  control {}
}