calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main() -> () {
  cells {
    @external(1) i = comb_mem_d1(32, 1, 1);
    lt = std_lt(32);
    lt_reg = std_reg(1);
    add = std_add(32);
  }

  wires {
    group cond {
      i.addr0 = 1'd0;
      lt.left = i.read_data;
      lt.right = 32'd8;
      lt_reg.in = lt.out;
      lt_reg.write_en = 1'b1;
      cond[done] = lt_reg.done;
    }

    group incr<"static"=1> {
      add.right = i.read_data;
      add.left = 32'd1;

      i.write_data = add.out;
      i.addr0 = 1'd0;
      i.write_en = 1'b1;

      incr[done] = i.done;
    }
  }

  control {
    seq {
      cond;
      while lt_reg.out {
        seq {
          incr;
          incr;
          cond;
        }
      }
    }
  }
}