calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main(@go go: 1) -> (@done done: 1) {
  cells {
    @external mem = comb_mem_d1(32, 1, 1);
    slice = std_bit_slice(32, 10, 14, 4);
    pad = std_pad(4, 32);
  }

  wires {
    group bit_slice {
      slice.in = 32'b00000000000000110010010110110000;

      pad.in = slice.out;

      mem.addr0 = 1'b0;
      mem.write_data = pad.out;
      mem.write_en = 1'b1;

      bit_slice[done] = mem.done;
    }
  }

  control {
    bit_slice;
  }
}