calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

extern "sync.sv" {
  //// ANCHOR: sync_interface
  primitive std_sync_reg[WIDTH](
    @write_together(1) in_0: WIDTH,
    @write_together(2) in_1: WIDTH,
    read_en_0: 1,
    read_en_1: 1, 
    @write_together(1) write_en_0: 1,
    @write_together(2) write_en_1: 1,
    @clk clk: 1,
    @reset reset: 1
  ) -> (
    out_0: WIDTH,
    out_1: WIDTH,
    write_done_0: 1,
    write_done_1: 1,
    read_done_0: 1,
    read_done_1: 1,
    peek: WIDTH
  );
  //// ANCHOR_END: sync_interface
}