calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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extern "pipelined.sv" {
    // A latency-sensitive multiplier that takes 4 cycles to compute its result.
    static<4> primitive pipelined_mult[WIDTH] (
        @clk clk: 1,
        @reset reset: 1,
        left: WIDTH,
        right: WIDTH
    ) -> (
        out: WIDTH
    );

    // A latency-sensitive multiplier that takes 4 cycles to compute its result.
    static<4> primitive pipelined_fp_smult [
        WIDTH, INT_WIDTH, FRAC_WIDTH
    ] (
        @clk clk: 1,
        @reset reset: 1,
        left: WIDTH,
        right: WIDTH
    ) -> (
        out: WIDTH
    );

}