calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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/// Represents an undefined value. Should never appear in the output of a program.
primitive undef<"share"=1>[WIDTH]() -> (out: WIDTH) {
    assign out = 'x;
}

/// Constants
comb primitive std_const<"share"=1>[WIDTH, VALUE]() -> (out: WIDTH) {
    assign out = VALUE;
}

/// Combinational wire to forward values
comb primitive std_wire<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH) {
    assign out = in;
}

/// Add two numbers.
comb primitive std_add<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH) {
  assign out = left + right;
}

/// Standard register with a one-cycle latency.
// ANCHOR: std_reg_def
primitive std_reg<"state_share"=1>[WIDTH](
  @write_together(1) @data in: WIDTH,
  @write_together(1) @interval(1) @go write_en: 1,
  @clk clk: 1,
  @reset reset: 1
) -> (
  @stable out: WIDTH,
  @done done: 1
)
// ANCHOR_END: std_reg_def
{
  always_ff @(posedge clk) begin
    if (reset) begin
       out <= 0;
       done <= 0;
    end else if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else done <= 1'd0;
  end
}