calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
component main() -> () {
  cells {
    @external(1) A0 = comb_mem_d1(32,8,4);
    A_read0_0 = std_reg(32);
    @external(1) B0 = comb_mem_d1(32,8,4);
    B_read0_0 = std_reg(32);
    @external(1) Sum0 = comb_mem_d1(32,8,4);
    add0 = std_add(32);
    add1 = std_add(4);
    const0 = std_const(4,0);
    const1 = std_const(4,7);
    const2 = std_const(4,1);
    i0 = std_reg(4);
    le0 = std_le(4);
  }
  wires {
    comb group cond0 {
      le0.left = i0.out;
      le0.right = const1.out;
    }
    group let0<"promotable"=1> {
      i0.in = const0.out;
      i0.write_en = 1'd1;
      let0[done] = i0.done;
    }
    group upd0<"promotable"=1> {
      A_read0_0.write_en = 1'd1;
      A0.addr0 = i0.out;
      A_read0_0.in = 1'd1 ? A0.read_data;
      upd0[done] = A_read0_0.done ? 1'd1;
    }
    group upd1<"promotable"=1> {
      B_read0_0.write_en = 1'd1;
      B0.addr0 = i0.out;
      B_read0_0.in = 1'd1 ? B0.read_data;
      upd1[done] = B_read0_0.done ? 1'd1;
    }
    group upd2<"promotable"=1> {
      Sum0.addr0 = i0.out;
      Sum0.write_en = 1'd1;
      add0.left = A_read0_0.out;
      add0.right = B_read0_0.out;
      Sum0.write_data = 1'd1 ? add0.out;
      upd2[done] = Sum0.done ? 1'd1;
    }
    group upd3<"promotable"=1> {
      i0.write_en = 1'd1;
      add1.left = i0.out;
      add1.right = const2.out;
      i0.in = 1'd1 ? add1.out;
      upd3[done] = i0.done ? 1'd1;
    }
  }
  control {
    seq {
      let0;
      while le0.out with cond0 {
        seq {
          par {
            upd0;
            upd1;
          }
          upd2;
          upd3;
        }
      }
    }
  }
}