calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/binary_operators.futil";

// *NOTE*: This was hand-written, and does not demonstrate the capabilities of Calyx.

// A simple example that takes the sum and product of two constants,
// and places each in its own register.
component main() -> () {
  cells {
    const0 = std_const(32, 4);       // 32-bit width constant with value 4.
    const1 = std_const(32, 5);       // 32-bit width constant with value 5.

    add    = std_add(32);            // 32-bit width adder.
    mult   = std_mult_pipe(32);      // 32-bit width multiply pipeline.

    reg0   = std_reg(32);            // 32-bit width register.
    reg1   = std_reg(32);            // 32-bit width register.
  }

  wires {
    group add_constants<"promotable"=1> {       // This group will finish in 1 cycle.
      add.left = const0.out;                // 4
      add.right = const1.out;               // 5
      reg0.in = add.out;                    // 4 + 5 = 9
      reg0.write_en = 1'd1;                 // Enable writes for register 0.
      add_constants[done] = reg0.done;      // Signify this group is done.
    }
    group multiply_constants {
      mult.left = const0.out;               // 4
      mult.right = const1.out;              // 5
      reg1.in = mult.out;                   // 4 * 5 = 20
      mult.go = !mult.done ? 1'd1;          // Initiate the pipeline.
      reg1.write_en = mult.done;            // Enable writes for register 1 when the pipeline is complete.
      multiply_constants[done] = reg1.done; // Signify this group is done.
    }
  }

  control {
    seq {                           // These are done sequentially.
      add_constants;                // Put 9 in reg0.
      multiply_constants;           // Put 20 in reg1.
    }
  }
}