calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/binary_operators.futil";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    @external @data A0 = comb_mem_d1(32, 8, 4);
    @data A_read0_0 = std_reg(32);
    @external @data B0 = comb_mem_d1(32, 8, 4);
    @data B_read0_0 = std_reg(32);
    @data add0 = std_add(32);
    @data add1 = std_add(4);
    @data const0 = std_const(4, 0);
    @control const1 = std_const(4, 7);
    @control const2 = std_const(1, 0);
    @data const3 = std_const(4, 1);
    @data i0 = std_reg(4);
    @control le0 = std_le(4);
    @data mult_pipe0 = std_mult_pipe(32);
    @external @data v0 = comb_mem_d1(32, 1, 1);
    @generated comb_reg = std_reg(1);
    @generated fsm = std_reg(4);
    @generated ud = undef(1);
    @generated adder = std_add(4);
    @generated ud0 = undef(1);
    @generated adder0 = std_add(4);
    @generated signal_reg = std_reg(1);
    @generated fsm0 = std_reg(2);
    @generated invoke0_go = std_wire(1);
    @generated invoke0_done = std_wire(1);
    @generated early_reset_cond00_go = std_wire(1);
    @generated early_reset_cond00_done = std_wire(1);
    @generated early_reset_static_seq_go = std_wire(1);
    @generated early_reset_static_seq_done = std_wire(1);
    @generated wrapper_early_reset_cond00_go = std_wire(1);
    @generated wrapper_early_reset_cond00_done = std_wire(1);
    @generated while_wrapper_early_reset_static_seq_go = std_wire(1);
    @generated while_wrapper_early_reset_static_seq_done = std_wire(1);
    @generated tdcc_go = std_wire(1);
    @generated tdcc_done = std_wire(1);
  }
  wires {
    i0.write_en = invoke0_go.out | fsm.out == 4'd1 & early_reset_static_seq_go.out ? 1'd1;
    i0.clk = clk;
    i0.reset = reset;
    i0.in = fsm.out == 4'd1 & early_reset_static_seq_go.out ? add1.out;
    i0.in = invoke0_go.out ? const0.out;
    early_reset_cond00_go.in = wrapper_early_reset_cond00_go.out ? 1'd1;
    add1.left = fsm.out == 4'd1 & early_reset_static_seq_go.out ? i0.out;
    add1.right = fsm.out == 4'd1 & early_reset_static_seq_go.out ? const3.out;
    done = tdcc_done.out ? 1'd1;
    fsm.write_en = early_reset_cond00_go.out | early_reset_static_seq_go.out ? 1'd1;
    fsm.clk = clk;
    fsm.reset = reset;
    fsm.in = fsm.out != 4'd0 & early_reset_cond00_go.out ? adder.out;
    fsm.in = fsm.out == 4'd0 & early_reset_cond00_go.out | fsm.out == 4'd7 & early_reset_static_seq_go.out ? 4'd0;
    fsm.in = fsm.out != 4'd7 & early_reset_static_seq_go.out ? adder0.out;
    adder.left = early_reset_cond00_go.out ? fsm.out;
    adder.right = early_reset_cond00_go.out ? 4'd1;
    add0.left = fsm.out == 4'd6 & early_reset_static_seq_go.out ? v0.read_data;
    add0.right = fsm.out == 4'd6 & early_reset_static_seq_go.out ? B_read0_0.out;
    v0.write_en = fsm.out == 4'd6 & early_reset_static_seq_go.out ? 1'd1;
    v0.clk = clk;
    v0.addr0 = fsm.out == 4'd6 & early_reset_static_seq_go.out ? const2.out;
    v0.reset = reset;
    v0.write_data = fsm.out == 4'd6 & early_reset_static_seq_go.out ? add0.out;
    comb_reg.write_en = early_reset_cond00_go.out | fsm.out == 4'd7 & early_reset_static_seq_go.out ? 1'd1;
    comb_reg.clk = clk;
    comb_reg.reset = reset;
    comb_reg.in = early_reset_cond00_go.out | fsm.out == 4'd7 & early_reset_static_seq_go.out ? le0.out;
    early_reset_cond00_done.in = ud.out;
    while_wrapper_early_reset_static_seq_go.in = !while_wrapper_early_reset_static_seq_done.out & fsm0.out == 2'd2 & tdcc_go.out ? 1'd1;
    invoke0_go.in = !invoke0_done.out & fsm0.out == 2'd0 & tdcc_go.out ? 1'd1;
    tdcc_go.in = go;
    A0.clk = clk;
    A0.addr0 = fsm.out == 4'd0 & early_reset_static_seq_go.out ? i0.out;
    A0.reset = reset;
    fsm0.write_en = fsm0.out == 2'd3 | fsm0.out == 2'd0 & invoke0_done.out & tdcc_go.out | fsm0.out == 2'd1 & wrapper_early_reset_cond00_done.out & tdcc_go.out | fsm0.out == 2'd2 & while_wrapper_early_reset_static_seq_done.out & tdcc_go.out ? 1'd1;
    fsm0.clk = clk;
    fsm0.reset = reset;
    fsm0.in = fsm0.out == 2'd0 & invoke0_done.out & tdcc_go.out ? 2'd1;
    fsm0.in = fsm0.out == 2'd3 ? 2'd0;
    fsm0.in = fsm0.out == 2'd2 & while_wrapper_early_reset_static_seq_done.out & tdcc_go.out ? 2'd3;
    fsm0.in = fsm0.out == 2'd1 & wrapper_early_reset_cond00_done.out & tdcc_go.out ? 2'd2;
    mult_pipe0.clk = clk;
    mult_pipe0.left = fsm.out >= 4'd1 & fsm.out < 4'd4 & early_reset_static_seq_go.out ? A_read0_0.out;
    mult_pipe0.go = fsm.out >= 4'd1 & fsm.out < 4'd4 & early_reset_static_seq_go.out ? 1'd1;
    mult_pipe0.reset = reset;
    mult_pipe0.right = fsm.out >= 4'd1 & fsm.out < 4'd4 & early_reset_static_seq_go.out ? B_read0_0.out;
    adder0.left = early_reset_static_seq_go.out ? fsm.out;
    adder0.right = early_reset_static_seq_go.out ? 4'd1;
    invoke0_done.in = i0.done;
    early_reset_static_seq_go.in = while_wrapper_early_reset_static_seq_go.out ? 1'd1;
    le0.left = early_reset_cond00_go.out | fsm.out == 4'd7 & early_reset_static_seq_go.out ? i0.out;
    le0.right = early_reset_cond00_go.out | fsm.out == 4'd7 & early_reset_static_seq_go.out ? const1.out;
    signal_reg.write_en = fsm.out == 4'd0 & signal_reg.out | fsm.out == 4'd0 & !signal_reg.out & wrapper_early_reset_cond00_go.out ? 1'd1;
    signal_reg.clk = clk;
    signal_reg.reset = reset;
    signal_reg.in = fsm.out == 4'd0 & !signal_reg.out & wrapper_early_reset_cond00_go.out ? 1'd1;
    signal_reg.in = fsm.out == 4'd0 & signal_reg.out ? 1'd0;
    B0.clk = clk;
    B0.addr0 = fsm.out == 4'd0 & early_reset_static_seq_go.out ? i0.out;
    B0.reset = reset;
    B_read0_0.write_en = (fsm.out == 4'd0 | fsm.out == 4'd5) & early_reset_static_seq_go.out ? 1'd1;
    B_read0_0.clk = clk;
    B_read0_0.reset = reset;
    B_read0_0.in = fsm.out == 4'd0 & early_reset_static_seq_go.out ? B0.read_data;
    B_read0_0.in = fsm.out == 4'd5 & early_reset_static_seq_go.out ? A_read0_0.out;
    wrapper_early_reset_cond00_go.in = !wrapper_early_reset_cond00_done.out & fsm0.out == 2'd1 & tdcc_go.out ? 1'd1;
    wrapper_early_reset_cond00_done.in = fsm.out == 4'd0 & signal_reg.out ? 1'd1;
    early_reset_static_seq_done.in = ud0.out;
    tdcc_done.in = fsm0.out == 2'd3 ? 1'd1;
    while_wrapper_early_reset_static_seq_done.in = !comb_reg.out & fsm.out == 4'd0 ? 1'd1;
    A_read0_0.write_en = (fsm.out == 4'd0 | fsm.out == 4'd4) & early_reset_static_seq_go.out ? 1'd1;
    A_read0_0.clk = clk;
    A_read0_0.reset = reset;
    A_read0_0.in = fsm.out == 4'd0 & early_reset_static_seq_go.out ? A0.read_data;
    A_read0_0.in = fsm.out == 4'd4 & early_reset_static_seq_go.out ? mult_pipe0.out;
    A0.write_en = 1'd0;
    B0.write_en = 1'd0;
  }
  control {}
}