bender 0.31.0

A dependency management tool for hardware projects.
Documentation 
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# {{HEADER_AUTOGEN}}
set ROOT "{{ root }}"
set search_path_initial $search_path
{% if compilation_mode == 'separate' %}{#                                                                           Individual block for each source file group
#}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
set search_path $search_path_initial
{% for incdir in group.incdirs %}{#                                                                                 Add group's include directories
#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{#                                                                      Catch errors immediately
#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{#    Analyze command for SystemVerilog or VHDL #}
{% if group.file_type == 'verilog' %}{#                                                                             Additional command arguments
#}{% for tmp_arg in verilog_args %}{{ tmp_arg }} \
{% endfor %}{#
#}{% else %}{#
#}{% for tmp_arg in vhdl_args %}{{ tmp_arg }} \
{% endfor %}{#
#}{% endif %}{#
#}{% for define in group.defines %}{#                                                                               Add group's defines
#}{% if loop.first %}-define { \
        {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}[list \
    {% for file in group.files %}{#                                                                                 Add group's files
#}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
    {% endfor %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{% else %}{# compilation_mode == 'common' #}{#                                                                      Common block for all files
#}{% for file in all_verilog %}{#                                                                                   Loop over verilog files
#}{% if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs %}{#                                                                                   Add all include directories
#}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif %}{#                                                                      Catch errors immediately
#}analyze -format sv \{#                                                                                            Analyze command for SystemVerilog #}
{% for tmp_arg in verilog_args %}{{ tmp_arg }} \
{% endfor %}{#                                                                                                      Additional command arguments
    #}{% for define in all_defines %}{#                                                                             Add all defines
}
#}{% if loop.first %}-define { \
        {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}[list \
    {% endif %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
    {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \{#                        Add all verilog files #}
    {% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{% for file in all_vhdl %}{% if loop.first %}{#                                                                     Loop over all VHDL files
#}{% if abort_on_error %}if {0 == [{% endif %}{#                                                                    Catch errors immediately
#}analyze -format vhdl \{#                                                                                          Analyze command for VHDL #}
{% for tmp_arg in vhdl_args %}{{ tmp_arg }} \
{% endfor %}{#                                                                                                      Additional command arguments
#}    [list \
    {% endif %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
    {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \{#                        Add all VHDL files #}
    {% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{% endif %}set search_path $search_path_initial