bender 0.31.0

A dependency management tool for hardware projects.
Documentation 
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# {{ HEADER_AUTOGEN }}
# Precision does not take relative paths into account when specifying include dirs.
# Define the common ROOT anyway if needed for patching file paths.
set ROOT {{ root }}
set_input_dir $ROOT
setup_design -search_path $ROOT
{% for define in all_defines %}{% if loop.first %}
# Set globally all defines for the (S)Verilog sources.
setup_design -defines { \
    {% endif %}+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %}

{% else %} \
    {% endif %}{% endfor %}{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}# {{ group.metadata }}
{% endif %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
    {% if group.file_type == 'verilog' %}-format SystemVerilog2012 \
    {% for incdir in group.incdirs %}{% if loop.first %}-search_path { \
        {% endif %}{{ incdir }}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}{% elif group.file_type == 'vhdl' %}-format vhdl_2008 \
    {% endif %}{ \
        {% for file in group.files %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
        {% endif %}{% endif %}{{ file.file }}{% if loop.last %} \
    {% else %} \
        {% endif %}{% endfor %}} \
{% if abort_on_error %}}]} {return 1}
{% endif %}
{% endif %}{% endfor %}
{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
    -format SystemVerilog2012 \
    {% for incdir in all_incdirs %}{% if loop.first %}-search_path { \
        {% endif %}{{ incdir }}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}{ \
        {% endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
        {% endif %}{% endif %}{{ file.file }}{% if loop.last %} \
    {% else %} \
        {% endif %}{% if loop.last %}} \
{% if abort_on_error %}}]} {return 1}
{% endif %}
{% endif %}{% endfor %}
{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
    -format vhdl_2008 \
    { \
        {% endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
        {% endif %}{% endif %}{{ file.file }}{% if loop.last %} \
    {% else %} \
        {% endif %}{% if loop.last %}} \
{% if abort_on_error %}}]} {return 1}
{% endif %}
{% endif %}{% endfor %}
{% endif %}