#[doc = "Register `ECC_sec_enable_set_reg0` reader"]
pub type R = crate::R<EccSecEnableSetReg0Spec>;
#[doc = "Register `ECC_sec_enable_set_reg0` writer"]
pub type W = crate::W<EccSecEnableSetReg0Spec>;
#[doc = "Field `INTERRUPT_ENABLE_SET_19` reader - 0:0\\]
Interrupt Enable Set Register for ramecc0_pend"]
pub type InterruptEnableSet19R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_19` writer - 0:0\\]
Interrupt Enable Set Register for ramecc0_pend"]
pub type InterruptEnableSet19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_18` reader - 1:1\\]
Interrupt Enable Set Register for ramecc1_pend"]
pub type InterruptEnableSet18R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_18` writer - 1:1\\]
Interrupt Enable Set Register for ramecc1_pend"]
pub type InterruptEnableSet18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_17` reader - 2:2\\]
Interrupt Enable Set Register for ramecc2_pend"]
pub type InterruptEnableSet17R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_17` writer - 2:2\\]
Interrupt Enable Set Register for ramecc2_pend"]
pub type InterruptEnableSet17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_16` reader - 3:3\\]
Interrupt Enable Set Register for ramecc3_pend"]
pub type InterruptEnableSet16R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_16` writer - 3:3\\]
Interrupt Enable Set Register for ramecc3_pend"]
pub type InterruptEnableSet16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_15` reader - 4:4\\]
Interrupt Enable Set Register for ramecc4_pend"]
pub type InterruptEnableSet15R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_15` writer - 4:4\\]
Interrupt Enable Set Register for ramecc4_pend"]
pub type InterruptEnableSet15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_14` reader - 5:5\\]
Interrupt Enable Set Register for ramecc5_pend"]
pub type InterruptEnableSet14R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_14` writer - 5:5\\]
Interrupt Enable Set Register for ramecc5_pend"]
pub type InterruptEnableSet14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_13` reader - 6:6\\]
Interrupt Enable Set Register for ramecc6_pend"]
pub type InterruptEnableSet13R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_13` writer - 6:6\\]
Interrupt Enable Set Register for ramecc6_pend"]
pub type InterruptEnableSet13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_12` reader - 7:7\\]
Interrupt Enable Set Register for ramecc7_pend"]
pub type InterruptEnableSet12R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_12` writer - 7:7\\]
Interrupt Enable Set Register for ramecc7_pend"]
pub type InterruptEnableSet12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_11` reader - 8:8\\]
Interrupt Enable Set Register for ramecc8_pend"]
pub type InterruptEnableSet11R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_11` writer - 8:8\\]
Interrupt Enable Set Register for ramecc8_pend"]
pub type InterruptEnableSet11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_10` reader - 9:9\\]
Interrupt Enable Set Register for ramecc9_pend"]
pub type InterruptEnableSet10R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_10` writer - 9:9\\]
Interrupt Enable Set Register for ramecc9_pend"]
pub type InterruptEnableSet10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_9` reader - 10:10\\]
Interrupt Enable Set Register for ramecc10_pend"]
pub type InterruptEnableSet9R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_9` writer - 10:10\\]
Interrupt Enable Set Register for ramecc10_pend"]
pub type InterruptEnableSet9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_8` reader - 11:11\\]
Interrupt Enable Set Register for ramecc11_pend"]
pub type InterruptEnableSet8R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_8` writer - 11:11\\]
Interrupt Enable Set Register for ramecc11_pend"]
pub type InterruptEnableSet8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_7` reader - 12:12\\]
Interrupt Enable Set Register for ramecc12_pend"]
pub type InterruptEnableSet7R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_7` writer - 12:12\\]
Interrupt Enable Set Register for ramecc12_pend"]
pub type InterruptEnableSet7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_6` reader - 13:13\\]
Interrupt Enable Set Register for ramecc13_pend"]
pub type InterruptEnableSet6R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_6` writer - 13:13\\]
Interrupt Enable Set Register for ramecc13_pend"]
pub type InterruptEnableSet6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_5` reader - 14:14\\]
Interrupt Enable Set Register for ramecc14_pend"]
pub type InterruptEnableSet5R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_5` writer - 14:14\\]
Interrupt Enable Set Register for ramecc14_pend"]
pub type InterruptEnableSet5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_4` reader - 15:15\\]
Interrupt Enable Set Register for ramecc15_pend"]
pub type InterruptEnableSet4R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_4` writer - 15:15\\]
Interrupt Enable Set Register for ramecc15_pend"]
pub type InterruptEnableSet4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_3` reader - 16:16\\]
Interrupt Enable Set Register for ramecc16_pend"]
pub type InterruptEnableSet3R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_3` writer - 16:16\\]
Interrupt Enable Set Register for ramecc16_pend"]
pub type InterruptEnableSet3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_2` reader - 17:17\\]
Interrupt Enable Set Register for ramecc17_pend"]
pub type InterruptEnableSet2R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_2` writer - 17:17\\]
Interrupt Enable Set Register for ramecc17_pend"]
pub type InterruptEnableSet2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET_1` reader - 18:18\\]
Interrupt Enable Set Register for ramecc18_pend"]
pub type InterruptEnableSet1R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET_1` writer - 18:18\\]
Interrupt Enable Set Register for ramecc18_pend"]
pub type InterruptEnableSet1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_SET` reader - 19:19\\]
Interrupt Enable Set Register for ramecc19_pend"]
pub type InterruptEnableSetR = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_SET` writer - 19:19\\]
Interrupt Enable Set Register for ramecc19_pend"]
pub type InterruptEnableSetW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for ramecc0_pend"]
#[inline(always)]
pub fn interrupt_enable_set_19(&self) -> InterruptEnableSet19R {
InterruptEnableSet19R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ramecc1_pend"]
#[inline(always)]
pub fn interrupt_enable_set_18(&self) -> InterruptEnableSet18R {
InterruptEnableSet18R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for ramecc2_pend"]
#[inline(always)]
pub fn interrupt_enable_set_17(&self) -> InterruptEnableSet17R {
InterruptEnableSet17R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for ramecc3_pend"]
#[inline(always)]
pub fn interrupt_enable_set_16(&self) -> InterruptEnableSet16R {
InterruptEnableSet16R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for ramecc4_pend"]
#[inline(always)]
pub fn interrupt_enable_set_15(&self) -> InterruptEnableSet15R {
InterruptEnableSet15R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for ramecc5_pend"]
#[inline(always)]
pub fn interrupt_enable_set_14(&self) -> InterruptEnableSet14R {
InterruptEnableSet14R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for ramecc6_pend"]
#[inline(always)]
pub fn interrupt_enable_set_13(&self) -> InterruptEnableSet13R {
InterruptEnableSet13R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for ramecc7_pend"]
#[inline(always)]
pub fn interrupt_enable_set_12(&self) -> InterruptEnableSet12R {
InterruptEnableSet12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for ramecc8_pend"]
#[inline(always)]
pub fn interrupt_enable_set_11(&self) -> InterruptEnableSet11R {
InterruptEnableSet11R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for ramecc9_pend"]
#[inline(always)]
pub fn interrupt_enable_set_10(&self) -> InterruptEnableSet10R {
InterruptEnableSet10R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for ramecc10_pend"]
#[inline(always)]
pub fn interrupt_enable_set_9(&self) -> InterruptEnableSet9R {
InterruptEnableSet9R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for ramecc11_pend"]
#[inline(always)]
pub fn interrupt_enable_set_8(&self) -> InterruptEnableSet8R {
InterruptEnableSet8R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for ramecc12_pend"]
#[inline(always)]
pub fn interrupt_enable_set_7(&self) -> InterruptEnableSet7R {
InterruptEnableSet7R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for ramecc13_pend"]
#[inline(always)]
pub fn interrupt_enable_set_6(&self) -> InterruptEnableSet6R {
InterruptEnableSet6R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Enable Set Register for ramecc14_pend"]
#[inline(always)]
pub fn interrupt_enable_set_5(&self) -> InterruptEnableSet5R {
InterruptEnableSet5R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Enable Set Register for ramecc15_pend"]
#[inline(always)]
pub fn interrupt_enable_set_4(&self) -> InterruptEnableSet4R {
InterruptEnableSet4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Enable Set Register for ramecc16_pend"]
#[inline(always)]
pub fn interrupt_enable_set_3(&self) -> InterruptEnableSet3R {
InterruptEnableSet3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Enable Set Register for ramecc17_pend"]
#[inline(always)]
pub fn interrupt_enable_set_2(&self) -> InterruptEnableSet2R {
InterruptEnableSet2R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Enable Set Register for ramecc18_pend"]
#[inline(always)]
pub fn interrupt_enable_set_1(&self) -> InterruptEnableSet1R {
InterruptEnableSet1R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Enable Set Register for ramecc19_pend"]
#[inline(always)]
pub fn interrupt_enable_set(&self) -> InterruptEnableSetR {
InterruptEnableSetR::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
Interrupt Enable Set Register for ramecc0_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_19(&mut self) -> InterruptEnableSet19W<EccSecEnableSetReg0Spec> {
InterruptEnableSet19W::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Enable Set Register for ramecc1_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_18(&mut self) -> InterruptEnableSet18W<EccSecEnableSetReg0Spec> {
InterruptEnableSet18W::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Enable Set Register for ramecc2_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_17(&mut self) -> InterruptEnableSet17W<EccSecEnableSetReg0Spec> {
InterruptEnableSet17W::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Enable Set Register for ramecc3_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_16(&mut self) -> InterruptEnableSet16W<EccSecEnableSetReg0Spec> {
InterruptEnableSet16W::new(self, 3)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Enable Set Register for ramecc4_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_15(&mut self) -> InterruptEnableSet15W<EccSecEnableSetReg0Spec> {
InterruptEnableSet15W::new(self, 4)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Enable Set Register for ramecc5_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_14(&mut self) -> InterruptEnableSet14W<EccSecEnableSetReg0Spec> {
InterruptEnableSet14W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Enable Set Register for ramecc6_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_13(&mut self) -> InterruptEnableSet13W<EccSecEnableSetReg0Spec> {
InterruptEnableSet13W::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Enable Set Register for ramecc7_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_12(&mut self) -> InterruptEnableSet12W<EccSecEnableSetReg0Spec> {
InterruptEnableSet12W::new(self, 7)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Enable Set Register for ramecc8_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_11(&mut self) -> InterruptEnableSet11W<EccSecEnableSetReg0Spec> {
InterruptEnableSet11W::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Enable Set Register for ramecc9_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_10(&mut self) -> InterruptEnableSet10W<EccSecEnableSetReg0Spec> {
InterruptEnableSet10W::new(self, 9)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Enable Set Register for ramecc10_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_9(&mut self) -> InterruptEnableSet9W<EccSecEnableSetReg0Spec> {
InterruptEnableSet9W::new(self, 10)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Enable Set Register for ramecc11_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_8(&mut self) -> InterruptEnableSet8W<EccSecEnableSetReg0Spec> {
InterruptEnableSet8W::new(self, 11)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Enable Set Register for ramecc12_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_7(&mut self) -> InterruptEnableSet7W<EccSecEnableSetReg0Spec> {
InterruptEnableSet7W::new(self, 12)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Enable Set Register for ramecc13_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_6(&mut self) -> InterruptEnableSet6W<EccSecEnableSetReg0Spec> {
InterruptEnableSet6W::new(self, 13)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Enable Set Register for ramecc14_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_5(&mut self) -> InterruptEnableSet5W<EccSecEnableSetReg0Spec> {
InterruptEnableSet5W::new(self, 14)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Enable Set Register for ramecc15_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_4(&mut self) -> InterruptEnableSet4W<EccSecEnableSetReg0Spec> {
InterruptEnableSet4W::new(self, 15)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Enable Set Register for ramecc16_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_3(&mut self) -> InterruptEnableSet3W<EccSecEnableSetReg0Spec> {
InterruptEnableSet3W::new(self, 16)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Enable Set Register for ramecc17_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_2(&mut self) -> InterruptEnableSet2W<EccSecEnableSetReg0Spec> {
InterruptEnableSet2W::new(self, 17)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Enable Set Register for ramecc18_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set_1(&mut self) -> InterruptEnableSet1W<EccSecEnableSetReg0Spec> {
InterruptEnableSet1W::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Enable Set Register for ramecc19_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_set(&mut self) -> InterruptEnableSetW<EccSecEnableSetReg0Spec> {
InterruptEnableSetW::new(self, 19)
}
}
#[doc = "Interrupt Enable Set Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_sec_enable_set_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_sec_enable_set_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccSecEnableSetReg0Spec;
impl crate::RegisterSpec for EccSecEnableSetReg0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecc_sec_enable_set_reg0::R`](R) reader structure"]
impl crate::Readable for EccSecEnableSetReg0Spec {}
#[doc = "`write(|w| ..)` method takes [`ecc_sec_enable_set_reg0::W`](W) writer structure"]
impl crate::Writable for EccSecEnableSetReg0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ECC_sec_enable_set_reg0 to value 0"]
impl crate::Resettable for EccSecEnableSetReg0Spec {
const RESET_VALUE: u32 = 0;
}