#[doc = "Register `ECC_ded_status_reg0` reader"]
pub type R = crate::R<EccDedStatusReg0Spec>;
#[doc = "Register `ECC_ded_status_reg0` writer"]
pub type W = crate::W<EccDedStatusReg0Spec>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_19` reader - 0:0\\]
Interrupt Pending Status for ramecc0_pend"]
pub type InterruptPendingStatus19R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_19` writer - 0:0\\]
Interrupt Pending Status for ramecc0_pend"]
pub type InterruptPendingStatus19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_18` reader - 1:1\\]
Interrupt Pending Status for ramecc1_pend"]
pub type InterruptPendingStatus18R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_18` writer - 1:1\\]
Interrupt Pending Status for ramecc1_pend"]
pub type InterruptPendingStatus18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_17` reader - 2:2\\]
Interrupt Pending Status for ramecc2_pend"]
pub type InterruptPendingStatus17R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_17` writer - 2:2\\]
Interrupt Pending Status for ramecc2_pend"]
pub type InterruptPendingStatus17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_16` reader - 3:3\\]
Interrupt Pending Status for ramecc3_pend"]
pub type InterruptPendingStatus16R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_16` writer - 3:3\\]
Interrupt Pending Status for ramecc3_pend"]
pub type InterruptPendingStatus16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_15` reader - 4:4\\]
Interrupt Pending Status for ramecc4_pend"]
pub type InterruptPendingStatus15R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_15` writer - 4:4\\]
Interrupt Pending Status for ramecc4_pend"]
pub type InterruptPendingStatus15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_14` reader - 5:5\\]
Interrupt Pending Status for ramecc5_pend"]
pub type InterruptPendingStatus14R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_14` writer - 5:5\\]
Interrupt Pending Status for ramecc5_pend"]
pub type InterruptPendingStatus14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_13` reader - 6:6\\]
Interrupt Pending Status for ramecc6_pend"]
pub type InterruptPendingStatus13R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_13` writer - 6:6\\]
Interrupt Pending Status for ramecc6_pend"]
pub type InterruptPendingStatus13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_12` reader - 7:7\\]
Interrupt Pending Status for ramecc7_pend"]
pub type InterruptPendingStatus12R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_12` writer - 7:7\\]
Interrupt Pending Status for ramecc7_pend"]
pub type InterruptPendingStatus12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_11` reader - 8:8\\]
Interrupt Pending Status for ramecc8_pend"]
pub type InterruptPendingStatus11R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_11` writer - 8:8\\]
Interrupt Pending Status for ramecc8_pend"]
pub type InterruptPendingStatus11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_10` reader - 9:9\\]
Interrupt Pending Status for ramecc9_pend"]
pub type InterruptPendingStatus10R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_10` writer - 9:9\\]
Interrupt Pending Status for ramecc9_pend"]
pub type InterruptPendingStatus10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_9` reader - 10:10\\]
Interrupt Pending Status for ramecc10_pend"]
pub type InterruptPendingStatus9R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_9` writer - 10:10\\]
Interrupt Pending Status for ramecc10_pend"]
pub type InterruptPendingStatus9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_8` reader - 11:11\\]
Interrupt Pending Status for ramecc11_pend"]
pub type InterruptPendingStatus8R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_8` writer - 11:11\\]
Interrupt Pending Status for ramecc11_pend"]
pub type InterruptPendingStatus8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_7` reader - 12:12\\]
Interrupt Pending Status for ramecc12_pend"]
pub type InterruptPendingStatus7R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_7` writer - 12:12\\]
Interrupt Pending Status for ramecc12_pend"]
pub type InterruptPendingStatus7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_6` reader - 13:13\\]
Interrupt Pending Status for ramecc13_pend"]
pub type InterruptPendingStatus6R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_6` writer - 13:13\\]
Interrupt Pending Status for ramecc13_pend"]
pub type InterruptPendingStatus6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_5` reader - 14:14\\]
Interrupt Pending Status for ramecc14_pend"]
pub type InterruptPendingStatus5R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_5` writer - 14:14\\]
Interrupt Pending Status for ramecc14_pend"]
pub type InterruptPendingStatus5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_4` reader - 15:15\\]
Interrupt Pending Status for ramecc15_pend"]
pub type InterruptPendingStatus4R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_4` writer - 15:15\\]
Interrupt Pending Status for ramecc15_pend"]
pub type InterruptPendingStatus4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_3` reader - 16:16\\]
Interrupt Pending Status for ramecc16_pend"]
pub type InterruptPendingStatus3R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_3` writer - 16:16\\]
Interrupt Pending Status for ramecc16_pend"]
pub type InterruptPendingStatus3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_2` reader - 17:17\\]
Interrupt Pending Status for ramecc17_pend"]
pub type InterruptPendingStatus2R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_2` writer - 17:17\\]
Interrupt Pending Status for ramecc17_pend"]
pub type InterruptPendingStatus2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS_1` reader - 18:18\\]
Interrupt Pending Status for ramecc18_pend"]
pub type InterruptPendingStatus1R = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS_1` writer - 18:18\\]
Interrupt Pending Status for ramecc18_pend"]
pub type InterruptPendingStatus1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_PENDING_STATUS` reader - 19:19\\]
Interrupt Pending Status for ramecc19_pend"]
pub type InterruptPendingStatusR = crate::BitReader;
#[doc = "Field `INTERRUPT_PENDING_STATUS` writer - 19:19\\]
Interrupt Pending Status for ramecc19_pend"]
pub type InterruptPendingStatusW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for ramecc0_pend"]
#[inline(always)]
pub fn interrupt_pending_status_19(&self) -> InterruptPendingStatus19R {
InterruptPendingStatus19R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ramecc1_pend"]
#[inline(always)]
pub fn interrupt_pending_status_18(&self) -> InterruptPendingStatus18R {
InterruptPendingStatus18R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for ramecc2_pend"]
#[inline(always)]
pub fn interrupt_pending_status_17(&self) -> InterruptPendingStatus17R {
InterruptPendingStatus17R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for ramecc3_pend"]
#[inline(always)]
pub fn interrupt_pending_status_16(&self) -> InterruptPendingStatus16R {
InterruptPendingStatus16R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for ramecc4_pend"]
#[inline(always)]
pub fn interrupt_pending_status_15(&self) -> InterruptPendingStatus15R {
InterruptPendingStatus15R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for ramecc5_pend"]
#[inline(always)]
pub fn interrupt_pending_status_14(&self) -> InterruptPendingStatus14R {
InterruptPendingStatus14R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for ramecc6_pend"]
#[inline(always)]
pub fn interrupt_pending_status_13(&self) -> InterruptPendingStatus13R {
InterruptPendingStatus13R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for ramecc7_pend"]
#[inline(always)]
pub fn interrupt_pending_status_12(&self) -> InterruptPendingStatus12R {
InterruptPendingStatus12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for ramecc8_pend"]
#[inline(always)]
pub fn interrupt_pending_status_11(&self) -> InterruptPendingStatus11R {
InterruptPendingStatus11R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for ramecc9_pend"]
#[inline(always)]
pub fn interrupt_pending_status_10(&self) -> InterruptPendingStatus10R {
InterruptPendingStatus10R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for ramecc10_pend"]
#[inline(always)]
pub fn interrupt_pending_status_9(&self) -> InterruptPendingStatus9R {
InterruptPendingStatus9R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for ramecc11_pend"]
#[inline(always)]
pub fn interrupt_pending_status_8(&self) -> InterruptPendingStatus8R {
InterruptPendingStatus8R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for ramecc12_pend"]
#[inline(always)]
pub fn interrupt_pending_status_7(&self) -> InterruptPendingStatus7R {
InterruptPendingStatus7R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for ramecc13_pend"]
#[inline(always)]
pub fn interrupt_pending_status_6(&self) -> InterruptPendingStatus6R {
InterruptPendingStatus6R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Pending Status for ramecc14_pend"]
#[inline(always)]
pub fn interrupt_pending_status_5(&self) -> InterruptPendingStatus5R {
InterruptPendingStatus5R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Pending Status for ramecc15_pend"]
#[inline(always)]
pub fn interrupt_pending_status_4(&self) -> InterruptPendingStatus4R {
InterruptPendingStatus4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Pending Status for ramecc16_pend"]
#[inline(always)]
pub fn interrupt_pending_status_3(&self) -> InterruptPendingStatus3R {
InterruptPendingStatus3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Pending Status for ramecc17_pend"]
#[inline(always)]
pub fn interrupt_pending_status_2(&self) -> InterruptPendingStatus2R {
InterruptPendingStatus2R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Pending Status for ramecc18_pend"]
#[inline(always)]
pub fn interrupt_pending_status_1(&self) -> InterruptPendingStatus1R {
InterruptPendingStatus1R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Pending Status for ramecc19_pend"]
#[inline(always)]
pub fn interrupt_pending_status(&self) -> InterruptPendingStatusR {
InterruptPendingStatusR::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
Interrupt Pending Status for ramecc0_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_19(
&mut self,
) -> InterruptPendingStatus19W<EccDedStatusReg0Spec> {
InterruptPendingStatus19W::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Pending Status for ramecc1_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_18(
&mut self,
) -> InterruptPendingStatus18W<EccDedStatusReg0Spec> {
InterruptPendingStatus18W::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Pending Status for ramecc2_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_17(
&mut self,
) -> InterruptPendingStatus17W<EccDedStatusReg0Spec> {
InterruptPendingStatus17W::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Pending Status for ramecc3_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_16(
&mut self,
) -> InterruptPendingStatus16W<EccDedStatusReg0Spec> {
InterruptPendingStatus16W::new(self, 3)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Pending Status for ramecc4_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_15(
&mut self,
) -> InterruptPendingStatus15W<EccDedStatusReg0Spec> {
InterruptPendingStatus15W::new(self, 4)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Pending Status for ramecc5_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_14(
&mut self,
) -> InterruptPendingStatus14W<EccDedStatusReg0Spec> {
InterruptPendingStatus14W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Pending Status for ramecc6_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_13(
&mut self,
) -> InterruptPendingStatus13W<EccDedStatusReg0Spec> {
InterruptPendingStatus13W::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Pending Status for ramecc7_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_12(
&mut self,
) -> InterruptPendingStatus12W<EccDedStatusReg0Spec> {
InterruptPendingStatus12W::new(self, 7)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Pending Status for ramecc8_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_11(
&mut self,
) -> InterruptPendingStatus11W<EccDedStatusReg0Spec> {
InterruptPendingStatus11W::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Pending Status for ramecc9_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_10(
&mut self,
) -> InterruptPendingStatus10W<EccDedStatusReg0Spec> {
InterruptPendingStatus10W::new(self, 9)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Pending Status for ramecc10_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_9(&mut self) -> InterruptPendingStatus9W<EccDedStatusReg0Spec> {
InterruptPendingStatus9W::new(self, 10)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Pending Status for ramecc11_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_8(&mut self) -> InterruptPendingStatus8W<EccDedStatusReg0Spec> {
InterruptPendingStatus8W::new(self, 11)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Pending Status for ramecc12_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_7(&mut self) -> InterruptPendingStatus7W<EccDedStatusReg0Spec> {
InterruptPendingStatus7W::new(self, 12)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Pending Status for ramecc13_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_6(&mut self) -> InterruptPendingStatus6W<EccDedStatusReg0Spec> {
InterruptPendingStatus6W::new(self, 13)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Pending Status for ramecc14_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_5(&mut self) -> InterruptPendingStatus5W<EccDedStatusReg0Spec> {
InterruptPendingStatus5W::new(self, 14)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Pending Status for ramecc15_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_4(&mut self) -> InterruptPendingStatus4W<EccDedStatusReg0Spec> {
InterruptPendingStatus4W::new(self, 15)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Pending Status for ramecc16_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_3(&mut self) -> InterruptPendingStatus3W<EccDedStatusReg0Spec> {
InterruptPendingStatus3W::new(self, 16)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Pending Status for ramecc17_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_2(&mut self) -> InterruptPendingStatus2W<EccDedStatusReg0Spec> {
InterruptPendingStatus2W::new(self, 17)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Pending Status for ramecc18_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status_1(&mut self) -> InterruptPendingStatus1W<EccDedStatusReg0Spec> {
InterruptPendingStatus1W::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Pending Status for ramecc19_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_pending_status(&mut self) -> InterruptPendingStatusW<EccDedStatusReg0Spec> {
InterruptPendingStatusW::new(self, 19)
}
}
#[doc = "Interrupt Status Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_ded_status_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_ded_status_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccDedStatusReg0Spec;
impl crate::RegisterSpec for EccDedStatusReg0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecc_ded_status_reg0::R`](R) reader structure"]
impl crate::Readable for EccDedStatusReg0Spec {}
#[doc = "`write(|w| ..)` method takes [`ecc_ded_status_reg0::W`](W) writer structure"]
impl crate::Writable for EccDedStatusReg0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ECC_ded_status_reg0 to value 0"]
impl crate::Resettable for EccDedStatusReg0Spec {
const RESET_VALUE: u32 = 0;
}