#[doc = "Register `ECC_sec_enable_clr_reg0` reader"]
pub type R = crate::R<EccSecEnableClrReg0Spec>;
#[doc = "Register `ECC_sec_enable_clr_reg0` writer"]
pub type W = crate::W<EccSecEnableClrReg0Spec>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_19` reader - 0:0\\]
Interrupt Enable Clear Register for ramecc0_pend"]
pub type InterruptEnableClear19R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_19` writer - 0:0\\]
Interrupt Enable Clear Register for ramecc0_pend"]
pub type InterruptEnableClear19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_18` reader - 1:1\\]
Interrupt Enable Clear Register for ramecc1_pend"]
pub type InterruptEnableClear18R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_18` writer - 1:1\\]
Interrupt Enable Clear Register for ramecc1_pend"]
pub type InterruptEnableClear18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_17` reader - 2:2\\]
Interrupt Enable Clear Register for ramecc2_pend"]
pub type InterruptEnableClear17R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_17` writer - 2:2\\]
Interrupt Enable Clear Register for ramecc2_pend"]
pub type InterruptEnableClear17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_16` reader - 3:3\\]
Interrupt Enable Clear Register for ramecc3_pend"]
pub type InterruptEnableClear16R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_16` writer - 3:3\\]
Interrupt Enable Clear Register for ramecc3_pend"]
pub type InterruptEnableClear16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_15` reader - 4:4\\]
Interrupt Enable Clear Register for ramecc4_pend"]
pub type InterruptEnableClear15R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_15` writer - 4:4\\]
Interrupt Enable Clear Register for ramecc4_pend"]
pub type InterruptEnableClear15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_14` reader - 5:5\\]
Interrupt Enable Clear Register for ramecc5_pend"]
pub type InterruptEnableClear14R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_14` writer - 5:5\\]
Interrupt Enable Clear Register for ramecc5_pend"]
pub type InterruptEnableClear14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_13` reader - 6:6\\]
Interrupt Enable Clear Register for ramecc6_pend"]
pub type InterruptEnableClear13R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_13` writer - 6:6\\]
Interrupt Enable Clear Register for ramecc6_pend"]
pub type InterruptEnableClear13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_12` reader - 7:7\\]
Interrupt Enable Clear Register for ramecc7_pend"]
pub type InterruptEnableClear12R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_12` writer - 7:7\\]
Interrupt Enable Clear Register for ramecc7_pend"]
pub type InterruptEnableClear12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_11` reader - 8:8\\]
Interrupt Enable Clear Register for ramecc8_pend"]
pub type InterruptEnableClear11R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_11` writer - 8:8\\]
Interrupt Enable Clear Register for ramecc8_pend"]
pub type InterruptEnableClear11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_10` reader - 9:9\\]
Interrupt Enable Clear Register for ramecc9_pend"]
pub type InterruptEnableClear10R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_10` writer - 9:9\\]
Interrupt Enable Clear Register for ramecc9_pend"]
pub type InterruptEnableClear10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_9` reader - 10:10\\]
Interrupt Enable Clear Register for ramecc10_pend"]
pub type InterruptEnableClear9R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_9` writer - 10:10\\]
Interrupt Enable Clear Register for ramecc10_pend"]
pub type InterruptEnableClear9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_8` reader - 11:11\\]
Interrupt Enable Clear Register for ramecc11_pend"]
pub type InterruptEnableClear8R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_8` writer - 11:11\\]
Interrupt Enable Clear Register for ramecc11_pend"]
pub type InterruptEnableClear8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_7` reader - 12:12\\]
Interrupt Enable Clear Register for ramecc12_pend"]
pub type InterruptEnableClear7R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_7` writer - 12:12\\]
Interrupt Enable Clear Register for ramecc12_pend"]
pub type InterruptEnableClear7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_6` reader - 13:13\\]
Interrupt Enable Clear Register for ramecc13_pend"]
pub type InterruptEnableClear6R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_6` writer - 13:13\\]
Interrupt Enable Clear Register for ramecc13_pend"]
pub type InterruptEnableClear6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_5` reader - 14:14\\]
Interrupt Enable Clear Register for ramecc14_pend"]
pub type InterruptEnableClear5R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_5` writer - 14:14\\]
Interrupt Enable Clear Register for ramecc14_pend"]
pub type InterruptEnableClear5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_4` reader - 15:15\\]
Interrupt Enable Clear Register for ramecc15_pend"]
pub type InterruptEnableClear4R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_4` writer - 15:15\\]
Interrupt Enable Clear Register for ramecc15_pend"]
pub type InterruptEnableClear4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_3` reader - 16:16\\]
Interrupt Enable Clear Register for ramecc16_pend"]
pub type InterruptEnableClear3R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_3` writer - 16:16\\]
Interrupt Enable Clear Register for ramecc16_pend"]
pub type InterruptEnableClear3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_2` reader - 17:17\\]
Interrupt Enable Clear Register for ramecc17_pend"]
pub type InterruptEnableClear2R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_2` writer - 17:17\\]
Interrupt Enable Clear Register for ramecc17_pend"]
pub type InterruptEnableClear2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_1` reader - 18:18\\]
Interrupt Enable Clear Register for ramecc18_pend"]
pub type InterruptEnableClear1R = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR_1` writer - 18:18\\]
Interrupt Enable Clear Register for ramecc18_pend"]
pub type InterruptEnableClear1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR` reader - 19:19\\]
Interrupt Enable Clear Register for ramecc19_pend"]
pub type InterruptEnableClearR = crate::BitReader;
#[doc = "Field `INTERRUPT_ENABLE_CLEAR` writer - 19:19\\]
Interrupt Enable Clear Register for ramecc19_pend"]
pub type InterruptEnableClearW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for ramecc0_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_19(&self) -> InterruptEnableClear19R {
InterruptEnableClear19R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ramecc1_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_18(&self) -> InterruptEnableClear18R {
InterruptEnableClear18R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for ramecc2_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_17(&self) -> InterruptEnableClear17R {
InterruptEnableClear17R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for ramecc3_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_16(&self) -> InterruptEnableClear16R {
InterruptEnableClear16R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for ramecc4_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_15(&self) -> InterruptEnableClear15R {
InterruptEnableClear15R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for ramecc5_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_14(&self) -> InterruptEnableClear14R {
InterruptEnableClear14R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for ramecc6_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_13(&self) -> InterruptEnableClear13R {
InterruptEnableClear13R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for ramecc7_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_12(&self) -> InterruptEnableClear12R {
InterruptEnableClear12R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for ramecc8_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_11(&self) -> InterruptEnableClear11R {
InterruptEnableClear11R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for ramecc9_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_10(&self) -> InterruptEnableClear10R {
InterruptEnableClear10R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for ramecc10_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_9(&self) -> InterruptEnableClear9R {
InterruptEnableClear9R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for ramecc11_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_8(&self) -> InterruptEnableClear8R {
InterruptEnableClear8R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for ramecc12_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_7(&self) -> InterruptEnableClear7R {
InterruptEnableClear7R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for ramecc13_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_6(&self) -> InterruptEnableClear6R {
InterruptEnableClear6R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Enable Clear Register for ramecc14_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_5(&self) -> InterruptEnableClear5R {
InterruptEnableClear5R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Enable Clear Register for ramecc15_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_4(&self) -> InterruptEnableClear4R {
InterruptEnableClear4R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Enable Clear Register for ramecc16_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_3(&self) -> InterruptEnableClear3R {
InterruptEnableClear3R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Enable Clear Register for ramecc17_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_2(&self) -> InterruptEnableClear2R {
InterruptEnableClear2R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Enable Clear Register for ramecc18_pend"]
#[inline(always)]
pub fn interrupt_enable_clear_1(&self) -> InterruptEnableClear1R {
InterruptEnableClear1R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Enable Clear Register for ramecc19_pend"]
#[inline(always)]
pub fn interrupt_enable_clear(&self) -> InterruptEnableClearR {
InterruptEnableClearR::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
Interrupt Enable Clear Register for ramecc0_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_19(
&mut self,
) -> InterruptEnableClear19W<EccSecEnableClrReg0Spec> {
InterruptEnableClear19W::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
Interrupt Enable Clear Register for ramecc1_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_18(
&mut self,
) -> InterruptEnableClear18W<EccSecEnableClrReg0Spec> {
InterruptEnableClear18W::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Interrupt Enable Clear Register for ramecc2_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_17(
&mut self,
) -> InterruptEnableClear17W<EccSecEnableClrReg0Spec> {
InterruptEnableClear17W::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Interrupt Enable Clear Register for ramecc3_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_16(
&mut self,
) -> InterruptEnableClear16W<EccSecEnableClrReg0Spec> {
InterruptEnableClear16W::new(self, 3)
}
#[doc = "Bit 4 - 4:4\\]
Interrupt Enable Clear Register for ramecc4_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_15(
&mut self,
) -> InterruptEnableClear15W<EccSecEnableClrReg0Spec> {
InterruptEnableClear15W::new(self, 4)
}
#[doc = "Bit 5 - 5:5\\]
Interrupt Enable Clear Register for ramecc5_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_14(
&mut self,
) -> InterruptEnableClear14W<EccSecEnableClrReg0Spec> {
InterruptEnableClear14W::new(self, 5)
}
#[doc = "Bit 6 - 6:6\\]
Interrupt Enable Clear Register for ramecc6_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_13(
&mut self,
) -> InterruptEnableClear13W<EccSecEnableClrReg0Spec> {
InterruptEnableClear13W::new(self, 6)
}
#[doc = "Bit 7 - 7:7\\]
Interrupt Enable Clear Register for ramecc7_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_12(
&mut self,
) -> InterruptEnableClear12W<EccSecEnableClrReg0Spec> {
InterruptEnableClear12W::new(self, 7)
}
#[doc = "Bit 8 - 8:8\\]
Interrupt Enable Clear Register for ramecc8_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_11(
&mut self,
) -> InterruptEnableClear11W<EccSecEnableClrReg0Spec> {
InterruptEnableClear11W::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
Interrupt Enable Clear Register for ramecc9_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_10(
&mut self,
) -> InterruptEnableClear10W<EccSecEnableClrReg0Spec> {
InterruptEnableClear10W::new(self, 9)
}
#[doc = "Bit 10 - 10:10\\]
Interrupt Enable Clear Register for ramecc10_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_9(&mut self) -> InterruptEnableClear9W<EccSecEnableClrReg0Spec> {
InterruptEnableClear9W::new(self, 10)
}
#[doc = "Bit 11 - 11:11\\]
Interrupt Enable Clear Register for ramecc11_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_8(&mut self) -> InterruptEnableClear8W<EccSecEnableClrReg0Spec> {
InterruptEnableClear8W::new(self, 11)
}
#[doc = "Bit 12 - 12:12\\]
Interrupt Enable Clear Register for ramecc12_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_7(&mut self) -> InterruptEnableClear7W<EccSecEnableClrReg0Spec> {
InterruptEnableClear7W::new(self, 12)
}
#[doc = "Bit 13 - 13:13\\]
Interrupt Enable Clear Register for ramecc13_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_6(&mut self) -> InterruptEnableClear6W<EccSecEnableClrReg0Spec> {
InterruptEnableClear6W::new(self, 13)
}
#[doc = "Bit 14 - 14:14\\]
Interrupt Enable Clear Register for ramecc14_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_5(&mut self) -> InterruptEnableClear5W<EccSecEnableClrReg0Spec> {
InterruptEnableClear5W::new(self, 14)
}
#[doc = "Bit 15 - 15:15\\]
Interrupt Enable Clear Register for ramecc15_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_4(&mut self) -> InterruptEnableClear4W<EccSecEnableClrReg0Spec> {
InterruptEnableClear4W::new(self, 15)
}
#[doc = "Bit 16 - 16:16\\]
Interrupt Enable Clear Register for ramecc16_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_3(&mut self) -> InterruptEnableClear3W<EccSecEnableClrReg0Spec> {
InterruptEnableClear3W::new(self, 16)
}
#[doc = "Bit 17 - 17:17\\]
Interrupt Enable Clear Register for ramecc17_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_2(&mut self) -> InterruptEnableClear2W<EccSecEnableClrReg0Spec> {
InterruptEnableClear2W::new(self, 17)
}
#[doc = "Bit 18 - 18:18\\]
Interrupt Enable Clear Register for ramecc18_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear_1(&mut self) -> InterruptEnableClear1W<EccSecEnableClrReg0Spec> {
InterruptEnableClear1W::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
Interrupt Enable Clear Register for ramecc19_pend"]
#[inline(always)]
#[must_use]
pub fn interrupt_enable_clear(&mut self) -> InterruptEnableClearW<EccSecEnableClrReg0Spec> {
InterruptEnableClearW::new(self, 19)
}
}
#[doc = "Interrupt Enable Clear Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc_sec_enable_clr_reg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecc_sec_enable_clr_reg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccSecEnableClrReg0Spec;
impl crate::RegisterSpec for EccSecEnableClrReg0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecc_sec_enable_clr_reg0::R`](R) reader structure"]
impl crate::Readable for EccSecEnableClrReg0Spec {}
#[doc = "`write(|w| ..)` method takes [`ecc_sec_enable_clr_reg0::W`](W) writer structure"]
impl crate::Writable for EccSecEnableClrReg0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ECC_sec_enable_clr_reg0 to value 0"]
impl crate::Resettable for EccSecEnableClrReg0Spec {
const RESET_VALUE: u32 = 0;
}