pub mod SQADD_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000000110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQADD_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQADD_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b000011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQSUB_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000010110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQSUB_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQSUB_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMGT_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000000011010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMGT_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMGT_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMGE_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000000011110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMGE_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMGE_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000000100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn SSHL_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000100110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQSHL_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SRSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000000101010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SRSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn SRSHL_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQRSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000101110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQRSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQRSHL_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod ADD_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001000010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "ADD_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn ADD_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMTST_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001000110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMTST_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMTST_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQDMULH_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000001011010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQDMULH_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQDMULH_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b101101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMULX_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000001101110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMULX_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FMULX_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMEQ_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000001110010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMEQ_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMEQ_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FRECPS_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FRECPS_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FRECPS_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FRSQRTS_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FRSQRTS_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FRSQRTS_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UQADD_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000000110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQADD_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn UQADD_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b000011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UQSUB_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000010110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQSUB_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn UQSUB_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMHI_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000000011010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMHI_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMHI_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMHS_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000000011110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMHS_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMHS_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b001111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod USHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000000100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn USHL_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UQSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000100110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn UQSHL_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod URSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000000101010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "URSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn URSHL_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UQRSHL_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000101110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQRSHL_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn UQRSHL_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b010111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SUB_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000001000010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SUB_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn SUB_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMEQ_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000001000110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMEQ_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMEQ_asisdsame_only(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110111u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQRDMULH_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000001011010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQRDMULH_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQRDMULH_asisdsame_only(
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b101101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMGE_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000001110010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMGE_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMGE_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FACGE_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FACGE_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FACGE_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FABD_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000001101010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FABD_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FABD_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMGT_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000001110010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMGT_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMGT_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FACGT_asisdsame_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FACGT_asisdsame_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FACGT_asisdsame_only(
sz: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b1u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}