pub mod SDOT_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110000000001001010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SDOT_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn SDOT_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTN_asimdsame2_H {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110000000001111010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTN_asimdsame2_H";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTN_asimdsame2_H(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110000u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FDOT_asimdsame2_DD {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110000000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FDOT_asimdsame2_DD";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FDOT_asimdsame2_DD(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110000u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTN_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110010000001111010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTN_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTN_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FDOT_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110010000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FDOT_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FDOT_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod USDOT_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110100000001001110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USDOT_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn USDOT_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FDOT_asimdsame2_FP16FP32 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110100000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FDOT_asimdsame2_FP16FP32";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FDOT_asimdsame2_FP16FP32(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b001110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQRDMLAH_asimdsame2_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110000000001000010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQRDMLAH_asimdsame2_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn SQRDMLAH_asimdsame2_only(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQRDMLSH_asimdsame2_only {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110000000001000110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQRDMLSH_asimdsame2_only";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn SQRDMLSH_asimdsame2_only(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UDOT_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110000000001001010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UDOT_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn UDOT_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b100101u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMLA_asimdsame2_C {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001110010000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110000000001100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMLA_asimdsame2_C";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_rot_OFFSET: u32 = 11u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_rot_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMLA_asimdsame2_C(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
rot: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110u32 << 13u32
| rot.into_inner() << 11u32
| 0b1u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCADD_asimdsame2_C {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111001000001110110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110000000001110010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCADD_asimdsame2_C";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_rot_OFFSET: u32 = 12u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_rot_WIDTH: u32 = 1u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCADD_asimdsame2_C(
Q: ::aarchmrs_types::BitValue<1>,
size: ::aarchmrs_types::BitValue<2>,
Rm: ::aarchmrs_types::BitValue<5>,
rot: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110u32 << 24u32
| size.into_inner() << 22u32
| 0b0u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111u32 << 13u32
| rot.into_inner() << 12u32
| 0b01u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod BFDOT_asimdsame2_D {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110010000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "BFDOT_asimdsame2_D";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn BFDOT_asimdsame2_D(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod BFMLAL_asimdsame2_F_ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b10111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00101110110000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "BFMLAL_asimdsame2_F_";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_OFFSET: u32 = 30u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Q_WIDTH: u32 = 1u32;
#[inline]
pub const fn BFMLAL_asimdsame2_F_(
Q: ::aarchmrs_types::BitValue<1>,
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0u32 << 31u32
| Q.into_inner() << 30u32
| 0b101110110u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALLBB_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110000000001100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALLBB_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALLBB_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b00001110000u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALLBT_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110010000001100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALLBT_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALLBT_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b00001110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALB_asimdsame2_J {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b00001110110000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALB_asimdsame2_J";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALB_asimdsame2_J(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b00001110110u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALLTB_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110000000001100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALLTB_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALLTB_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110000u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALLTT_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110010000001100010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALLTT_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALLTT_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b110001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SMMLA_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110100000001010010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SMMLA_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn SMMLA_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b101001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod USMMLA_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110100000001010110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USMMLA_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn USMMLA_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b101011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMMLA_asimd_FP16FP16 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110110000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMMLA_asimd_FP16FP16";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMMLA_asimd_FP16FP16(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110110u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMLALT_asimdsame2_J {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110110000001111110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMLALT_asimdsame2_J";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMLALT_asimdsame2_J(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110110u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111111u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMMLA_asimd_FP8FP16 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01101110000000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMMLA_asimd_FP8FP16";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMMLA_asimd_FP8FP16(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01101110000u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMMLA_asimd_FP16FP32 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01001110010000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMMLA_asimd_FP16FP32";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMMLA_asimd_FP16FP32(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01001110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod BFMMLA_asimdsame2_E {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01101110010000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "BFMMLA_asimdsame2_E";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn BFMMLA_asimdsame2_E(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01101110010u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FMMLA_asimd_FP8FP32 {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01101110100000001110110000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FMMLA_asimd_FP8FP32";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn FMMLA_asimd_FP8FP32(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01101110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b111011u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UMMLA_asimdsame2_G {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111000001111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01101110100000001010010000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UMMLA_asimdsame2_G";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_OFFSET: u32 = 16u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rm_WIDTH: u32 = 5u32;
#[inline]
pub const fn UMMLA_asimdsame2_G(
Rm: ::aarchmrs_types::BitValue<5>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01101110100u32 << 21u32
| Rm.into_inner() << 16u32
| 0b101001u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}