pub mod SUQADD_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SUQADD_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SUQADD_asisdmisc_R(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b100000001110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQABS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000000111100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQABS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQABS_asisdmisc_R(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b100000011110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMGT_asisdmisc_Z {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001000100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMGT_asisdmisc_Z";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMGT_asisdmisc_Z(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0101111011100000100010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMEQ_asisdmisc_Z {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001001100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMEQ_asisdmisc_Z";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMEQ_asisdmisc_Z(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0101111011100000100110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMLT_asisdmisc_Z {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMLT_asisdmisc_Z";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMLT_asisdmisc_Z(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0101111011100000101010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod ABS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110111000001011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "ABS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn ABS_asisdmisc_R(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0101111011100000101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQXTN_asisdmisc_N {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000010100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQXTN_asisdmisc_N";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQXTN_asisdmisc_N(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01011110u32 << 24u32
| size.into_inner() << 22u32
| 0b100001010010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTNS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000011010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTNS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTNS_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTMS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000011011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTMS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTMS_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTAS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000011100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTAS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTAS_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SCVTF_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110001000011101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SCVTF_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn SCVTF_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMGT_asisdmisc_FZ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000001100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMGT_asisdmisc_FZ";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMGT_asisdmisc_FZ(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100000110010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMEQ_asisdmisc_FZ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000001101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMEQ_asisdmisc_FZ";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMEQ_asisdmisc_FZ(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100000110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMLT_asisdmisc_FZ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000001110100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMLT_asisdmisc_FZ";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMLT_asisdmisc_FZ(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100000111010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTPS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000011010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTPS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTPS_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTZS_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000011011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTZS_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTZS_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FRECPE_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000011101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FRECPE_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FRECPE_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FRECPX_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01011110101000011111100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FRECPX_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FRECPX_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b010111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001111110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod USQADD_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "USQADD_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn USQADD_asisdmisc_R(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b100000001110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQNEG_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000000111100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQNEG_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQNEG_asisdmisc_R(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b100000011110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMGE_asisdmisc_Z {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000001000100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMGE_asisdmisc_Z";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMGE_asisdmisc_Z(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0111111011100000100010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod CMLE_asisdmisc_Z {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000001001100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "CMLE_asisdmisc_Z";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn CMLE_asisdmisc_Z(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0111111011100000100110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod NEG_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110111000001011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "NEG_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn NEG_asisdmisc_R(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0111111011100000101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod SQXTUN_asisdmisc_N {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000010010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "SQXTUN_asisdmisc_N";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn SQXTUN_asisdmisc_N(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b100001001010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UQXTN_asisdmisc_N {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111001111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000010100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UQXTN_asisdmisc_N";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_size_WIDTH: u32 = 2u32;
#[inline]
pub const fn UQXTN_asisdmisc_N(
size: ::aarchmrs_types::BitValue<2>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b01111110u32 << 24u32
| size.into_inner() << 22u32
| 0b100001010010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTXN_asisdmisc_N {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111111111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110011000010110100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTXN_asisdmisc_N";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[inline]
pub const fn FCVTXN_asisdmisc_N(
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b0111111001100001011010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTNU_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000011010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTNU_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTNU_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTMU_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000011011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTMU_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTMU_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTAU_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000011100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTAU_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTAU_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod UCVTF_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110001000011101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "UCVTF_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn UCVTF_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111100u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMGE_asisdmisc_FZ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000001100100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMGE_asisdmisc_FZ";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMGE_asisdmisc_FZ(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100000110010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCMLE_asisdmisc_FZ {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000001101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCMLE_asisdmisc_FZ";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCMLE_asisdmisc_FZ(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100000110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTPU_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000011010100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTPU_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTPU_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101010u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FCVTZU_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000011011100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FCVTZU_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FCVTZU_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001101110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}
pub mod FRSQRTE_asisdmisc_R {
#[cfg(feature = "meta")]
pub const OPCODE_MASK: u32 = 0b11111111101111111111110000000000u32;
#[cfg(feature = "meta")]
pub const OPCODE: u32 = 0b01111110101000011101100000000000u32;
#[cfg(feature = "meta")]
pub const SHOULD_BE_MASK: u32 = 0b00000000000000000000000000000000u32;
#[cfg(feature = "meta")]
pub const NAME: &str = "FRSQRTE_asisdmisc_R";
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_OFFSET: u32 = 0u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rd_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_OFFSET: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_Rn_WIDTH: u32 = 5u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_OFFSET: u32 = 22u32;
#[cfg(feature = "meta_field")]
#[allow(nonstandard_style)]
pub const FIELD_sz_WIDTH: u32 = 1u32;
#[inline]
pub const fn FRSQRTE_asisdmisc_R(
sz: ::aarchmrs_types::BitValue<1>,
Rn: ::aarchmrs_types::BitValue<5>,
Rd: ::aarchmrs_types::BitValue<5>,
) -> ::aarchmrs_types::InstructionCode {
::aarchmrs_types::InstructionCode::from_u32(
0b011111101u32 << 23u32
| sz.into_inner() << 22u32
| 0b100001110110u32 << 10u32
| Rn.into_inner() << 5u32
| Rd.into_inner() << 0u32,
)
}
}