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RegisterBlock

xr806_pac::uart2

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 18 fields
    pub lcr: Reg<LCR_SPEC>,
    pub mcr: Reg<MCR_SPEC>,
    pub lsr: Reg<LSR_SPEC>,
    pub msr: Reg<MSR_SPEC>,
    pub sch: Reg<SCH_SPEC>,
    pub usr: Reg<USR_SPEC>,
    pub tfl: Reg<TFL_SPEC>,
    pub rfl: Reg<RFL_SPEC>,
    pub halt: Reg<HALT_SPEC>,
    pub dbg_dll: Reg<DBG_DLL_SPEC>,
    pub dbg_dlh: Reg<DBG_DLH_SPEC>,
    pub rs485_ctl: Reg<RS485_CTL_SPEC>,
    pub rs485_addr_match: Reg<RS485_ADDR_MATCH_SPEC>,
    pub rs485_bus_idle_chk: Reg<RS485_BUS_IDLE_CHK_SPEC>,
    pub tx_dly: Reg<TX_DLY_SPEC>,
    pub bdcr: Reg<BDCR_SPEC>,
    pub bdclr: Reg<BDCLR_SPEC>,
    pub bdchr: Reg<BDCHR_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§lcr: Reg<LCR_SPEC>

0x0c - UART Line Control Register

§mcr: Reg<MCR_SPEC>

0x10 - UART Modem Control Register

§lsr: Reg<LSR_SPEC>

0x14 - UART Line Status Register

§msr: Reg<MSR_SPEC>

0x18 - UART Modem Status Register

§sch: Reg<SCH_SPEC>

0x1c - UART Scratch Register

§usr: Reg<USR_SPEC>

0x7c - UART Status Register

§tfl: Reg<TFL_SPEC>

0x80 - UART Transmit FIFO Level Register

§rfl: Reg<RFL_SPEC>

0x84 - UART Receive FIFO Level Register

§halt: Reg<HALT_SPEC>

0xa4 - UART Halt TX Register

§dbg_dll: Reg<DBG_DLL_SPEC>

0xb0 - UART Debug DLL Register

§dbg_dlh: Reg<DBG_DLH_SPEC>

0xb4 - UART Debug DLH Register

§rs485_ctl: Reg<RS485_CTL_SPEC>

0xc0 - UART RS485 Control and Status Register

§rs485_addr_match: Reg<RS485_ADDR_MATCH_SPEC>

0xc4 - UART RS485 Address Match Register

§rs485_bus_idle_chk: Reg<RS485_BUS_IDLE_CHK_SPEC>

0xc8 - UART RS485 Bus Idle Check Register

§tx_dly: Reg<TX_DLY_SPEC>

0xcc - UART TX Delay Register

§bdcr: Reg<BDCR_SPEC>

0xd4 - UART Baudrate Detection Control Register

§bdclr: Reg<BDCLR_SPEC>

0xd8 - UART Baudrate Detection Counter Low Register

§bdchr: Reg<BDCHR_SPEC>

0xdc - UART Baudrate Detection Counter High Register

Implementations§

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impl RegisterBlock

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pub fn dll(&self) -> &Reg<DLL_SPEC>

0x00 - UART Divisor Latch Low Register

Source

pub fn thr(&self) -> &Reg<THR_SPEC>

0x00 - UART Transmit Holding Register

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pub fn rbr(&self) -> &Reg<RBR_SPEC>

0x00 - UART Receive Buffer Register

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pub fn ier(&self) -> &Reg<IER_SPEC>

0x04 - UART Interrupt Enable Register

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pub fn dlh(&self) -> &Reg<DLH_SPEC>

0x04 - UART Divisor Latch High Register

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pub fn fcr(&self) -> &Reg<FCR_SPEC>

0x08 - UART FIFO Control Register

Source

pub fn iir(&self) -> &Reg<IIR_SPEC>

0x08 - UART Interrupt Identity Register

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