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xr806_pac/
uart2.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved_0_dll: [u8; 0x04],
5    _reserved_1_dlh: [u8; 0x04],
6    _reserved_2_fcr: [u8; 0x04],
7    #[doc = "0x0c - UART Line Control Register"]
8    pub lcr: crate::Reg<lcr::LCR_SPEC>,
9    #[doc = "0x10 - UART Modem Control Register"]
10    pub mcr: crate::Reg<mcr::MCR_SPEC>,
11    #[doc = "0x14 - UART Line Status Register"]
12    pub lsr: crate::Reg<lsr::LSR_SPEC>,
13    #[doc = "0x18 - UART Modem Status Register"]
14    pub msr: crate::Reg<msr::MSR_SPEC>,
15    #[doc = "0x1c - UART Scratch Register"]
16    pub sch: crate::Reg<sch::SCH_SPEC>,
17    _reserved8: [u8; 0x5c],
18    #[doc = "0x7c - UART Status Register"]
19    pub usr: crate::Reg<usr::USR_SPEC>,
20    #[doc = "0x80 - UART Transmit FIFO Level Register"]
21    pub tfl: crate::Reg<tfl::TFL_SPEC>,
22    #[doc = "0x84 - UART Receive FIFO Level Register"]
23    pub rfl: crate::Reg<rfl::RFL_SPEC>,
24    _reserved11: [u8; 0x1c],
25    #[doc = "0xa4 - UART Halt TX Register"]
26    pub halt: crate::Reg<halt::HALT_SPEC>,
27    _reserved12: [u8; 0x08],
28    #[doc = "0xb0 - UART Debug DLL Register"]
29    pub dbg_dll: crate::Reg<dbg_dll::DBG_DLL_SPEC>,
30    #[doc = "0xb4 - UART Debug DLH Register"]
31    pub dbg_dlh: crate::Reg<dbg_dlh::DBG_DLH_SPEC>,
32    _reserved14: [u8; 0x08],
33    #[doc = "0xc0 - UART RS485 Control and Status Register"]
34    pub rs485_ctl: crate::Reg<rs485_ctl::RS485_CTL_SPEC>,
35    #[doc = "0xc4 - UART RS485 Address Match Register"]
36    pub rs485_addr_match: crate::Reg<rs485_addr_match::RS485_ADDR_MATCH_SPEC>,
37    #[doc = "0xc8 - UART RS485 Bus Idle Check Register"]
38    pub rs485_bus_idle_chk: crate::Reg<rs485_bus_idle_chk::RS485_BUS_IDLE_CHK_SPEC>,
39    #[doc = "0xcc - UART TX Delay Register"]
40    pub tx_dly: crate::Reg<tx_dly::TX_DLY_SPEC>,
41    _reserved18: [u8; 0x04],
42    #[doc = "0xd4 - UART Baudrate Detection Control Register"]
43    pub bdcr: crate::Reg<bdcr::BDCR_SPEC>,
44    #[doc = "0xd8 - UART Baudrate Detection Counter Low Register"]
45    pub bdclr: crate::Reg<bdclr::BDCLR_SPEC>,
46    #[doc = "0xdc - UART Baudrate Detection Counter High Register"]
47    pub bdchr: crate::Reg<bdchr::BDCHR_SPEC>,
48}
49impl RegisterBlock {
50    #[doc = "0x00 - UART Divisor Latch Low Register"]
51    #[inline(always)]
52    pub fn dll(&self) -> &crate::Reg<dll::DLL_SPEC> {
53        unsafe {
54            &*(((self as *const Self) as *const u8).add(0usize) as *const crate::Reg<dll::DLL_SPEC>)
55        }
56    }
57    #[doc = "0x00 - UART Transmit Holding Register"]
58    #[inline(always)]
59    pub fn thr(&self) -> &crate::Reg<thr::THR_SPEC> {
60        unsafe {
61            &*(((self as *const Self) as *const u8).add(0usize) as *const crate::Reg<thr::THR_SPEC>)
62        }
63    }
64    #[doc = "0x00 - UART Receive Buffer Register"]
65    #[inline(always)]
66    pub fn rbr(&self) -> &crate::Reg<rbr::RBR_SPEC> {
67        unsafe {
68            &*(((self as *const Self) as *const u8).add(0usize) as *const crate::Reg<rbr::RBR_SPEC>)
69        }
70    }
71    #[doc = "0x04 - UART Interrupt Enable Register"]
72    #[inline(always)]
73    pub fn ier(&self) -> &crate::Reg<ier::IER_SPEC> {
74        unsafe {
75            &*(((self as *const Self) as *const u8).add(4usize) as *const crate::Reg<ier::IER_SPEC>)
76        }
77    }
78    #[doc = "0x04 - UART Divisor Latch High Register"]
79    #[inline(always)]
80    pub fn dlh(&self) -> &crate::Reg<dlh::DLH_SPEC> {
81        unsafe {
82            &*(((self as *const Self) as *const u8).add(4usize) as *const crate::Reg<dlh::DLH_SPEC>)
83        }
84    }
85    #[doc = "0x08 - UART FIFO Control Register"]
86    #[inline(always)]
87    pub fn fcr(&self) -> &crate::Reg<fcr::FCR_SPEC> {
88        unsafe {
89            &*(((self as *const Self) as *const u8).add(8usize) as *const crate::Reg<fcr::FCR_SPEC>)
90        }
91    }
92    #[doc = "0x08 - UART Interrupt Identity Register"]
93    #[inline(always)]
94    pub fn iir(&self) -> &crate::Reg<iir::IIR_SPEC> {
95        unsafe {
96            &*(((self as *const Self) as *const u8).add(8usize) as *const crate::Reg<iir::IIR_SPEC>)
97        }
98    }
99}
100#[doc = "RBR register accessor: an alias for `Reg<RBR_SPEC>`"]
101pub type RBR = crate::Reg<rbr::RBR_SPEC>;
102#[doc = "UART Receive Buffer Register"]
103pub mod rbr;
104#[doc = "THR register accessor: an alias for `Reg<THR_SPEC>`"]
105pub type THR = crate::Reg<thr::THR_SPEC>;
106#[doc = "UART Transmit Holding Register"]
107pub mod thr;
108#[doc = "DLL register accessor: an alias for `Reg<DLL_SPEC>`"]
109pub type DLL = crate::Reg<dll::DLL_SPEC>;
110#[doc = "UART Divisor Latch Low Register"]
111pub mod dll;
112#[doc = "DLH register accessor: an alias for `Reg<DLH_SPEC>`"]
113pub type DLH = crate::Reg<dlh::DLH_SPEC>;
114#[doc = "UART Divisor Latch High Register"]
115pub mod dlh;
116#[doc = "IER register accessor: an alias for `Reg<IER_SPEC>`"]
117pub type IER = crate::Reg<ier::IER_SPEC>;
118#[doc = "UART Interrupt Enable Register"]
119pub mod ier;
120#[doc = "IIR register accessor: an alias for `Reg<IIR_SPEC>`"]
121pub type IIR = crate::Reg<iir::IIR_SPEC>;
122#[doc = "UART Interrupt Identity Register"]
123pub mod iir;
124#[doc = "FCR register accessor: an alias for `Reg<FCR_SPEC>`"]
125pub type FCR = crate::Reg<fcr::FCR_SPEC>;
126#[doc = "UART FIFO Control Register"]
127pub mod fcr;
128#[doc = "LCR register accessor: an alias for `Reg<LCR_SPEC>`"]
129pub type LCR = crate::Reg<lcr::LCR_SPEC>;
130#[doc = "UART Line Control Register"]
131pub mod lcr;
132#[doc = "MCR register accessor: an alias for `Reg<MCR_SPEC>`"]
133pub type MCR = crate::Reg<mcr::MCR_SPEC>;
134#[doc = "UART Modem Control Register"]
135pub mod mcr;
136#[doc = "LSR register accessor: an alias for `Reg<LSR_SPEC>`"]
137pub type LSR = crate::Reg<lsr::LSR_SPEC>;
138#[doc = "UART Line Status Register"]
139pub mod lsr;
140#[doc = "MSR register accessor: an alias for `Reg<MSR_SPEC>`"]
141pub type MSR = crate::Reg<msr::MSR_SPEC>;
142#[doc = "UART Modem Status Register"]
143pub mod msr;
144#[doc = "SCH register accessor: an alias for `Reg<SCH_SPEC>`"]
145pub type SCH = crate::Reg<sch::SCH_SPEC>;
146#[doc = "UART Scratch Register"]
147pub mod sch;
148#[doc = "USR register accessor: an alias for `Reg<USR_SPEC>`"]
149pub type USR = crate::Reg<usr::USR_SPEC>;
150#[doc = "UART Status Register"]
151pub mod usr;
152#[doc = "TFL register accessor: an alias for `Reg<TFL_SPEC>`"]
153pub type TFL = crate::Reg<tfl::TFL_SPEC>;
154#[doc = "UART Transmit FIFO Level Register"]
155pub mod tfl;
156#[doc = "RFL register accessor: an alias for `Reg<RFL_SPEC>`"]
157pub type RFL = crate::Reg<rfl::RFL_SPEC>;
158#[doc = "UART Receive FIFO Level Register"]
159pub mod rfl;
160#[doc = "HALT register accessor: an alias for `Reg<HALT_SPEC>`"]
161pub type HALT = crate::Reg<halt::HALT_SPEC>;
162#[doc = "UART Halt TX Register"]
163pub mod halt;
164#[doc = "DBG_DLL register accessor: an alias for `Reg<DBG_DLL_SPEC>`"]
165pub type DBG_DLL = crate::Reg<dbg_dll::DBG_DLL_SPEC>;
166#[doc = "UART Debug DLL Register"]
167pub mod dbg_dll;
168#[doc = "DBG_DLH register accessor: an alias for `Reg<DBG_DLH_SPEC>`"]
169pub type DBG_DLH = crate::Reg<dbg_dlh::DBG_DLH_SPEC>;
170#[doc = "UART Debug DLH Register"]
171pub mod dbg_dlh;
172#[doc = "RS485_CTL register accessor: an alias for `Reg<RS485_CTL_SPEC>`"]
173pub type RS485_CTL = crate::Reg<rs485_ctl::RS485_CTL_SPEC>;
174#[doc = "UART RS485 Control and Status Register"]
175pub mod rs485_ctl;
176#[doc = "RS485_ADDR_MATCH register accessor: an alias for `Reg<RS485_ADDR_MATCH_SPEC>`"]
177pub type RS485_ADDR_MATCH = crate::Reg<rs485_addr_match::RS485_ADDR_MATCH_SPEC>;
178#[doc = "UART RS485 Address Match Register"]
179pub mod rs485_addr_match;
180#[doc = "RS485_BUS_IDLE_CHK register accessor: an alias for `Reg<RS485_BUS_IDLE_CHK_SPEC>`"]
181pub type RS485_BUS_IDLE_CHK = crate::Reg<rs485_bus_idle_chk::RS485_BUS_IDLE_CHK_SPEC>;
182#[doc = "UART RS485 Bus Idle Check Register"]
183pub mod rs485_bus_idle_chk;
184#[doc = "TX_DLY register accessor: an alias for `Reg<TX_DLY_SPEC>`"]
185pub type TX_DLY = crate::Reg<tx_dly::TX_DLY_SPEC>;
186#[doc = "UART TX Delay Register"]
187pub mod tx_dly;
188#[doc = "BDCR register accessor: an alias for `Reg<BDCR_SPEC>`"]
189pub type BDCR = crate::Reg<bdcr::BDCR_SPEC>;
190#[doc = "UART Baudrate Detection Control Register"]
191pub mod bdcr;
192#[doc = "BDCLR register accessor: an alias for `Reg<BDCLR_SPEC>`"]
193pub type BDCLR = crate::Reg<bdclr::BDCLR_SPEC>;
194#[doc = "UART Baudrate Detection Counter Low Register"]
195pub mod bdclr;
196#[doc = "BDCHR register accessor: an alias for `Reg<BDCHR_SPEC>`"]
197pub type BDCHR = crate::Reg<bdchr::BDCHR_SPEC>;
198#[doc = "UART Baudrate Detection Counter High Register"]
199pub mod bdchr;