Struct xmc4800::Peripherals
source · pub struct Peripherals {Show 158 fields
pub PPB: PPB,
pub DLR: DLR,
pub ERU0: ERU0,
pub ERU1: ERU1,
pub GPDMA0: GPDMA0,
pub GPDMA0_CH0: GPDMA0_CH0,
pub GPDMA0_CH1: GPDMA0_CH1,
pub GPDMA0_CH2: GPDMA0_CH2,
pub GPDMA0_CH3: GPDMA0_CH3,
pub GPDMA0_CH4: GPDMA0_CH4,
pub GPDMA0_CH5: GPDMA0_CH5,
pub GPDMA0_CH6: GPDMA0_CH6,
pub GPDMA0_CH7: GPDMA0_CH7,
pub GPDMA1: GPDMA1,
pub GPDMA1_CH0: GPDMA1_CH0,
pub GPDMA1_CH1: GPDMA1_CH1,
pub GPDMA1_CH2: GPDMA1_CH2,
pub GPDMA1_CH3: GPDMA1_CH3,
pub FCE: FCE,
pub FCE_KE0: FCE_KE0,
pub FCE_KE1: FCE_KE1,
pub FCE_KE2: FCE_KE2,
pub FCE_KE3: FCE_KE3,
pub PBA0: PBA0,
pub PBA1: PBA1,
pub FLASH0: FLASH0,
pub PREF: PREF,
pub PMU0: PMU0,
pub WDT: WDT,
pub RTC: RTC,
pub SCU_CLK: SCU_CLK,
pub SCU_OSC: SCU_OSC,
pub SCU_PLL: SCU_PLL,
pub SCU_GENERAL: SCU_GENERAL,
pub SCU_INTERRUPT: SCU_INTERRUPT,
pub SCU_PARITY: SCU_PARITY,
pub SCU_TRAP: SCU_TRAP,
pub SCU_HIBERNATE: SCU_HIBERNATE,
pub SCU_POWER: SCU_POWER,
pub SCU_RESET: SCU_RESET,
pub LEDTS0: LEDTS0,
pub SDMMC_CON: SDMMC_CON,
pub SDMMC: SDMMC,
pub EBU: EBU,
pub ETH0_CON: ETH0_CON,
pub ETH0: ETH0,
pub ECAT0_CON: ECAT0_CON,
pub ECAT0: ECAT0,
pub ECAT0_FMMU0: ECAT0_FMMU0,
pub ECAT0_FMMU1: ECAT0_FMMU1,
pub ECAT0_FMMU2: ECAT0_FMMU2,
pub ECAT0_FMMU3: ECAT0_FMMU3,
pub ECAT0_FMMU4: ECAT0_FMMU4,
pub ECAT0_FMMU5: ECAT0_FMMU5,
pub ECAT0_FMMU6: ECAT0_FMMU6,
pub ECAT0_FMMU7: ECAT0_FMMU7,
pub ECAT0_SM0: ECAT0_SM0,
pub ECAT0_SM1: ECAT0_SM1,
pub ECAT0_SM2: ECAT0_SM2,
pub ECAT0_SM3: ECAT0_SM3,
pub ECAT0_SM4: ECAT0_SM4,
pub ECAT0_SM5: ECAT0_SM5,
pub ECAT0_SM6: ECAT0_SM6,
pub ECAT0_SM7: ECAT0_SM7,
pub USB0: USB0,
pub USB0_EP0: USB0_EP0,
pub USB0_EP1: USB0_EP1,
pub USB0_EP2: USB0_EP2,
pub USB0_EP3: USB0_EP3,
pub USB0_EP4: USB0_EP4,
pub USB0_EP5: USB0_EP5,
pub USB0_EP6: USB0_EP6,
pub USB0_CH0: USB0_CH0,
pub USB0_CH1: USB0_CH1,
pub USB0_CH2: USB0_CH2,
pub USB0_CH3: USB0_CH3,
pub USB0_CH4: USB0_CH4,
pub USB0_CH5: USB0_CH5,
pub USB0_CH6: USB0_CH6,
pub USB0_CH7: USB0_CH7,
pub USB0_CH8: USB0_CH8,
pub USB0_CH9: USB0_CH9,
pub USB0_CH10: USB0_CH10,
pub USB0_CH11: USB0_CH11,
pub USB0_CH12: USB0_CH12,
pub USB0_CH13: USB0_CH13,
pub USIC0: USIC0,
pub USIC1: USIC1,
pub USIC2: USIC2,
pub USIC0_CH0: USIC0_CH0,
pub USIC0_CH1: USIC0_CH1,
pub USIC1_CH0: USIC1_CH0,
pub USIC1_CH1: USIC1_CH1,
pub USIC2_CH0: USIC2_CH0,
pub USIC2_CH1: USIC2_CH1,
pub CAN: CAN,
pub CAN_NODE0: CAN_NODE0,
pub CAN_NODE1: CAN_NODE1,
pub CAN_NODE2: CAN_NODE2,
pub CAN_NODE3: CAN_NODE3,
pub CAN_NODE4: CAN_NODE4,
pub CAN_NODE5: CAN_NODE5,
pub CAN_MO: CAN_MO,
pub VADC: VADC,
pub VADC_G0: VADC_G0,
pub VADC_G1: VADC_G1,
pub VADC_G2: VADC_G2,
pub VADC_G3: VADC_G3,
pub DSD: DSD,
pub DSD_CH0: DSD_CH0,
pub DSD_CH1: DSD_CH1,
pub DSD_CH2: DSD_CH2,
pub DSD_CH3: DSD_CH3,
pub DAC: DAC,
pub CCU40: CCU40,
pub CCU41: CCU41,
pub CCU42: CCU42,
pub CCU43: CCU43,
pub CCU40_CC40: CCU40_CC40,
pub CCU40_CC41: CCU40_CC41,
pub CCU40_CC42: CCU40_CC42,
pub CCU40_CC43: CCU40_CC43,
pub CCU41_CC40: CCU41_CC40,
pub CCU41_CC41: CCU41_CC41,
pub CCU41_CC42: CCU41_CC42,
pub CCU41_CC43: CCU41_CC43,
pub CCU42_CC40: CCU42_CC40,
pub CCU42_CC41: CCU42_CC41,
pub CCU42_CC42: CCU42_CC42,
pub CCU42_CC43: CCU42_CC43,
pub CCU43_CC40: CCU43_CC40,
pub CCU43_CC41: CCU43_CC41,
pub CCU43_CC42: CCU43_CC42,
pub CCU43_CC43: CCU43_CC43,
pub CCU80: CCU80,
pub CCU81: CCU81,
pub CCU80_CC80: CCU80_CC80,
pub CCU80_CC81: CCU80_CC81,
pub CCU80_CC82: CCU80_CC82,
pub CCU80_CC83: CCU80_CC83,
pub CCU81_CC80: CCU81_CC80,
pub CCU81_CC81: CCU81_CC81,
pub CCU81_CC82: CCU81_CC82,
pub CCU81_CC83: CCU81_CC83,
pub POSIF0: POSIF0,
pub POSIF1: POSIF1,
pub PORT0: PORT0,
pub PORT1: PORT1,
pub PORT2: PORT2,
pub PORT3: PORT3,
pub PORT4: PORT4,
pub PORT5: PORT5,
pub PORT6: PORT6,
pub PORT7: PORT7,
pub PORT8: PORT8,
pub PORT9: PORT9,
pub PORT14: PORT14,
pub PORT15: PORT15,
}
Expand description
All the peripherals.
Fields§
§PPB: PPB
PPB
DLR: DLR
DLR
ERU0: ERU0
ERU0
ERU1: ERU1
ERU1
GPDMA0: GPDMA0
GPDMA0
GPDMA0_CH0: GPDMA0_CH0
GPDMA0_CH0
GPDMA0_CH1: GPDMA0_CH1
GPDMA0_CH1
GPDMA0_CH2: GPDMA0_CH2
GPDMA0_CH2
GPDMA0_CH3: GPDMA0_CH3
GPDMA0_CH3
GPDMA0_CH4: GPDMA0_CH4
GPDMA0_CH4
GPDMA0_CH5: GPDMA0_CH5
GPDMA0_CH5
GPDMA0_CH6: GPDMA0_CH6
GPDMA0_CH6
GPDMA0_CH7: GPDMA0_CH7
GPDMA0_CH7
GPDMA1: GPDMA1
GPDMA1
GPDMA1_CH0: GPDMA1_CH0
GPDMA1_CH0
GPDMA1_CH1: GPDMA1_CH1
GPDMA1_CH1
GPDMA1_CH2: GPDMA1_CH2
GPDMA1_CH2
GPDMA1_CH3: GPDMA1_CH3
GPDMA1_CH3
FCE: FCE
FCE
FCE_KE0: FCE_KE0
FCE_KE0
FCE_KE1: FCE_KE1
FCE_KE1
FCE_KE2: FCE_KE2
FCE_KE2
FCE_KE3: FCE_KE3
FCE_KE3
PBA0: PBA0
PBA0
PBA1: PBA1
PBA1
FLASH0: FLASH0
FLASH0
PREF: PREF
PREF
PMU0: PMU0
PMU0
WDT: WDT
WDT
RTC: RTC
RTC
SCU_CLK: SCU_CLK
SCU_CLK
SCU_OSC: SCU_OSC
SCU_OSC
SCU_PLL: SCU_PLL
SCU_PLL
SCU_GENERAL: SCU_GENERAL
SCU_GENERAL
SCU_INTERRUPT: SCU_INTERRUPT
SCU_INTERRUPT
SCU_PARITY: SCU_PARITY
SCU_PARITY
SCU_TRAP: SCU_TRAP
SCU_TRAP
SCU_HIBERNATE: SCU_HIBERNATE
SCU_HIBERNATE
SCU_POWER: SCU_POWER
SCU_POWER
SCU_RESET: SCU_RESET
SCU_RESET
LEDTS0: LEDTS0
LEDTS0
SDMMC_CON: SDMMC_CON
SDMMC_CON
SDMMC: SDMMC
SDMMC
EBU: EBU
EBU
ETH0_CON: ETH0_CON
ETH0_CON
ETH0: ETH0
ETH0
ECAT0_CON: ECAT0_CON
ECAT0_CON
ECAT0: ECAT0
ECAT0
ECAT0_FMMU0: ECAT0_FMMU0
ECAT0_FMMU0
ECAT0_FMMU1: ECAT0_FMMU1
ECAT0_FMMU1
ECAT0_FMMU2: ECAT0_FMMU2
ECAT0_FMMU2
ECAT0_FMMU3: ECAT0_FMMU3
ECAT0_FMMU3
ECAT0_FMMU4: ECAT0_FMMU4
ECAT0_FMMU4
ECAT0_FMMU5: ECAT0_FMMU5
ECAT0_FMMU5
ECAT0_FMMU6: ECAT0_FMMU6
ECAT0_FMMU6
ECAT0_FMMU7: ECAT0_FMMU7
ECAT0_FMMU7
ECAT0_SM0: ECAT0_SM0
ECAT0_SM0
ECAT0_SM1: ECAT0_SM1
ECAT0_SM1
ECAT0_SM2: ECAT0_SM2
ECAT0_SM2
ECAT0_SM3: ECAT0_SM3
ECAT0_SM3
ECAT0_SM4: ECAT0_SM4
ECAT0_SM4
ECAT0_SM5: ECAT0_SM5
ECAT0_SM5
ECAT0_SM6: ECAT0_SM6
ECAT0_SM6
ECAT0_SM7: ECAT0_SM7
ECAT0_SM7
USB0: USB0
USB0
USB0_EP0: USB0_EP0
USB0_EP0
USB0_EP1: USB0_EP1
USB0_EP1
USB0_EP2: USB0_EP2
USB0_EP2
USB0_EP3: USB0_EP3
USB0_EP3
USB0_EP4: USB0_EP4
USB0_EP4
USB0_EP5: USB0_EP5
USB0_EP5
USB0_EP6: USB0_EP6
USB0_EP6
USB0_CH0: USB0_CH0
USB0_CH0
USB0_CH1: USB0_CH1
USB0_CH1
USB0_CH2: USB0_CH2
USB0_CH2
USB0_CH3: USB0_CH3
USB0_CH3
USB0_CH4: USB0_CH4
USB0_CH4
USB0_CH5: USB0_CH5
USB0_CH5
USB0_CH6: USB0_CH6
USB0_CH6
USB0_CH7: USB0_CH7
USB0_CH7
USB0_CH8: USB0_CH8
USB0_CH8
USB0_CH9: USB0_CH9
USB0_CH9
USB0_CH10: USB0_CH10
USB0_CH10
USB0_CH11: USB0_CH11
USB0_CH11
USB0_CH12: USB0_CH12
USB0_CH12
USB0_CH13: USB0_CH13
USB0_CH13
USIC0: USIC0
USIC0
USIC1: USIC1
USIC1
USIC2: USIC2
USIC2
USIC0_CH0: USIC0_CH0
USIC0_CH0
USIC0_CH1: USIC0_CH1
USIC0_CH1
USIC1_CH0: USIC1_CH0
USIC1_CH0
USIC1_CH1: USIC1_CH1
USIC1_CH1
USIC2_CH0: USIC2_CH0
USIC2_CH0
USIC2_CH1: USIC2_CH1
USIC2_CH1
CAN: CAN
CAN
CAN_NODE0: CAN_NODE0
CAN_NODE0
CAN_NODE1: CAN_NODE1
CAN_NODE1
CAN_NODE2: CAN_NODE2
CAN_NODE2
CAN_NODE3: CAN_NODE3
CAN_NODE3
CAN_NODE4: CAN_NODE4
CAN_NODE4
CAN_NODE5: CAN_NODE5
CAN_NODE5
CAN_MO: CAN_MO
CAN_MO
VADC: VADC
VADC
VADC_G0: VADC_G0
VADC_G0
VADC_G1: VADC_G1
VADC_G1
VADC_G2: VADC_G2
VADC_G2
VADC_G3: VADC_G3
VADC_G3
DSD: DSD
DSD
DSD_CH0: DSD_CH0
DSD_CH0
DSD_CH1: DSD_CH1
DSD_CH1
DSD_CH2: DSD_CH2
DSD_CH2
DSD_CH3: DSD_CH3
DSD_CH3
DAC: DAC
DAC
CCU40: CCU40
CCU40
CCU41: CCU41
CCU41
CCU42: CCU42
CCU42
CCU43: CCU43
CCU43
CCU40_CC40: CCU40_CC40
CCU40_CC40
CCU40_CC41: CCU40_CC41
CCU40_CC41
CCU40_CC42: CCU40_CC42
CCU40_CC42
CCU40_CC43: CCU40_CC43
CCU40_CC43
CCU41_CC40: CCU41_CC40
CCU41_CC40
CCU41_CC41: CCU41_CC41
CCU41_CC41
CCU41_CC42: CCU41_CC42
CCU41_CC42
CCU41_CC43: CCU41_CC43
CCU41_CC43
CCU42_CC40: CCU42_CC40
CCU42_CC40
CCU42_CC41: CCU42_CC41
CCU42_CC41
CCU42_CC42: CCU42_CC42
CCU42_CC42
CCU42_CC43: CCU42_CC43
CCU42_CC43
CCU43_CC40: CCU43_CC40
CCU43_CC40
CCU43_CC41: CCU43_CC41
CCU43_CC41
CCU43_CC42: CCU43_CC42
CCU43_CC42
CCU43_CC43: CCU43_CC43
CCU43_CC43
CCU80: CCU80
CCU80
CCU81: CCU81
CCU81
CCU80_CC80: CCU80_CC80
CCU80_CC80
CCU80_CC81: CCU80_CC81
CCU80_CC81
CCU80_CC82: CCU80_CC82
CCU80_CC82
CCU80_CC83: CCU80_CC83
CCU80_CC83
CCU81_CC80: CCU81_CC80
CCU81_CC80
CCU81_CC81: CCU81_CC81
CCU81_CC81
CCU81_CC82: CCU81_CC82
CCU81_CC82
CCU81_CC83: CCU81_CC83
CCU81_CC83
POSIF0: POSIF0
POSIF0
POSIF1: POSIF1
POSIF1
PORT0: PORT0
PORT0
PORT1: PORT1
PORT1
PORT2: PORT2
PORT2
PORT3: PORT3
PORT3
PORT4: PORT4
PORT4
PORT5: PORT5
PORT5
PORT6: PORT6
PORT6
PORT7: PORT7
PORT7
PORT8: PORT8
PORT8
PORT9: PORT9
PORT9
PORT14: PORT14
PORT14
PORT15: PORT15
PORT15