pub enum Instruction {
Show 319 variants
HALT([Operand; 0]),
NOP([Operand; 0]),
REI([Operand; 0]),
BPT([Operand; 0]),
RET([Operand; 0]),
RSB([Operand; 0]),
LDPCTX([Operand; 0]),
SVPCTX([Operand; 0]),
CVTPS([Operand; 4]),
CVTSP([Operand; 4]),
INDEX([Operand; 6]),
CRC([Operand; 4]),
PROBER([Operand; 3]),
PROBEW([Operand; 3]),
INSQUE([Operand; 2]),
REMQUE([Operand; 2]),
BSBB([Operand; 1]),
BRB([Operand; 1]),
BNEQ([Operand; 1]),
BEQL([Operand; 1]),
BGTR([Operand; 1]),
BLEQ([Operand; 1]),
JSB([Operand; 1]),
JMP([Operand; 1]),
BGEQ([Operand; 1]),
BLSS([Operand; 1]),
BGTRU([Operand; 1]),
BLEQU([Operand; 1]),
BVC([Operand; 1]),
BVS([Operand; 1]),
BGEQU([Operand; 1]),
BLSSU([Operand; 1]),
ADDP4([Operand; 4]),
ADDP6([Operand; 6]),
SUBP4([Operand; 4]),
SUBP6([Operand; 6]),
CVTPT([Operand; 5]),
MULP([Operand; 6]),
CVTTP([Operand; 5]),
DIVP([Operand; 6]),
MOVC3([Operand; 3]),
CMPC3([Operand; 3]),
SCANC([Operand; 4]),
SPANC([Operand; 4]),
MOVC5([Operand; 5]),
CMPC5([Operand; 5]),
MOVTC([Operand; 6]),
MOVTUC([Operand; 6]),
BSBW([Operand; 1]),
BRW([Operand; 1]),
CVTWL([Operand; 2]),
CVTWB([Operand; 2]),
MOVP([Operand; 3]),
CMPP3([Operand; 3]),
CVTPL([Operand; 3]),
CMPP4([Operand; 4]),
EDITPC([Operand; 4]),
MATCHC([Operand; 4]),
LOCC([Operand; 3]),
SKPC([Operand; 3]),
MOVZWL([Operand; 2]),
ACBW([Operand; 4]),
MOVAW([Operand; 2]),
PUSHAW([Operand; 1]),
ADDF2([Operand; 2]),
ADDF3([Operand; 3]),
SUBF2([Operand; 2]),
SUBF3([Operand; 3]),
MULF2([Operand; 2]),
MULF3([Operand; 3]),
DIVF2([Operand; 2]),
DIVF3([Operand; 3]),
CVTFB([Operand; 2]),
CVTFW([Operand; 2]),
CVTFL([Operand; 2]),
CVTRFL([Operand; 2]),
CVTBF([Operand; 2]),
CVTWF([Operand; 2]),
CVTLF([Operand; 2]),
ACBF([Operand; 4]),
MOVF([Operand; 2]),
CMPF([Operand; 2]),
MNEGF([Operand; 2]),
TSTF([Operand; 1]),
EMODF([Operand; 5]),
POLYF([Operand; 3]),
CVTFD([Operand; 2]),
ADAWI([Operand; 2]),
INSQHI([Operand; 2]),
INSQTI([Operand; 2]),
REMQHI([Operand; 2]),
REMQTI([Operand; 2]),
ADDD2([Operand; 2]),
ADDD3([Operand; 3]),
SUBD2([Operand; 2]),
SUBD3([Operand; 3]),
MULD2([Operand; 2]),
MULD3([Operand; 3]),
DIVD2([Operand; 2]),
DIVD3([Operand; 3]),
CVTDB([Operand; 2]),
CVTDW([Operand; 2]),
CVTDL([Operand; 2]),
CVTRDL([Operand; 2]),
CVTBD([Operand; 2]),
CVTWD([Operand; 2]),
CVTLD([Operand; 2]),
ACBD([Operand; 4]),
MOVD([Operand; 2]),
CMPD([Operand; 2]),
MNEGD([Operand; 2]),
TSTD([Operand; 1]),
EMODD([Operand; 5]),
POLYD([Operand; 3]),
CVTDF([Operand; 2]),
ASHL([Operand; 3]),
ASHQ([Operand; 3]),
EMUL([Operand; 4]),
EDIV([Operand; 4]),
CLRQ([Operand; 1]),
MOVQ([Operand; 2]),
MOVAQ([Operand; 2]),
PUSHAQ([Operand; 1]),
ADDB2([Operand; 2]),
ADDB3([Operand; 3]),
SUBB2([Operand; 2]),
SUBB3([Operand; 3]),
MULB2([Operand; 2]),
MULB3([Operand; 3]),
DIVB2([Operand; 2]),
DIVB3([Operand; 3]),
BISB2([Operand; 2]),
BISB3([Operand; 3]),
BICB2([Operand; 2]),
BICB3([Operand; 3]),
XORB2([Operand; 2]),
XORB3([Operand; 3]),
MNEGB([Operand; 2]),
CASEB([Operand; 3]),
MOVB([Operand; 2]),
CMPB([Operand; 2]),
MCOMB([Operand; 2]),
BITB([Operand; 2]),
CLRB([Operand; 1]),
TSTB([Operand; 1]),
INCB([Operand; 1]),
DECB([Operand; 1]),
CVTBL([Operand; 2]),
CVTBW([Operand; 2]),
MOVZBL([Operand; 2]),
MOVZBW([Operand; 2]),
ROTL([Operand; 3]),
ACBB([Operand; 4]),
MOVAB([Operand; 2]),
PUSHAB([Operand; 1]),
ADDW2([Operand; 2]),
ADDW3([Operand; 3]),
SUBW2([Operand; 2]),
SUBW3([Operand; 3]),
MULW2([Operand; 2]),
MULW3([Operand; 3]),
DIVW2([Operand; 2]),
DIVW3([Operand; 3]),
BISW2([Operand; 2]),
BISW3([Operand; 3]),
BICW2([Operand; 2]),
BICW3([Operand; 3]),
XORW2([Operand; 2]),
XORW3([Operand; 3]),
MNEGW([Operand; 2]),
CASEW([Operand; 3]),
MOVW([Operand; 2]),
CMPW([Operand; 2]),
MCOMW([Operand; 2]),
BITW([Operand; 2]),
CLRW([Operand; 1]),
TSTW([Operand; 1]),
INCW([Operand; 1]),
DECW([Operand; 1]),
BISPSW([Operand; 1]),
BICPSW([Operand; 1]),
POPR([Operand; 1]),
PUSHR([Operand; 1]),
CHMK([Operand; 1]),
CHME([Operand; 1]),
CHMS([Operand; 1]),
CHMU([Operand; 1]),
ADDL2([Operand; 2]),
ADDL3([Operand; 3]),
SUBL2([Operand; 2]),
SUBL3([Operand; 3]),
MULL2([Operand; 2]),
MULL3([Operand; 3]),
DIVL2([Operand; 2]),
DIVL3([Operand; 3]),
BISL2([Operand; 2]),
BISL3([Operand; 3]),
BICL2([Operand; 2]),
BICL3([Operand; 3]),
XORL2([Operand; 2]),
XORL3([Operand; 3]),
MNEGL([Operand; 2]),
CASEL([Operand; 3]),
MOVL([Operand; 2]),
CMPL([Operand; 2]),
MCOML([Operand; 2]),
BITL([Operand; 2]),
CLRL([Operand; 1]),
TSTL([Operand; 1]),
INCL([Operand; 1]),
DECL([Operand; 1]),
ADWC([Operand; 2]),
SBWC([Operand; 2]),
MTPR([Operand; 2]),
MFPR([Operand; 2]),
MOVPSL([Operand; 1]),
PUSHL([Operand; 1]),
MOVAL([Operand; 2]),
PUSHAL([Operand; 1]),
BBS([Operand; 3]),
BBC([Operand; 3]),
BBSS([Operand; 3]),
BBCS([Operand; 3]),
BBSC([Operand; 3]),
BBCC([Operand; 3]),
BBSSI([Operand; 3]),
BBCCI([Operand; 3]),
BLBS([Operand; 2]),
BLBC([Operand; 2]),
FFS([Operand; 4]),
FFC([Operand; 4]),
CMPV([Operand; 4]),
CMPZV([Operand; 4]),
EXTV([Operand; 4]),
EXTZV([Operand; 4]),
INSV([Operand; 4]),
ACBL([Operand; 4]),
AOBLSS([Operand; 3]),
AOBLEQ([Operand; 3]),
SOBGEQ([Operand; 2]),
SOBGTR([Operand; 2]),
CVTLB([Operand; 2]),
CVTLW([Operand; 2]),
ASHP([Operand; 6]),
CVTLP([Operand; 3]),
CALLG([Operand; 2]),
CALLC([Operand; 2]),
XFC([Operand; 0]),
CVTDH([Operand; 2]),
CVTGF([Operand; 2]),
ADDG2([Operand; 2]),
ADDG3([Operand; 3]),
SUBG2([Operand; 2]),
SUBG3([Operand; 3]),
MULG2([Operand; 2]),
MULG3([Operand; 3]),
DIVG2([Operand; 2]),
DIVG3([Operand; 3]),
CVTGB([Operand; 2]),
CVTGW([Operand; 2]),
CVTGL([Operand; 2]),
CVTRGL([Operand; 2]),
CVTBG([Operand; 2]),
CVTWG([Operand; 2]),
CVTLG([Operand; 2]),
ACBG([Operand; 4]),
MOVG([Operand; 2]),
CMPG([Operand; 2]),
MNEGG([Operand; 2]),
TSTG([Operand; 1]),
EMODG([Operand; 5]),
POLYG([Operand; 3]),
CVTGH([Operand; 2]),
ADDH2([Operand; 2]),
ADDH3([Operand; 3]),
SUBH2([Operand; 2]),
SUBH3([Operand; 3]),
MULH2([Operand; 2]),
MULH3([Operand; 3]),
DIVH2([Operand; 2]),
DIVH3([Operand; 3]),
CVTHB([Operand; 2]),
CVTHW([Operand; 2]),
CVTHL([Operand; 2]),
CVTRHL([Operand; 2]),
CVTBH([Operand; 2]),
CVTWH([Operand; 2]),
CVTLH([Operand; 2]),
ACBH([Operand; 4]),
MOVH([Operand; 2]),
CMPH([Operand; 2]),
MNEGH([Operand; 2]),
TSTH([Operand; 1]),
EMODH([Operand; 5]),
POLYH([Operand; 3]),
CVTHG([Operand; 2]),
CLRO([Operand; 1]),
MOVO([Operand; 2]),
MOVAO([Operand; 2]),
PUSHAO([Operand; 1]),
CVTFH([Operand; 2]),
CVTFG([Operand; 2]),
CVTHF([Operand; 2]),
CVTHD([Operand; 2]),
BUGL([Operand; 1]),
BUGW([Operand; 1]),
BNEQU([Operand; 1]),
BEQLU([Operand; 1]),
BCC([Operand; 1]),
BCS([Operand; 1]),
CLRD([Operand; 1]),
CLRG([Operand; 1]),
MOVAD([Operand; 2]),
MOVAG([Operand; 2]),
PUSHAD([Operand; 1]),
PUSHAG([Operand; 1]),
CLRH([Operand; 1]),
MOVAH([Operand; 2]),
PUSHAH([Operand; 1]),
}Expand description
§VAX Instruction
The VAX architecture has a variable-length instruction format. An instruction specifies an operation and 0 to 6 operands. An operand specifier determines how an operand is accessed. An operand specifier consists of an addressing mode specifier and, if needed, a specifier extension, immediate data, or an address.
§Examples
use vax_disassembler::{
Instruction,
Operand,
ReadMacro32,
operand::Register,
};
use std::io::Cursor;
let movc5_buf = [0x2C, 0x50, 0x61, 0x20, 0x52, 0x63];
let instruction = Cursor::new(movc5_buf).disassemble().unwrap();
assert_eq!(instruction, Instruction::MOVC5([
Operand::Register(Register::R0),
Operand::RegisterDeferred(Register::R1),
Operand::Literal(0x20),
Operand::Register(Register::R2),
Operand::RegisterDeferred(Register::R3),
]));
assert_eq!(&format!("{}", instruction), "MOVC5 R0, (R1), S^#32, R2, (R3)");Variants§
HALT([Operand; 0])
Halt
Format: HALT
NOP([Operand; 0])
No Operation
Format: NOP
REI([Operand; 0])
Return from Exception or Interrupt
Format: REI
BPT([Operand; 0])
Breakpoint
Format: BPT
RET([Operand; 0])
Return from Procedure
Format: RET
RSB([Operand; 0])
Return From Subroutine
Format: RSB
LDPCTX([Operand; 0])
Load Process Context
Format: LDPCTX
SVPCTX([Operand; 0])
Save Process Context
Format: SVPCTX
CVTPS([Operand; 4])
Convert Packed to Leading Separate Numeric
Format: CVTPS srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
CVTSP([Operand; 4])
Convert Leading Separate Numeric to Packed
Format: CVTSP srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
INDEX([Operand; 6])
Compute Index
Format: INDEX subscript.rl, low.rl, high.rl, size.rl, indexin.rl, indexout.wl
CRC([Operand; 4])
Calculate Cyclic Redundancy Check
Format: CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab
PROBER([Operand; 3])
Probe Read Accessibility
Format: PROBER mode.rb, len.rw, base.ab
PROBEW([Operand; 3])
Probe Write Accessibility
Format: PROBEW mode.rb, len.rw, base.ab
INSQUE([Operand; 2])
Insert Entry in Queue
Format: INSQUE entry.ab, pred.ab
REMQUE([Operand; 2])
Remove Entry from Queue
Format: REMQUE entry.ab, addr.wl
BSBB([Operand; 1])
Branch to Subroutine With Byte Displacement
Format: BSBB displ.bb
BRB([Operand; 1])
Branch With Byte Displacement
Format: BRB displ.bb
BNEQ([Operand; 1])
Branch on Not Equal (signed) [Z EQL 0]
Format: BNEQ displ.bb
BEQL([Operand; 1])
Branch on Equal (signed) [Z EQL 1]
Format: BEQL displ.bb
BGTR([Operand; 1])
Branch on Greater Than (signed) [{N OR Z} EQL 0]
Format: BGTR displ.bb
BLEQ([Operand; 1])
Branch on Less Than or Equal (signed) [{N OR Z} EQL 1]
Format: BLEQ displ.bb
JSB([Operand; 1])
Jump to Subroutine
Format: JSB dst.ab
JMP([Operand; 1])
Jump
Format: JMP dst.ab
BGEQ([Operand; 1])
Branch on Greater Than or Equal (signed) [N EQL 0]
Format: BGEQ displ.bb
BLSS([Operand; 1])
Branch on Less Than (signed) [N EQL 1]
Format: BLSS displ.bb
BGTRU([Operand; 1])
Branch on Greater Than (unsigned) [{C OR Z} EQL 0]
Format: BGTRU displ.bb
BLEQU([Operand; 1])
Branch on Less Than or Equal (unsigned) [{C OR Z} EQL 1]
Format: BLEQU displ.bb
BVC([Operand; 1])
Branch on Overflow Clear [V EQL 0]
Format: BVC displ.bb
BVS([Operand; 1])
Branch on Overflow Set [V EQL 1]
Format: BVS displ.bb
BGEQU([Operand; 1])
Branch on Greater Than or Equal (unsigned) [C EQL 0]
Format: BGEQU displ.bb
BLSSU([Operand; 1])
Branch on Less Than (unsigned) [C EQL 1]
Format: BLSSU displ.bb
ADDP4([Operand; 4])
Add Packed 4 Operand
Format: ADDP4 addlen.rw, addaddr.ab, sumlen.rw, sumaddr.ab
ADDP6([Operand; 6])
Add Packed 6 Operand
Format: ADDP6 add1len.rw, add1addr.ab, add2len.rw, add2addr.ab, sumlen.rw, sumaddr.ab
SUBP4([Operand; 4])
Subtract Packed 4 Operand
Format: SUBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab
SUBP6([Operand; 6])
Subtract Packed 6 Operand
Format: SUBP6 sublen.rw, subaddr.ab, minlen.rw, minaddr.ab, diflen.rw, difaddr.ab
CVTPT([Operand; 5])
Convert Packed to Trailing Numeric
Format: CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
MULP([Operand; 6])
Multiply Packed
Format: MULP mulrlen.rw, mulraddr.ab, muldlen.rw, muldaddr.ab, prodlen.rw, prodaddr.ab
CVTTP([Operand; 5])
Convert Trailing Numeric to Packed
Format: CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, dstlen.rw, dstaddr.ab
DIVP([Operand; 6])
Divide Packed
Format: DIVP divrlen.rw, divraddr.ab, divdlen.rw, divdaddr.ab, quolen.rw, quoaddr.ab
MOVC3([Operand; 3])
Move Character 3 Operand
Format: MOVC3 len.rw, srcaddr.ab, dstaddr.ab
CMPC3([Operand; 3])
Compare Characters 3 Operand
Format: CMPC3 len.rw, src1addr.ab, src2addr.ab
SCANC([Operand; 4])
Scan Characters
Format: SCANC len.rw, addr.ab, tbladdr.ab, mask.rb
SPANC([Operand; 4])
Span Characters
Format: SPANC len.rw, addr.ab, tbladdr.ab, mask.rb
MOVC5([Operand; 5])
Move Character 5 Operand
Format: MOVC5 srclen.rw, srcaddr.ab, fill.rb, dstlen.rw, dstaddr.ab
CMPC5([Operand; 5])
Compare Characters 5 Operand
Format: CMPC5 src1len.rw, src1addr.ab, fill.rb, src2len.rw, src2addr.ab
MOVTC([Operand; 6])
Move Translated Characters
Format: MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab, dstlen.rw, dstaddr.ab
MOVTUC([Operand; 6])
Move Translated Until Character
Format: MOVTUC srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab, dstlen.rw, dstaddr.ab
BSBW([Operand; 1])
Branch to Subroutine With Word Displacement
Format: BSBW displ.bw
BRW([Operand; 1])
Branch With Word Displacement
Format: BRW displ.bw
CVTWL([Operand; 2])
Convert Word to Long
Format: CVTWL src.rw, dst.wl
CVTWB([Operand; 2])
Convert Word to Byte
Format: CVTWB src.rw, dst.wb
MOVP([Operand; 3])
Move Packed
Format: MOVP len.rw, srcaddr.ab, dstaddr.ab
CMPP3([Operand; 3])
Compare Packed 3 Operand
Format: CMPP3 len.rw, src1addr.ab, src2addr.ab
CVTPL([Operand; 3])
Convert Packed to Long
Format: CVTPL srclen.rw, srcaddr.ab, dst.wl
CMPP4([Operand; 4])
Compare Packed 4 Operand
Format: CMPP4 src1len.rw, src1addr.ab, src2len.rw, src2addr.ab
EDITPC([Operand; 4])
Edit Packed to Character String
Format: EDITPC srclen.rw, srcaddr.ab, pattern.ab, dstaddr.ab
MATCHC([Operand; 4])
Match Character
Format: MATCHC objlen.rw, objaddr.ab, srclen.rw, srcaddr.ab
LOCC([Operand; 3])
Locate Character
Format: LOCC char.rb, len.rw, addr.ab
SKPC([Operand; 3])
Skip Character
Format: SKPC char.rb, len.rw, addr.ab
MOVZWL([Operand; 2])
Move Zero-Extended Word to Long
Format: MOVZWL src.rw, dst.wl
ACBW([Operand; 4])
Add Compare and Branch Word
Format: ACBW limit.rw, add.rw, index.mw, displ.bw
MOVAW([Operand; 2])
Move Address Word
Format: MOVAW src.aw, dst.wl
PUSHAW([Operand; 1])
Push Address Word
Format: PUSHAW src.aw
ADDF2([Operand; 2])
Add F_floating 2 Operand
Format: ADDF2 add.rf, sum.mf
ADDF3([Operand; 3])
Add F_floating 3 Operand
Format: ADDF3 add1.rf, add2.rf, sum.wf
SUBF2([Operand; 2])
Subtract F_floating 2 Operand
Format: SUBF2 sub.rf, dif.mf
SUBF3([Operand; 3])
Subtract F_floating 3 Operand
Format: SUBF3 sub.rf, min.rf, dif.wf
MULF2([Operand; 2])
Multiply F_floating 2 Operand
Format: MULF2 mulr.rf, prod.mf
MULF3([Operand; 3])
Multiply F_floating 3 Operand
Format: MULF3 mulr.rf, muld.rf, prod.wf
DIVF2([Operand; 2])
Divide F_floating 2 Operand
Format: DIVF2 divr.rf, quo.mf
DIVF3([Operand; 3])
Divide F_floating 3 Operand
Format: DIVF3 divr.rf, divd.rf, quo.wf
CVTFB([Operand; 2])
Convert F_floating to Byte
Format: CVTFB src.rf, dst.wb
CVTFW([Operand; 2])
Convert F_floating to Word
Format: CVTFW src.rf, dst.ww
CVTFL([Operand; 2])
Convert F_floating to Long
Format: CVTFL src.rf, dst.wl
CVTRFL([Operand; 2])
Convert Rounded F_floating to Long
Format: CVTRFL src.rf, dst.wl
CVTBF([Operand; 2])
Convert Byte to F_floating
Format: CVTBF src.rb, dst.wf
CVTWF([Operand; 2])
Convert Word to F_floating
Format: CVTWF src.rw, dst.wf
CVTLF([Operand; 2])
Convert Long to F_floating
Format: CVTLF src.rl, dst.wf
ACBF([Operand; 4])
Add Compare and Branch F_floating
Format: ACBF limit.rf, add.rf, index.mf, displ.bw
MOVF([Operand; 2])
Move F_floating
Format: MOVF src.rf, dst.wf
CMPF([Operand; 2])
Compare F_floating
Format: CMPF src1.rf, src2.rf
MNEGF([Operand; 2])
Move Negated F_floating
Format: MNEGF src.rf, dst.wf
TSTF([Operand; 1])
Test F_floating
Format: TSTF src.rf
EMODF([Operand; 5])
Extended Multiply and Integerize F_floating
Format: EMODF mulr.rf, mulrx.rb, muld.rf, int.wl, fract.wf
POLYF([Operand; 3])
Polynomial Evaluation F_floating
Format: POLYF arg.rf, degree.rw, tbladdr.ab
CVTFD([Operand; 2])
Convert F_floating to D_floating
Format: CVTFD src.rf, dst.wd
ADAWI([Operand; 2])
Add Aligned Word Interlocked
Format: ADAWI add.rw, sum.mw
INSQHI([Operand; 2])
Insert Entry into Queue at Head Interlocked
Format: INSQHI entry.ab, header.aq
INSQTI([Operand; 2])
Insert Entry into Queue at Tail Interlocked
Format: INSQTI entry.ab, header.aq
REMQHI([Operand; 2])
Remove Entry from Queue at Head Interlocked
Format: REMQHI header.aq, addr.wl
REMQTI([Operand; 2])
Remove Entry from Queue at Tail Interlocked
Format: REMQTI header.aq, addr.wl
ADDD2([Operand; 2])
Add D_floating 2 Operand
Format: ADDD2 add.rd, sum.md
ADDD3([Operand; 3])
Add D_floating 3 Operand
Format: ADDD3 add1.rd, add2.rd, sum.wd
SUBD2([Operand; 2])
Subtract D_floating 2 Operand
Format: SUBD2 sub.rd, dif.md
SUBD3([Operand; 3])
Subtract D_floating 3 Operand
Format: SUBD3 sub.rd, min.rd, dif.wd
MULD2([Operand; 2])
Multiply D_floating 2 Operand
Format: MULD2 mulr.rd, prod.md
MULD3([Operand; 3])
Multiply D_floating 3 Operand
Format: MULD3 mulr.rd, muld.rd, prod.wd
DIVD2([Operand; 2])
Divide D_floating 2 Operand
Format: DIVD2 divr.rd, quo.md
DIVD3([Operand; 3])
Divide D_floating 3 Operand
Format: DIVD3 divr.rd, divd.rd, quo.wd
CVTDB([Operand; 2])
Convert D_floating to Byte
Format: CVTDB src.rd, dst.wb
CVTDW([Operand; 2])
Convert D_floating to Word
Format: CVTDW src.rd, dst.ww
CVTDL([Operand; 2])
Convert D_floating to Long
Format: CVTDL src.rd, dst.wl
CVTRDL([Operand; 2])
Convert Rounded D_floating to Long
Format: CVTRDL src.rd, dst.wl
CVTBD([Operand; 2])
Convert Byte to D_floating
Format: CVTBD src.rb, dst.wd
CVTWD([Operand; 2])
Convert Word to D_floating
Format: CVTWD src.rw, dst.wd
CVTLD([Operand; 2])
Convert Long to D_floating
Format: CVTLD src.rl, dst.wd
ACBD([Operand; 4])
Add Compare and Branch D_floating
Format: ACBD limit.rd, add.rd, index.md, displ.bw
MOVD([Operand; 2])
Move D_floating
Format: MOVD src.rd, dst.wd
CMPD([Operand; 2])
Compare D_floating
Format: CMPD src1.rd, src2.rd
MNEGD([Operand; 2])
Move Negated D_floating
Format: MNEGD src.rd, dst.wd
TSTD([Operand; 1])
Test D_floating
Format: TSTD src.rd
EMODD([Operand; 5])
Extended Multiply and Integerize D_floating
Format: EMODD mulr.rd, mulrx.rb, muld.rd, int.wl, fract.wd
POLYD([Operand; 3])
Polynomial Evaluation D_floating
Format: POLYD arg.rd, degree.rw, tbladdr.ab
CVTDF([Operand; 2])
Convert D_floating to F_floating
Format: CVTDF src.rd, dst.wf
ASHL([Operand; 3])
Arithmetic Shift Long
Format: ASHL cnt.rb, src.rl, dst.wl
ASHQ([Operand; 3])
Arithmetic Shift Quad
Format: ASHQ cnt.rb, src.rq, dst.wq
EMUL([Operand; 4])
Extended Multiply
Format: EMUL mulr.rl, muld.rl, add.rl, prod.wq
EDIV([Operand; 4])
Extended Divide
Format: EDIV divr.rl, divd.rq, quo.wl, rem.wl
CLRQ([Operand; 1])
Clear Quad
Format: CLRQ dst.wq
MOVQ([Operand; 2])
Move Quad
Format: MOVQ src.rq, dst.wq
MOVAQ([Operand; 2])
Move Address Quad
Format: MOVAQ src.aq, dst.wl
PUSHAQ([Operand; 1])
Push Address Quad
Format: PUSHAQ src.aq
ADDB2([Operand; 2])
Add Byte 2 Operand
Format: ADDB2 add.rb, sum.mb
ADDB3([Operand; 3])
Add Byte 3 Operand
Format: ADDB3 addl.rb, add2.rb, sum.wb
SUBB2([Operand; 2])
Subtract Byte 2 Operand
Format: SUBB2 sub.rb, dif.mb
SUBB3([Operand; 3])
Subtract Byte 3 Operand
Format: SUBB3 sub.rb, min.rb, dif.wb
MULB2([Operand; 2])
Multiply Byte 2 Operand
Format: MULB2 mulr.rb, prod.mb
MULB3([Operand; 3])
Multiply Byte 3 Operand
Format: MULB3 mulr.rb, muld.rb, prod.wb
DIVB2([Operand; 2])
Divide Byte 2 Operand
Format: DIVB2 divr.rb, quo.mb
DIVB3([Operand; 3])
Divide Byte 3 Operand
Format: DIVB3 divr.rb, divd.rb, quo.wb
BISB2([Operand; 2])
Bit Set Byte 2 Operand
Format: BISB2 mask.rb, dst.mb
BISB3([Operand; 3])
Bit Set Byte 3 Operand
Format: BISB3 mask.rb, src.rb, dst.wb
BICB2([Operand; 2])
Bit Clear Byte 2 Operand
Format: BICB2 mask.rb, dst.mb
BICB3([Operand; 3])
Bit Clear Byte 3 Operand
Format: BICB3 mask.rb, src.rb, dst.wb
XORB2([Operand; 2])
Exclusive-OR Byte 2 Operand
Format: XORB2 mask.rb, dst.mb
XORB3([Operand; 3])
Exclusive-OR Byte 3 Operand
Format: XORB3 mask.rb, src.rb, dst.wb
MNEGB([Operand; 2])
Move Negated Byte
Format: MNEGB src.rb, dst.wb
CASEB([Operand; 3])
Case Byte
Format: CASEB selector.rb, base.rb, limit.rb
MOVB([Operand; 2])
Move Byte
Format: MOVB src.rb, dst.wb
CMPB([Operand; 2])
Compare Byte
Format: CMPB src1.rb, src2.rb
MCOMB([Operand; 2])
Move Complemented Byte
Format: MCOMB src.rb, dst.wb
BITB([Operand; 2])
Bit Test Byte
Format: BITB mask.rb, src.rb
CLRB([Operand; 1])
Clear Byte
Format: CLRB dst.wb
TSTB([Operand; 1])
Test Byte
Format: TSTB src.rb
INCB([Operand; 1])
Increment Byte
Format: INCB sum.mb
DECB([Operand; 1])
Decrement Byte
Format: DECB dif.mb
CVTBL([Operand; 2])
Convert Byte to Long
Format: CVTBL src.rb, dst.wl
CVTBW([Operand; 2])
Convert Byte to Word
Format: CVTBW src.rb, dst.ww
MOVZBL([Operand; 2])
Move Zero-Extended Byte to Long
Format: MOVZBL src.rb, dst.wl
MOVZBW([Operand; 2])
Move Zero-Extended Byte to Word
Format: MOVZBW src.rb, dst.ww
ROTL([Operand; 3])
Rotate Long
Format: ROTL cnt.rb, src.rl, dst.wl
ACBB([Operand; 4])
Add Compare and Branch Byte
Format: ACBB limit.rb, add.rb, index.mb, displ.bw
MOVAB([Operand; 2])
Move Address Byte
Format: MOVAB src.ab, dst.wl
PUSHAB([Operand; 1])
Push Address Byte
Format: PUSHAB src.ab
ADDW2([Operand; 2])
Add Word 2 Operand
Format: ADDW2 add.rw, sum.mw
ADDW3([Operand; 3])
Add Word 3 Operand
Format: ADDW3 addl.rw, add2.rw, sum.ww
SUBW2([Operand; 2])
Subtract Word 2 Operand
Format: SUBW2 sub.rw, dif.mw
SUBW3([Operand; 3])
Subtract Word 3 Operand
Format: SUBW3 sub.rw, min.rw, dif.ww
MULW2([Operand; 2])
Multiply Word 2 Operand
Format: MULW2 mulr.rw, prod.mw
MULW3([Operand; 3])
Multiply Word 3 Operand
Format: MULW3 mulr.rw, muld.rw, prod.ww
DIVW2([Operand; 2])
Divide Word 2 Operand
Format: DIVW2 divr.rw, quo.mw
DIVW3([Operand; 3])
Divide Word 3 Operand
Format: DIVW3 divr.rw, divd.rw, quo.ww
BISW2([Operand; 2])
Bit Set Word 2 Operand
Format: BISW2 mask.rw, dst.mw
BISW3([Operand; 3])
Bit Set Word 3 Operand
Format: BISW3 mask.rw, src.rw, dst.ww
BICW2([Operand; 2])
Bit Clear Word 2 Operand
Format: BICW2 mask.rw, dst.mw
BICW3([Operand; 3])
Bit Clear Word 3 Operand
Format: BICW3 mask.rw, src.rw, dst.ww
XORW2([Operand; 2])
Exclusive-OR Word 2 Operand
Format: XORW2 mask.rw, dst.mw
XORW3([Operand; 3])
Exclusive-OR Word 3 Operand
Format: XORW3 mask.rw, src.rw, dst.ww
MNEGW([Operand; 2])
Move Negated Word
Format: MNEGW src.rw, dst.ww
CASEW([Operand; 3])
Case Word
Format: CASEW selector.rw, base.rw, limit.rw
MOVW([Operand; 2])
Move Word
Format: MOVW src.rw, dst.ww
CMPW([Operand; 2])
Compare Word
Format: CMPW src1.rw, src2.rw
MCOMW([Operand; 2])
Move Complemented Word
Format: MCOMW src.rw, dst.ww
BITW([Operand; 2])
Bit Test Word
Format: BITW mask.rw, src.rw
CLRW([Operand; 1])
Clear Word
Format: CLRW dst.ww
TSTW([Operand; 1])
Test Word
Format: TSTW src.rw
INCW([Operand; 1])
Increment Word
Format: INCW sum.mw
DECW([Operand; 1])
Decrement Word
Format: DECW dif.mw
BISPSW([Operand; 1])
Bit Set PSW
Format: BISPSW mask.rw
BICPSW([Operand; 1])
Bit Clear PSW
Format: BICPSW mask.rw
POPR([Operand; 1])
Pop Registers
Format: POPR mask.rw
PUSHR([Operand; 1])
Push Registers
Format: PUSHR mask.rw
CHMK([Operand; 1])
Change Mode to Kernel
Format: CHMK code.rw
CHME([Operand; 1])
Change Mode to Executive
Format: CHME code.rw
CHMS([Operand; 1])
Change Mode to Supervisor
Format: CHMS code.rw
CHMU([Operand; 1])
Change Mode to User
Format: CHMU code.rw
ADDL2([Operand; 2])
Add Long 2 Operand
Format: ADDL2 add.rl, sum.ml
ADDL3([Operand; 3])
Add Long 3 Operand
Format: ADDL3 addl.rl, add2.rl, sum.wl
SUBL2([Operand; 2])
Subtract Long 2 Operand
Format: SUBL2 sub.rl, dif.ml
SUBL3([Operand; 3])
Subtract Long 3 Operand
Format: SUBL3 sub.rl, min.rl, dif.wl
MULL2([Operand; 2])
Multiply Long 2 Operand
Format: MULL2 mulr.rl, prod.ml
MULL3([Operand; 3])
Multiply Long 3 Operand
Format: MULL3 mulr.rl, muld.rl, prod.wl
DIVL2([Operand; 2])
Divide Long 2 Operand
Format: DIVL2 divr.rl, quo.ml
DIVL3([Operand; 3])
Divide Long 3 Operand
Format: DIVL3 divr.rl, divd.rl, quo.wl
BISL2([Operand; 2])
Bit Set Long 2 Operand
Format: BISL2 mask.rl, dst.ml
BISL3([Operand; 3])
Bit Set Long 3 Operand
Format: BISL3 mask.rl, src.rl, dst.wl
BICL2([Operand; 2])
Bit Clear Long 2 Operand
Format: BICL2 mask.rl, dst.ml
BICL3([Operand; 3])
Bit Clear Long 3 Operand
Format: BICL3 mask.rl, src.rl, dst.wl
XORL2([Operand; 2])
Exclusive-OR Long 2 Operand
Format: XORL2 mask.rl, dst.ml
XORL3([Operand; 3])
Exclusive-OR Long 3 Operand
Format: XORL3 mask.rl, src.rl, dst.wl
MNEGL([Operand; 2])
Move Negated Long
Format: MNEGL src.rl, dst.wl
CASEL([Operand; 3])
Case Long
Format: CASEL selector.rl, base.rl, limit.rl
MOVL([Operand; 2])
Move Long
Format: MOVL src.rl, dst.wl
CMPL([Operand; 2])
Compare Long
Format: CMPL src1.rl, src2.rl
MCOML([Operand; 2])
Move Complemented Long
Format: MCOML src.rl, dst.wl
BITL([Operand; 2])
Bit Test Long
Format: BITL mask.rl, src.rl
CLRL([Operand; 1])
Clear Long
Format: CLRL dst.wl
TSTL([Operand; 1])
Test Long
Format: TSTL src.rl
INCL([Operand; 1])
Increment Long
Format: INCL sum.ml
DECL([Operand; 1])
Decrement Long
Format: DECL dif.ml
ADWC([Operand; 2])
Add With Carry
Format: ADWC add.rl, sum.ml
SBWC([Operand; 2])
Subtract With Carry
Format: SBWC sub.rl, dif.ml
MTPR([Operand; 2])
Move To Processor Register
Format: MTPR src.rl, procreg.rl
MFPR([Operand; 2])
Move From Processor Register
Format: MFPR procreg.rl, dst.wl
MOVPSL([Operand; 1])
Move from PSL
Format: MOVPSL dst.wl
PUSHL([Operand; 1])
Push Long
Format: PUSHL src.rl
MOVAL([Operand; 2])
Move Address Long
Format: MOVAL src.al, dst.wl
PUSHAL([Operand; 1])
Push Address Long
Format: PUSHAL src.al
BBS([Operand; 3])
Branch on Bit Set
Format: BBS pos.rl, base.vb, displ.bb
BBC([Operand; 3])
Branch on Bit Clear
Format: BBC pos.rl, base.vb, displ.bb
BBSS([Operand; 3])
Branch on Bit Set and Set
Format: BBSS pos.rl, base.vb, displ.bb
BBCS([Operand; 3])
Branch on Bit Clear and Set
Format: BBCS pos.rl, base.vb, displ.bb
BBSC([Operand; 3])
Branch on Bit Set and Clear
Format: BBSC pos.rl, base.vb, displ.bb
BBCC([Operand; 3])
Branch on Bit Clear and Clear
Format: BBCC pos.rl, base.vb, displ.bb
BBSSI([Operand; 3])
Branch on Bit Set and Set Interlocked
Format: BBSSI pos.rl, base.vb, displ.bb
BBCCI([Operand; 3])
Branch on Bit Clear and Clear Interlocked
Format: BBCCI pos.rl, base.vb, displ.bb
BLBS([Operand; 2])
Branch on Low Bit Set
Format: BLBS src.rl, displ.bb
BLBC([Operand; 2])
Branch on Low Bit Clear
Format: BLBC src.rl, displ.bb
FFS([Operand; 4])
Find First Set
Format: FFS startpos.rl, size.rb, base.vb, findpos.wl
FFC([Operand; 4])
Find First Clear
Format: FFC startpos.rl, size.rb, base.vb, findpos.wl
CMPV([Operand; 4])
Compare Field
Format: CMPV pos.rl, size.rb, base.vb, src.rl
CMPZV([Operand; 4])
Compare Zero-Extended Field
Format: CMPZV pos.rl, size.rb, base.vb, src.rl
EXTV([Operand; 4])
Extract Field
Format: EXTV pos.rl, size.rb, base.vb, dst.wl
EXTZV([Operand; 4])
Extract Zero-Extended Field
Format: EXTZV pos.rl, size.rb, base.vb, dst.wl
INSV([Operand; 4])
Insert Field
Format: INSV src.rl, pos.rl, size.rb, base.vb
ACBL([Operand; 4])
Add Compare and Branch Long
Format: ACBL limit.rl, add.rl, index.ml, displ.bw
AOBLSS([Operand; 3])
Add One and Branch Less Than
Format: AOBLSS limit.rl, index.ml, displ.bb
AOBLEQ([Operand; 3])
Add One and Branch Less Than or Equal
Format: AOBLEQ limit.rl, index.ml, displ.bb
SOBGEQ([Operand; 2])
Subtract One and Branch Greater Than or Equal
Format: SOBGEQ index.ml, displ.bb
SOBGTR([Operand; 2])
Subtract One and Branch Greater Than
Format: SOBGTR index.ml, displ.bb
CVTLB([Operand; 2])
Convert Long to Byte
Format: CVTLB src.rl, dst.wb
CVTLW([Operand; 2])
Convert Long to Word
Format: CVTLW src.rl, dst.ww
ASHP([Operand; 6])
Arithmetic Shift and Round Packed
Format: ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, dstlen.rw, dstaddr.ab
CVTLP([Operand; 3])
Convert Long to Packed
Format: CVTLP src.rl, dstlen.rw, dstaddr.ab
CALLG([Operand; 2])
Call Procedure with General Argument List
Format: CALLG arglist.ab, dst.ab
CALLC([Operand; 2])
Call Procedure with Stack Argument List
Format: CALLC numarg.rl, dst.ab
XFC([Operand; 0])
Extended Function Call
Format: XFC
CVTDH([Operand; 2])
Convert D_floating to H_floating
Format: CVTDH src.rd, dst.wh
CVTGF([Operand; 2])
Convert G_floating to F_floating
Format: CVTGF src.rg, dst.wf
ADDG2([Operand; 2])
Add G_floating 2 Operand
Format: ADDG2 add.rg, sum.mg
ADDG3([Operand; 3])
Add G_floating 3 Operand
Format: ADDG3 add1.rg, add2.rg, sum.wg
SUBG2([Operand; 2])
Subtract G_floating 2 Operand
Format: SUBG2 sub.rg, dif.mg
SUBG3([Operand; 3])
Subtract G_floating 3 Operand
Format: SUBG3 sub.rg, min.rg, dif.wg
MULG2([Operand; 2])
Multiply G_floating 2 Operand
Format: MULG2 mulr.rg, prod.mg
MULG3([Operand; 3])
Multiply G_floating 3 Operand
Format: MULG3 mulr.rg, muld.rg, prod.wg
DIVG2([Operand; 2])
Divide G_floating 2 Operand
Format: DIVG2 divr.rg, quo.mg
DIVG3([Operand; 3])
Divide G_floating 3 Operand
Format: DIVG3 divr.rg, divd.rg, quo.wg
CVTGB([Operand; 2])
Convert G_floating to Byte
Format: CVTGB src.rg, dst.wb
CVTGW([Operand; 2])
Convert G_floating to Word
Format: CVTGW src.rg, dst.ww
CVTGL([Operand; 2])
Convert G_floating to Long
Format: CVTGL src.rg, dst.wl
CVTRGL([Operand; 2])
Convert Rounded G_floating to Long
Format: CVTRGL src.rg, dst.wl
CVTBG([Operand; 2])
Convert Byte to G_floating
Format: CVTBG src.rb, dst.wg
CVTWG([Operand; 2])
Convert Word to G_floating
Format: CVTWG src.rw, dst.wg
CVTLG([Operand; 2])
Convert Long to G_floating
Format: CVTLG src.rl, dst.wg
ACBG([Operand; 4])
Add Compare and Branch G_floating
Format: ACBG limit.rg, add.rg, index.mg, displ.bw
MOVG([Operand; 2])
Move G_floating
Format: MOVG src.rg, dst.wg
CMPG([Operand; 2])
Compare G_floating
Format: CMPG src1.rg, src2.rg
MNEGG([Operand; 2])
Move Negated G_floating
Format: MNEGG src.rg, dst.wg
TSTG([Operand; 1])
Test G_floating
Format: TSTG src.rg
EMODG([Operand; 5])
Extended Multiply and Integerize G_floating
Format: EMODG mulr.rg, mulrx.rw, muld.rg, int.wl, fract.wg
POLYG([Operand; 3])
Polynomial Evaluation G_floating
Format: POLYG arg.rg, degree.rw, tbladdr.ab
CVTGH([Operand; 2])
Convert G_floating to H_floating
Format: CVTGH src.rg, dst.wh
ADDH2([Operand; 2])
Add H_floating 2 Operand
Format: ADDH2 add.rh, sum.mh
ADDH3([Operand; 3])
Add H_floating 3 Operand
Format: ADDH3 add1.rh, add2.rh, sum.wh
SUBH2([Operand; 2])
Subtract H_floating 2 Operand
Format: SUBH2 sub.rh, dif.mh
SUBH3([Operand; 3])
Subtract H_floating 3 Operand
Format: SUBH3 sub.rh, min.rh, dif.wh
MULH2([Operand; 2])
Multiply H_floating 2 Operand
Format: MULH2 mulr.rh, prod.mh
MULH3([Operand; 3])
Multiply H_floating 3 Operand
Format: MULH3 mulr.rh, muld.rh, prod.wh
DIVH2([Operand; 2])
Divide H_floating 2 Operand
Format: DIVH2 divr.rh, quo.mh
DIVH3([Operand; 3])
Divide H_floating 3 Operand
Format: DIVH3 divr.rh, divd.rh, quo.wh
CVTHB([Operand; 2])
Convert H_floating to Byte
Format: CVTHB src.rh, dst.wb
CVTHW([Operand; 2])
Convert H_floating to Word
Format: CVTHW src.rh, dst.ww
CVTHL([Operand; 2])
Convert H_floating to Long
Format: CVTHL src.rh, dst.wl
CVTRHL([Operand; 2])
Convert Rounded H_floating to Long
Format: CVTRHL src.rh, dst.wl
CVTBH([Operand; 2])
Convert Byte to H_floating
Format: CVTBH src.rb, dst.wh
CVTWH([Operand; 2])
Convert Word to H_floating
Format: CVTWH src.rw, dst.wh
CVTLH([Operand; 2])
Convert Long to H_floating
Format: CVTLH src.rl, dst.wh
ACBH([Operand; 4])
Add Compare and Branch H_floating
Format: ACBH limit.rh, add.rh, index.mh, displ.bw
MOVH([Operand; 2])
Move H_floating
Format: MOVH src.rh, dst.wh
CMPH([Operand; 2])
Compare H_floating
Format: CMPH src1.rh, src2.rh
MNEGH([Operand; 2])
Move Negated H_floating
Format: MNEGH src.rh, dst.wh
TSTH([Operand; 1])
Test H_floating
Format: TSTH src.rh
EMODH([Operand; 5])
Extended Multiply and Integerize H_floating
Format: EMODH mulr.rh, mulrx.rw, muld.rh, int.wl, fract.wh
POLYH([Operand; 3])
Polynomial Evaluation H_floating
Format: POLYH arg.rh, degree.rw, tbladdr.ab
CVTHG([Operand; 2])
Convert H_floating to G_floating
Format: CVTHG src.rh, dst.wg
CLRO([Operand; 1])
Clear Octa
Format: CLRO dst.wo
MOVO([Operand; 2])
Move Octa
Format: MOVO src.ro, dst.wo
MOVAO([Operand; 2])
Move Address Octa
Format: MOVAO src.ao, dst.wl
PUSHAO([Operand; 1])
Push Address Octa
Format: PUSHAO src.ao
CVTFH([Operand; 2])
Convert F_floating to H_floating
Format: CVTFH src.rf, dst.wh
CVTFG([Operand; 2])
Convert F_floating to G_floating
Format: CVTFG src.rf, dst.wg
CVTHF([Operand; 2])
Convert H_floating to F_floating
Format: CVTHF src.rh, dst.wf
CVTHD([Operand; 2])
Convert H_floating to D_floating
Format: CVTHD src.rh, dst.wd
BUGL([Operand; 1])
Bugcheck with Longword Message Identifier
Format: BUGL message.bw
BUGW([Operand; 1])
Bugcheck with Word Message Identifier
Format: BUGW message.bl
BNEQU([Operand; 1])
BEQLU([Operand; 1])
BCC([Operand; 1])
BCS([Operand; 1])
CLRD([Operand; 1])
CLRG([Operand; 1])
MOVAD([Operand; 2])
MOVAG([Operand; 2])
PUSHAD([Operand; 1])
PUSHAG([Operand; 1])
CLRH([Operand; 1])
MOVAH([Operand; 2])
PUSHAH([Operand; 1])
Implementations§
Source§impl Instruction
impl Instruction
Sourcepub fn operands(&self) -> &[Operand]
pub fn operands(&self) -> &[Operand]
Return a slice with all of the operands for this instruction.
§Examples
use vax_disassembler::opcode::{Instruction, Opcode};
use vax_disassembler::operand::{Operand, Register};
// MOVC5 R0, (R1), S^#^A/ /, R2, (R3)
let instruction = Instruction::MOVC5([
Operand::Register(Register::R0),
Operand::RegisterDeferred(Register::R1),
Operand::Literal(b' '),
Operand::Register(Register::R2),
Operand::RegisterDeferred(Register::R3),
]);
let mut operands = instruction.operands().iter();
assert_eq!(operands.next().unwrap(), &Operand::Register(Register::R0));
assert_eq!(operands.next().unwrap(), &Operand::RegisterDeferred(Register::R1));
assert_eq!(operands.next().unwrap(), &Operand::Literal(b' '));
assert_eq!(operands.next().unwrap(), &Operand::Register(Register::R2));
assert_eq!(operands.next().unwrap(), &Operand::RegisterDeferred(Register::R3));
assert!(operands.next().is_none());Trait Implementations§
Source§impl Clone for Instruction
impl Clone for Instruction
Source§fn clone(&self) -> Instruction
fn clone(&self) -> Instruction
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreSource§impl Debug for Instruction
impl Debug for Instruction
Source§impl Display for Instruction
impl Display for Instruction
Source§fn fmt(&self, f: &mut Formatter<'_>) -> Result
fn fmt(&self, f: &mut Formatter<'_>) -> Result
Formats the value using the given formatter.
§Examples
use vax_disassembler::opcode::{Instruction, Opcode};
use vax_disassembler::operand::{Operand, Register};
assert_eq!(&format!("{}", Instruction::NOP([])), "NOP");
assert_eq!(
&format!("{}", Instruction::MOVC5([
Operand::Register(Register::R0),
Operand::RegisterDeferred(Register::R1),
Operand::Literal(b' '),
Operand::Register(Register::R2),
Operand::RegisterDeferred(Register::R3),
])),
"MOVC5 R0, (R1), S^#32, R2, (R3)"
);