Enum RegisterTRICORE 

#[repr(u32)]
pub enum RegisterTRICORE {
    INVALID = 0,
    A0 = 1,
    A1 = 2,
    A2 = 3,
    A3 = 4,
    A4 = 5,
    A5 = 6,
    A6 = 7,
    A7 = 8,
    A8 = 9,
    A9 = 10,
    A10 = 11,
    A11 = 12,
    A12 = 13,
    A13 = 14,
    A14 = 15,
    A15 = 16,
    D0 = 17,
    D1 = 18,
    D2 = 19,
    D3 = 20,
    D4 = 21,
    D5 = 22,
    D6 = 23,
    D7 = 24,
    D8 = 25,
    D9 = 26,
    D10 = 27,
    D11 = 28,
    D12 = 29,
    D13 = 30,
    D14 = 31,
    D15 = 32,
    PCXI = 33,
    PSW = 34,
    PSW_USB_C = 35,
    PSW_USB_V = 36,
    PSW_USB_SV = 37,
    PSW_USB_AV = 38,
    PSW_USB_SAV = 39,
    PC = 40,
    SYSCON = 41,
    CPU_ID = 42,
    BIV = 43,
    BTV = 44,
    ISP = 45,
    ICR = 46,
    FCX = 47,
    LCX = 48,
    COMPAT = 49,
    DPR0_U = 50,
    DPR1_U = 51,
    DPR2_U = 52,
    DPR3_U = 53,
    DPR0_L = 54,
    DPR1_L = 55,
    DPR2_L = 56,
    DPR3_L = 57,
    CPR0_U = 58,
    CPR1_U = 59,
    CPR2_U = 60,
    CPR3_U = 61,
    CPR0_L = 62,
    CPR1_L = 63,
    CPR2_L = 64,
    CPR3_L = 65,
    DPM0 = 66,
    DPM1 = 67,
    DPM2 = 68,
    DPM3 = 69,
    CPM0 = 70,
    CPM1 = 71,
    CPM2 = 72,
    CPM3 = 73,
    MMU_CON = 74,
    MMU_ASI = 75,
    MMU_TVA = 76,
    MMU_TPA = 77,
    MMU_TPX = 78,
    MMU_TFA = 79,
    BMACON = 80,
    SMACON = 81,
    DIEAR = 82,
    DIETR = 83,
    CCDIER = 84,
    MIECON = 85,
    PIEAR = 86,
    PIETR = 87,
    CCPIER = 88,
    DBGSR = 89,
    EXEVT = 90,
    CREVT = 91,
    SWEVT = 92,
    TR0EVT = 93,
    TR1EVT = 94,
    DMS = 95,
    DCX = 96,
    DBGTCR = 97,
    CCTRL = 98,
    CCNT = 99,
    ICNT = 100,
    M1CNT = 101,
    M2CNT = 102,
    M3CNT = 103,
    ENDING = 104,
}

Variants

INVALID = 0

A0 = 1

A1 = 2

A2 = 3

A3 = 4

A4 = 5

A5 = 6

A6 = 7

A7 = 8

A8 = 9

A9 = 10

A10 = 11

A11 = 12

A12 = 13

A13 = 14

A14 = 15

A15 = 16

D0 = 17

D1 = 18

D2 = 19

D3 = 20

D4 = 21

D5 = 22

D6 = 23

D7 = 24

D8 = 25

D9 = 26

D10 = 27

D11 = 28

D12 = 29

D13 = 30

D14 = 31

D15 = 32

PCXI = 33

PSW = 34

PSW_USB_C = 35

PSW_USB_V = 36

PSW_USB_SV = 37

PSW_USB_AV = 38

PSW_USB_SAV = 39

PC = 40

SYSCON = 41

CPU_ID = 42

BIV = 43

BTV = 44

ISP = 45

ICR = 46

FCX = 47

LCX = 48

COMPAT = 49

DPR0_U = 50

DPR1_U = 51

DPR2_U = 52

DPR3_U = 53

DPR0_L = 54

DPR1_L = 55

DPR2_L = 56

DPR3_L = 57

CPR0_U = 58

CPR1_U = 59

CPR2_U = 60

CPR3_U = 61

CPR0_L = 62

CPR1_L = 63

CPR2_L = 64

CPR3_L = 65

DPM0 = 66

DPM1 = 67

DPM2 = 68

DPM3 = 69

CPM0 = 70

CPM1 = 71

CPM2 = 72

CPM3 = 73

MMU_CON = 74

MMU_ASI = 75

MMU_TVA = 76

MMU_TPA = 77

MMU_TPX = 78

MMU_TFA = 79

BMACON = 80

SMACON = 81

DIEAR = 82

DIETR = 83

CCDIER = 84

MIECON = 85

PIEAR = 86

PIETR = 87

CCPIER = 88

DBGSR = 89

EXEVT = 90

CREVT = 91

SWEVT = 92

TR0EVT = 93

TR1EVT = 94

DMS = 95

DCX = 96

DBGTCR = 97

CCTRL = 98

CCNT = 99

ICNT = 100

M1CNT = 101

M2CNT = 102

M3CNT = 103

ENDING = 104

Implementations

impl RegisterTRICORE

pub const GA0: RegisterTRICORE = RegisterTRICORE::A0

impl RegisterTRICORE

pub const GA1: RegisterTRICORE = RegisterTRICORE::A1

impl RegisterTRICORE

pub const GA8: RegisterTRICORE = RegisterTRICORE::A8

impl RegisterTRICORE

pub const GA9: RegisterTRICORE = RegisterTRICORE::A9

impl RegisterTRICORE

pub const SP: RegisterTRICORE = RegisterTRICORE::A10

impl RegisterTRICORE

pub const LR: RegisterTRICORE = RegisterTRICORE::A11

impl RegisterTRICORE

pub const IA: RegisterTRICORE = RegisterTRICORE::A15

impl RegisterTRICORE

pub const ID: RegisterTRICORE = RegisterTRICORE::D15

Trait Implementations

impl Clone for RegisterTRICORE

fn clone(&self) -> RegisterTRICORE

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RegisterTRICORE

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<RegisterTRICORE> for i32

fn from(value: RegisterTRICORE) -> Self

Converts to this type from the input type.

impl Hash for RegisterTRICORE

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for RegisterTRICORE

fn cmp(&self, other: &RegisterTRICORE) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized,

Restrict a value to a certain interval.

impl PartialEq for RegisterTRICORE

fn eq(&self, other: &RegisterTRICORE) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for RegisterTRICORE

fn partial_cmp(&self, other: &RegisterTRICORE) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for RegisterTRICORE

impl Eq for RegisterTRICORE

impl StructuralPartialEq for RegisterTRICORE